1 /*
2 * Copyright (c) 2014 Brian Swetland
3 * Copyright (c) 2014 Travis Geiselbrecht
4 *
5 * Use of this source code is governed by a MIT-style
6 * license that can be found in the LICENSE file or at
7 * https://opensource.org/licenses/MIT
8 */
9 #include <dev/qspi.h>
10
11 #include <lk/debug.h>
12 #include <assert.h>
13 #include <lk/compiler.h>
14 #include <printf.h>
15 #include <string.h>
16 #include <lk/reg.h>
17
18 #include <lk/console_cmd.h>
19
20 #include <platform/zynq.h>
21
22 #define QSPI_CONFIG 0xE000D000
23 #define CFG_IFMODE (1 << 31) // Inteligent Flash Mode
24 #define CFG_LITTLE_ENDIAN (0 << 26)
25 #define CFG_BIG_ENDIAN (1 << 26)
26 #define CFG_HOLDB_DR (1 << 19) // set to 1 for dual/quad spi mode
27 #define CFG_NO_MODIFY_MASK (1 << 17) // do not modify this bit
28 #define CFG_MANUAL_START (1 << 16) // start transaction
29 #define CFG_MANUAL_START_EN (1 << 15) // enable manual start mode
30 #define CFG_MANUAL_CS_EN (1 << 14) // enable manual CS control
31 #define CFG_MANUAL_CS (1 << 10) // directly drives n_ss_out if MANUAL_CS_EN==1
32 #define CFG_FIFO_WIDTH_32 (3 << 6) // only valid setting
33 #define CFG_BAUD_MASK (7 << 3)
34 #define CFG_BAUD_DIV_2 (0 << 3)
35 #define CFG_BAUD_DIV_4 (1 << 3)
36 #define CFG_BAUD_DIV_8 (2 << 3)
37 #define CFG_BAUD_DIV_16 (3 << 3)
38 #define CFG_CPHA (1 << 2) // clock phase
39 #define CFG_CPOL (1 << 1) // clock polarity
40 #define CFG_MASTER_MODE (1 << 0) // only valid setting
41
42 #define QSPI_IRQ_STATUS 0xE000D004 // ro status (write UNDERFLOW/OVERFLOW to clear)
43 #define QSPI_IRQ_ENABLE 0xE000D008 // write 1s to set mask bits
44 #define QSPI_IRQ_DISABLE 0xE000D00C // write 1s to clear mask bits
45 #define QSPI_IRQ_MASK 0xE000D010 // ro mask value (1 = irq enabled)
46 #define TX_UNDERFLOW (1 << 6)
47 #define RX_FIFO_FULL (1 << 5)
48 #define RX_FIFO_NOT_EMPTY (1 << 4)
49 #define TX_FIFO_FULL (1 << 3)
50 #define TX_FIFO_NOT_FULL (1 << 2)
51 #define RX_OVERFLOW (1 << 0)
52
53 #define QSPI_ENABLE 0xE000D014 // write 1 to enable
54
55 #define QSPI_DELAY 0xE000D018
56 #define QSPI_TXD0 0xE000D01C
57 #define QSPI_RXDATA 0xE000D020
58 #define QSPI_SLAVE_IDLE_COUNT 0xE000D024
59 #define QSPI_TX_THRESHOLD 0xE000D028
60 #define QSPI_RX_THRESHOLD 0xE000D02C
61 #define QSPI_GPIO 0xE000D030
62 #define QSPI_LPBK_DLY_ADJ 0xE000D038
63 #define QSPI_TXD1 0xE000D080
64 #define QSPI_TXD2 0xE000D084
65 #define QSPI_TXD3 0xE000D088
66
67 #define QSPI_LINEAR_CONFIG 0xE000D0A0
68 #define LCFG_ENABLE (1 << 31) // enable linear quad spi mode
69 #define LCFG_TWO_MEM (1 << 30)
70 #define LCFG_SEP_BUS (1 << 29) // 0=shared 1=separate
71 #define LCFG_U_PAGE (1 << 28)
72 #define LCFG_MODE_EN (1 << 25) // send mode bits (required for dual/quad io)
73 #define LCFG_MODE_ON (1 << 24) // only send instruction code for first read
74 #define LCFG_MODE_BITS(n) (((n) & 0xFF) << 16)
75 #define LCFG_DUMMY_BYTES(n) (((n) & 7) << 8)
76 #define LCFG_INST_CODE(n) ((n) & 0xFF)
77
78 #define QSPI_LINEAR_STATUS 0xE000D0A4
79 #define QSPI_MODULE_ID 0xE000D0FC
80
qspi_set_speed(struct qspi_ctxt * qspi,uint32_t khz)81 int qspi_set_speed(struct qspi_ctxt *qspi, uint32_t khz) {
82 uint32_t n;
83
84 if (khz >= 100000) {
85 n = CFG_BAUD_DIV_2;
86 khz = 100000;
87 } else if (khz >= 50000) {
88 n = CFG_BAUD_DIV_4;
89 khz = 50000;
90 } else if (khz >= 25000) {
91 n = CFG_BAUD_DIV_8;
92 khz = 25000;
93 } else {
94 return -1;
95 }
96
97 if (khz == qspi->khz)
98 return 0;
99
100 qspi->khz = khz;
101
102 writel(0, QSPI_ENABLE);
103 if (n == CFG_BAUD_DIV_2) {
104 writel(0x20, QSPI_LPBK_DLY_ADJ);
105 } else {
106 writel(0, QSPI_LPBK_DLY_ADJ);
107 }
108
109 qspi->cfg &= ~CFG_BAUD_MASK;
110 qspi->cfg |= n;
111
112 writel(qspi->cfg, QSPI_CONFIG);
113 writel(1, QSPI_ENABLE);
114
115 return 0;
116 }
117
qspi_init(struct qspi_ctxt * qspi,uint32_t khz)118 int qspi_init(struct qspi_ctxt *qspi, uint32_t khz) {
119 writel(0, QSPI_ENABLE);
120 writel(0, QSPI_LINEAR_CONFIG);
121
122 // flush rx fifo
123 while (readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY)
124 readl(QSPI_RXDATA);
125
126 qspi->cfg = (readl(QSPI_CONFIG) & CFG_NO_MODIFY_MASK) |
127 CFG_IFMODE |
128 CFG_HOLDB_DR |
129 CFG_FIFO_WIDTH_32 |
130 CFG_CPHA | CFG_CPOL |
131 CFG_MASTER_MODE |
132 CFG_BAUD_DIV_2 |
133 CFG_MANUAL_START_EN | CFG_MANUAL_CS_EN | CFG_MANUAL_CS;
134
135 writel(qspi->cfg, QSPI_CONFIG);
136 qspi->khz = 100000;
137 qspi->linear_mode = false;
138
139 writel(1, QSPI_ENABLE);
140
141 // clear sticky irqs
142 writel(TX_UNDERFLOW | RX_OVERFLOW, QSPI_IRQ_STATUS);
143
144 return 0;
145 }
146
qspi_enable_linear(struct qspi_ctxt * qspi)147 int qspi_enable_linear(struct qspi_ctxt *qspi) {
148 if (qspi->linear_mode)
149 return 0;
150
151 /* disable the controller */
152 writel(0, QSPI_ENABLE);
153 writel(0, QSPI_LINEAR_CONFIG);
154
155 /* put the controller in auto chip select mode and assert chip select */
156 qspi->cfg &= ~(CFG_MANUAL_START_EN | CFG_MANUAL_CS_EN | CFG_MANUAL_CS);
157 writel(qspi->cfg, QSPI_CONFIG);
158
159 #if 1
160 // uses Quad I/O mode
161 // should be 0x82FF02EB according to xilinx manual for spansion flashes
162 writel(LCFG_ENABLE |
163 LCFG_MODE_EN |
164 LCFG_MODE_BITS(0xff) |
165 LCFG_DUMMY_BYTES(2) |
166 LCFG_INST_CODE(0xeb),
167 QSPI_LINEAR_CONFIG);
168 #else
169 // uses Quad Output Read mode
170 // should be 0x8000016B according to xilinx manual for spansion flashes
171 writel(LCFG_ENABLE |
172 LCFG_MODE_BITS(0) |
173 LCFG_DUMMY_BYTES(1) |
174 LCFG_INST_CODE(0x6b),
175 QSPI_LINEAR_CONFIG);
176 #endif
177
178 /* enable the controller */
179 writel(1, QSPI_ENABLE);
180
181 qspi->linear_mode = true;
182
183 DSB;
184
185 return 0;
186 }
187
qspi_disable_linear(struct qspi_ctxt * qspi)188 int qspi_disable_linear(struct qspi_ctxt *qspi) {
189 if (!qspi->linear_mode)
190 return 0;
191
192 /* disable the controller */
193 writel(0, QSPI_ENABLE);
194 writel(0, QSPI_LINEAR_CONFIG);
195
196 /* put the controller back into manual chip select mode */
197 qspi->cfg |= (CFG_MANUAL_START_EN | CFG_MANUAL_CS_EN | CFG_MANUAL_CS);
198 writel(qspi->cfg, QSPI_CONFIG);
199
200 /* enable the controller */
201 writel(1, QSPI_ENABLE);
202
203 qspi->linear_mode = false;
204
205 DSB;
206
207 return 0;
208 }
209
qspi_cs(struct qspi_ctxt * qspi,unsigned int cs)210 void qspi_cs(struct qspi_ctxt *qspi, unsigned int cs) {
211 DEBUG_ASSERT(cs <= 1);
212
213 if (cs == 0)
214 qspi->cfg &= ~(CFG_MANUAL_CS);
215 else
216 qspi->cfg |= CFG_MANUAL_CS;
217 writel(qspi->cfg, QSPI_CONFIG);
218 }
219
qspi_xmit(struct qspi_ctxt * qspi)220 static inline void qspi_xmit(struct qspi_ctxt *qspi) {
221 // start txn
222 writel(qspi->cfg | CFG_MANUAL_START, QSPI_CONFIG);
223
224 // wait for command to transmit and TX fifo to be empty
225 while ((readl(QSPI_IRQ_STATUS) & TX_FIFO_NOT_FULL) == 0) ;
226 }
227
qspi_flush_rx(void)228 static inline void qspi_flush_rx(void) {
229 while (!(readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY)) ;
230 readl(QSPI_RXDATA);
231 }
232
233 static const uint32_t TXFIFO[] = { QSPI_TXD1, QSPI_TXD2, QSPI_TXD3, QSPI_TXD0, QSPI_TXD0, QSPI_TXD0 };
234
qspi_rd(struct qspi_ctxt * qspi,uint32_t cmd,uint32_t asize,uint32_t * data,uint32_t count)235 void qspi_rd(struct qspi_ctxt *qspi, uint32_t cmd, uint32_t asize, uint32_t *data, uint32_t count) {
236 uint32_t sent = 0;
237 uint32_t rcvd = 0;
238
239 DEBUG_ASSERT(qspi);
240 DEBUG_ASSERT(asize < 6);
241
242 qspi_cs(qspi, 0);
243
244 writel(cmd, TXFIFO[asize]);
245 qspi_xmit(qspi);
246
247 if (asize == 4) { // dummy byte
248 writel(0, QSPI_TXD1);
249 qspi_xmit(qspi);
250 qspi_flush_rx();
251 }
252
253 qspi_flush_rx();
254
255 while (rcvd < count) {
256 while (readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY) {
257 *data++ = readl(QSPI_RXDATA);
258 rcvd++;
259 }
260 while ((readl(QSPI_IRQ_STATUS) & TX_FIFO_NOT_FULL) && (sent < count)) {
261 writel(0, QSPI_TXD0);
262 sent++;
263 }
264 qspi_xmit(qspi);
265 }
266 qspi_cs(qspi, 1);
267 }
268
qspi_wr(struct qspi_ctxt * qspi,uint32_t cmd,uint32_t asize,uint32_t * data,uint32_t count)269 void qspi_wr(struct qspi_ctxt *qspi, uint32_t cmd, uint32_t asize, uint32_t *data, uint32_t count) {
270 uint32_t sent = 0;
271 uint32_t rcvd = 0;
272
273 DEBUG_ASSERT(qspi);
274 DEBUG_ASSERT(asize < 6);
275
276 qspi_cs(qspi, 0);
277
278 writel(cmd, TXFIFO[asize]);
279 qspi_xmit(qspi);
280
281 if (asize == 4) { // dummy byte
282 writel(0, QSPI_TXD1);
283 qspi_xmit(qspi);
284 qspi_flush_rx();
285 }
286
287 qspi_flush_rx();
288
289 while (rcvd < count) {
290 while (readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY) {
291 readl(QSPI_RXDATA); // discard
292 rcvd++;
293 }
294 while ((readl(QSPI_IRQ_STATUS) & TX_FIFO_NOT_FULL) && (sent < count)) {
295 writel(*data++, QSPI_TXD0);
296 sent++;
297 }
298 qspi_xmit(qspi);
299 }
300
301 qspi_cs(qspi, 1);
302 }
303
qspi_wr1(struct qspi_ctxt * qspi,uint32_t cmd)304 void qspi_wr1(struct qspi_ctxt *qspi, uint32_t cmd) {
305 DEBUG_ASSERT(qspi);
306
307 qspi_cs(qspi, 0);
308 writel(cmd, QSPI_TXD1);
309 qspi_xmit(qspi);
310
311 while (!(readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY)) ;
312
313 readl(QSPI_RXDATA);
314 qspi_cs(qspi, 1);
315 }
316
qspi_wr2(struct qspi_ctxt * qspi,uint32_t cmd)317 void qspi_wr2(struct qspi_ctxt *qspi, uint32_t cmd) {
318 DEBUG_ASSERT(qspi);
319
320 qspi_cs(qspi, 0);
321 writel(cmd, QSPI_TXD2);
322 qspi_xmit(qspi);
323
324 while (!(readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY)) ;
325
326 readl(QSPI_RXDATA);
327 qspi_cs(qspi, 1);
328 }
329
qspi_wr3(struct qspi_ctxt * qspi,uint32_t cmd)330 void qspi_wr3(struct qspi_ctxt *qspi, uint32_t cmd) {
331 DEBUG_ASSERT(qspi);
332
333 qspi_cs(qspi, 0);
334 writel(cmd, QSPI_TXD3);
335 qspi_xmit(qspi);
336
337 while (!(readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY)) ;
338
339 readl(QSPI_RXDATA);
340 qspi_cs(qspi, 1);
341 }
342
qspi_rd1(struct qspi_ctxt * qspi,uint32_t cmd)343 uint32_t qspi_rd1(struct qspi_ctxt *qspi, uint32_t cmd) {
344 qspi_cs(qspi, 0);
345 writel(cmd, QSPI_TXD2);
346 qspi_xmit(qspi);
347
348 while (!(readl(QSPI_IRQ_STATUS) & RX_FIFO_NOT_EMPTY)) ;
349
350 qspi_cs(qspi, 1);
351 return readl(QSPI_RXDATA);
352 }
353