1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * R-Car Display Unit Channels Pair
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10 /*
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
13 * control, planes, ...) shared between the two CRTCs.
14 *
15 * The R8A7790 introduced a third CRTC with its own set of global resources.
16 * This would be modeled as two separate DU device instances if it wasn't for
17 * a handful or resources that are shared between the three CRTCs (mostly
18 * related to input and output routing). For this reason the R8A7790 DU must be
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
21 *
22 * The rcar_du_group object is a driver specific object, without any real
23 * counterpart in the DU documentation, that models those semi-global resources.
24 */
25
26 #include <linux/clk.h>
27 #include <linux/io.h>
28
29 #include "rcar_du_drv.h"
30 #include "rcar_du_group.h"
31 #include "rcar_du_regs.h"
32
rcar_du_group_read(struct rcar_du_group * rgrp,u32 reg)33 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
34 {
35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
36 }
37
rcar_du_group_write(struct rcar_du_group * rgrp,u32 reg,u32 data)38 void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
39 {
40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
41 }
42
rcar_du_group_setup_pins(struct rcar_du_group * rgrp)43 static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
44 {
45 u32 defr6 = DEFR6_CODE;
46
47 if (rgrp->channels_mask & BIT(0))
48 defr6 |= DEFR6_ODPM02_DISP;
49
50 if (rgrp->channels_mask & BIT(1))
51 defr6 |= DEFR6_ODPM12_DISP;
52
53 rcar_du_group_write(rgrp, DEFR6, defr6);
54 }
55
rcar_du_group_setup_defr8(struct rcar_du_group * rgrp)56 static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
57 {
58 struct rcar_du_device *rcdu = rgrp->dev;
59 u32 defr8 = DEFR8_CODE;
60
61 if (rcdu->info->gen < 3) {
62 defr8 |= DEFR8_DEFE8;
63
64 /*
65 * On Gen2 the DEFR8 register for the first group also controls
66 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
67 * DU instances that support it.
68 */
69 if (rgrp->index == 0) {
70 defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
71 if (rgrp->dev->vspd1_sink == 2)
72 defr8 |= DEFR8_VSCS;
73 }
74 } else {
75 /*
76 * On Gen3 VSPD routing can't be configured, and DPAD routing
77 * is set in the group corresponding to the DPAD output (no Gen3
78 * SoC has multiple DPAD sources belonging to separate groups).
79 */
80 if (rgrp->index == rcdu->dpad0_source / 2)
81 defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
82 }
83
84 rcar_du_group_write(rgrp, DEFR8, defr8);
85 }
86
rcar_du_group_setup_didsr(struct rcar_du_group * rgrp)87 static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
88 {
89 struct rcar_du_device *rcdu = rgrp->dev;
90 struct rcar_du_crtc *rcrtc;
91 unsigned int num_crtcs = 0;
92 unsigned int i;
93 u32 didsr;
94
95 /*
96 * Configure input dot clock routing with a hardcoded configuration. If
97 * the DU channel can use the LVDS encoder output clock as the dot
98 * clock, do so. Otherwise route DU_DOTCLKINn signal to DUn.
99 *
100 * Each channel can then select between the dot clock configured here
101 * and the clock provided by the CPG through the ESCR register.
102 */
103 if (rcdu->info->gen < 3 && rgrp->index == 0) {
104 /*
105 * On Gen2 a single register in the first group controls dot
106 * clock selection for all channels.
107 */
108 rcrtc = rcdu->crtcs;
109 num_crtcs = rcdu->num_crtcs;
110 } else if (rcdu->info->gen >= 3 && rgrp->num_crtcs > 1) {
111 /*
112 * On Gen3 dot clocks are setup through per-group registers,
113 * only available when the group has two channels.
114 */
115 rcrtc = &rcdu->crtcs[rgrp->index * 2];
116 num_crtcs = rgrp->num_crtcs;
117 }
118
119 if (!num_crtcs)
120 return;
121
122 didsr = DIDSR_CODE;
123 for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
124 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
125 didsr |= DIDSR_LDCS_LVDS0(i)
126 | DIDSR_PDCS_CLK(i, 0);
127 else if (rcdu->info->dsi_clk_mask & BIT(rcrtc->index))
128 didsr |= DIDSR_LDCS_DSI(i);
129 else
130 didsr |= DIDSR_LDCS_DCLKIN(i)
131 | DIDSR_PDCS_CLK(i, 0);
132 }
133
134 rcar_du_group_write(rgrp, DIDSR, didsr);
135 }
136
rcar_du_group_setup(struct rcar_du_group * rgrp)137 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
138 {
139 struct rcar_du_device *rcdu = rgrp->dev;
140 u32 defr7 = DEFR7_CODE;
141
142 /* Enable extended features */
143 rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
144 if (rcdu->info->gen < 3) {
145 rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
146 rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
147 rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
148 }
149 rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
150
151 if (rcdu->info->gen < 4)
152 rcar_du_group_setup_pins(rgrp);
153
154 if (rcdu->info->gen < 4) {
155 /*
156 * TODO: Handle routing of the DU output to CMM dynamically, as
157 * we should bypass CMM completely when no color management
158 * feature is used.
159 */
160 defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |
161 (rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);
162 rcar_du_group_write(rgrp, DEFR7, defr7);
163 }
164
165 if (rcdu->info->gen >= 2) {
166 if (rcdu->info->gen < 4)
167 rcar_du_group_setup_defr8(rgrp);
168 rcar_du_group_setup_didsr(rgrp);
169 }
170
171 if (rcdu->info->gen >= 3)
172 rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
173
174 /*
175 * Use DS1PR and DS2PR to configure planes priorities and connects the
176 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
177 */
178 rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
179
180 /* Apply planes to CRTCs association. */
181 mutex_lock(&rgrp->lock);
182 rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
183 rgrp->dptsr_planes);
184 mutex_unlock(&rgrp->lock);
185 }
186
187 /*
188 * rcar_du_group_get - Acquire a reference to the DU channels group
189 *
190 * Acquiring the first reference setups core registers. A reference must be held
191 * before accessing any hardware registers.
192 *
193 * This function must be called with the DRM mode_config lock held.
194 *
195 * Return 0 in case of success or a negative error code otherwise.
196 */
rcar_du_group_get(struct rcar_du_group * rgrp)197 int rcar_du_group_get(struct rcar_du_group *rgrp)
198 {
199 if (rgrp->use_count)
200 goto done;
201
202 rcar_du_group_setup(rgrp);
203
204 done:
205 rgrp->use_count++;
206 return 0;
207 }
208
209 /*
210 * rcar_du_group_put - Release a reference to the DU
211 *
212 * This function must be called with the DRM mode_config lock held.
213 */
rcar_du_group_put(struct rcar_du_group * rgrp)214 void rcar_du_group_put(struct rcar_du_group *rgrp)
215 {
216 --rgrp->use_count;
217 }
218
__rcar_du_group_start_stop(struct rcar_du_group * rgrp,bool start)219 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
220 {
221 struct rcar_du_device *rcdu = rgrp->dev;
222
223 /*
224 * Group start/stop is controlled by the DRES and DEN bits of DSYSR0
225 * for the first group and DSYSR2 for the second group. On most DU
226 * instances, this maps to the first CRTC of the group, and we can just
227 * use rcar_du_crtc_dsysr_clr_set() to access the correct DSYSR. On
228 * M3-N, however, DU2 doesn't exist, but DSYSR2 does. We thus need to
229 * access the register directly using group read/write.
230 */
231 if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) {
232 struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2];
233
234 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
235 start ? DSYSR_DEN : DSYSR_DRES);
236 } else {
237 rcar_du_group_write(rgrp, DSYSR,
238 start ? DSYSR_DEN : DSYSR_DRES);
239 }
240 }
241
rcar_du_group_start_stop(struct rcar_du_group * rgrp,bool start)242 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
243 {
244 /*
245 * Many of the configuration bits are only updated when the display
246 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
247 * of those bits could be pre-configured, but others (especially the
248 * bits related to plane assignment to display timing controllers) need
249 * to be modified at runtime.
250 *
251 * Restart the display controller if a start is requested. Sorry for the
252 * flicker. It should be possible to move most of the "DRES-update" bits
253 * setup to driver initialization time and minimize the number of cases
254 * when the display controller will have to be restarted.
255 */
256 if (start) {
257 if (rgrp->used_crtcs++ != 0)
258 __rcar_du_group_start_stop(rgrp, false);
259 __rcar_du_group_start_stop(rgrp, true);
260 } else {
261 if (--rgrp->used_crtcs == 0)
262 __rcar_du_group_start_stop(rgrp, false);
263 }
264 }
265
rcar_du_group_restart(struct rcar_du_group * rgrp)266 void rcar_du_group_restart(struct rcar_du_group *rgrp)
267 {
268 rgrp->need_restart = false;
269
270 __rcar_du_group_start_stop(rgrp, false);
271 __rcar_du_group_start_stop(rgrp, true);
272 }
273
rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device * rcdu)274 int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
275 {
276 struct rcar_du_group *rgrp;
277 struct rcar_du_crtc *crtc;
278 unsigned int index;
279 int ret;
280
281 if (rcdu->info->gen < 2)
282 return 0;
283
284 /*
285 * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
286 * configured in the DEFR8 register of the first group on Gen2 and the
287 * last group on Gen3. As this function can be called with the DU
288 * channels of the corresponding CRTCs disabled, we need to enable the
289 * group clock before accessing the register.
290 */
291 index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;
292 rgrp = &rcdu->groups[index];
293 crtc = &rcdu->crtcs[index * 2];
294
295 ret = clk_prepare_enable(crtc->clock);
296 if (ret < 0)
297 return ret;
298
299 rcar_du_group_setup_defr8(rgrp);
300
301 clk_disable_unprepare(crtc->clock);
302
303 return 0;
304 }
305
rcar_du_group_set_dpad_levels(struct rcar_du_group * rgrp)306 static void rcar_du_group_set_dpad_levels(struct rcar_du_group *rgrp)
307 {
308 static const u32 doflr_values[2] = {
309 DOFLR_HSYCFL0 | DOFLR_VSYCFL0 | DOFLR_ODDFL0 |
310 DOFLR_DISPFL0 | DOFLR_CDEFL0 | DOFLR_RGBFL0,
311 DOFLR_HSYCFL1 | DOFLR_VSYCFL1 | DOFLR_ODDFL1 |
312 DOFLR_DISPFL1 | DOFLR_CDEFL1 | DOFLR_RGBFL1,
313 };
314 static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1)
315 | BIT(RCAR_DU_OUTPUT_DPAD0);
316 struct rcar_du_device *rcdu = rgrp->dev;
317 u32 doflr = DOFLR_CODE;
318 unsigned int i;
319
320 if (rcdu->info->gen < 2)
321 return;
322
323 /*
324 * The DPAD outputs can't be controlled directly. However, the parallel
325 * output of the DU channels routed to DPAD can be set to fixed levels
326 * through the DOFLR group register. Use this to turn the DPAD on or off
327 * by driving fixed low-level signals at the output of any DU channel
328 * not routed to a DPAD output. This doesn't affect the DU output
329 * signals going to other outputs, such as the internal LVDS and HDMI
330 * encoders.
331 */
332
333 for (i = 0; i < rgrp->num_crtcs; ++i) {
334 struct rcar_du_crtc_state *rstate;
335 struct rcar_du_crtc *rcrtc;
336
337 rcrtc = &rcdu->crtcs[rgrp->index * 2 + i];
338 rstate = to_rcar_crtc_state(rcrtc->crtc.state);
339
340 if (!(rstate->outputs & dpad_mask))
341 doflr |= doflr_values[i];
342 }
343
344 rcar_du_group_write(rgrp, DOFLR, doflr);
345 }
346
rcar_du_group_set_routing(struct rcar_du_group * rgrp)347 int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
348 {
349 struct rcar_du_device *rcdu = rgrp->dev;
350 u32 dorcr = rcar_du_group_read(rgrp, DORCR);
351
352 dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
353
354 /*
355 * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
356 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
357 * by default.
358 */
359 if (rcdu->dpad1_source == rgrp->index * 2)
360 dorcr |= DORCR_PG2D_DS1;
361 else
362 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
363
364 rcar_du_group_write(rgrp, DORCR, dorcr);
365
366 rcar_du_group_set_dpad_levels(rgrp);
367
368 return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
369 }
370