1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3 * Copyright (c) 2016, Linaro Limited
4 * Copyright (c) 2014, STMicroelectronics International N.V.
5 */
6
7 #ifndef ARM32_H
8 #define ARM32_H
9
10 #include <compiler.h>
11 #include <sys/cdefs.h>
12 #include <stdint.h>
13 #include <util.h>
14
15 #define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK
16 #define CPSR_MODE_USR ARM32_CPSR_MODE_USR
17 #define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ
18 #define CPSR_MODE_IRQ ARM32_CPSR_MODE_IRQ
19 #define CPSR_MODE_SVC ARM32_CPSR_MODE_SVC
20 #define CPSR_MODE_MON ARM32_CPSR_MODE_MON
21 #define CPSR_MODE_ABT ARM32_CPSR_MODE_ABT
22 #define CPSR_MODE_UND ARM32_CPSR_MODE_UND
23 #define CPSR_MODE_SYS ARM32_CPSR_MODE_SYS
24
25 #define CPSR_T ARM32_CPSR_T
26 #define CPSR_F_SHIFT ARM32_CPSR_F_SHIFT
27 #define CPSR_F ARM32_CPSR_F
28 #define CPSR_I ARM32_CPSR_I
29 #define CPSR_A ARM32_CPSR_A
30 #define CPSR_FIA ARM32_CPSR_FIA
31 #define CPSR_IT_MASK ARM32_CPSR_IT_MASK
32 #define CPSR_IT_MASK1 ARM32_CPSR_IT_MASK1
33 #define CPSR_IT_MASK2 ARM32_CPSR_IT_MASK2
34
35 #define PMCR_DP BIT32(5)
36
37 #define SCR_NS BIT32(0)
38 #define SCR_IRQ BIT32(1)
39 #define SCR_FIQ BIT32(2)
40 #define SCR_EA BIT32(3)
41 #define SCR_FW BIT32(4)
42 #define SCR_AW BIT32(5)
43 #define SCR_NET BIT32(6)
44 #define SCR_SCD BIT32(7)
45 #define SCR_HCE BIT32(8)
46 #define SCR_SIF BIT32(9)
47
48 #define SCTLR_M BIT32(0)
49 #define SCTLR_A BIT32(1)
50 #define SCTLR_C BIT32(2)
51 #define SCTLR_CP15BEN BIT32(5)
52 #define SCTLR_SW BIT32(10)
53 #define SCTLR_Z BIT32(11)
54 #define SCTLR_I BIT32(12)
55 #define SCTLR_V BIT32(13)
56 #define SCTLR_RR BIT32(14)
57 #define SCTLR_HA BIT32(17)
58 #define SCTLR_WXN BIT32(19)
59 #define SCTLR_UWXN BIT32(20)
60 #define SCTLR_FI BIT32(21)
61 #define SCTLR_SPAN BIT32(23)
62 #define SCTLR_VE BIT32(24)
63 #define SCTLR_EE BIT32(25)
64 #define SCTLR_NMFI BIT32(27)
65 #define SCTLR_TRE BIT32(28)
66 #define SCTLR_AFE BIT32(29)
67 #define SCTLR_TE BIT32(30)
68
69 /* Only valid for Cortex-A15 */
70 #define ACTLR_CA15_ENABLE_INVALIDATE_BTB BIT(0)
71 /* Only valid for Cortex-A8 */
72 #define ACTLR_CA8_ENABLE_INVALIDATE_BTB BIT(6)
73 /* Only valid for Cortex-A9 */
74 #define ACTLR_CA9_WFLZ BIT(3)
75
76 #define ACTLR_SMP BIT32(6)
77
78 #define NSACR_CP10 BIT32(10)
79 #define NSACR_CP11 BIT32(11)
80 #define NSACR_NSD32DIS BIT32(14)
81 #define NSACR_NSASEDIS BIT32(15)
82 #define NSACR_NS_L2ERR BIT32(17)
83 #define NSACR_NS_SMP BIT32(18)
84
85 #define CPACR_ASEDIS BIT32(31)
86 #define CPACR_D32DIS BIT32(30)
87 #define CPACR_CP(co_proc, access) SHIFT_U32((access), ((co_proc) * 2))
88 #define CPACR_CP_ACCESS_DENIED U(0x0)
89 #define CPACR_CP_ACCESS_PL1_ONLY U(0x1)
90 #define CPACR_CP_ACCESS_FULL U(0x3)
91
92
93 #define DACR_DOMAIN(num, perm) SHIFT_U32((perm), ((num) * 2))
94 #define DACR_DOMAIN_PERM_NO_ACCESS U(0x0)
95 #define DACR_DOMAIN_PERM_CLIENT U(0x1)
96 #define DACR_DOMAIN_PERM_MANAGER U(0x3)
97
98 #define PAR_F BIT32(0)
99 #define PAR_SS BIT32(1)
100 #define PAR_LPAE BIT32(11)
101 #define PAR_PA_SHIFT U(12)
102 #define PAR32_PA_MASK (BIT32(20) - 1)
103 #define PAR64_PA_MASK (BIT64(28) - 1)
104
105 /*
106 * TTBCR has different register layout if LPAE is enabled or not.
107 * TTBCR.EAE == 0 => LPAE is not enabled
108 * TTBCR.EAE == 1 => LPAE is enabled
109 */
110 #define TTBCR_EAE BIT32(31)
111
112 /* When TTBCR.EAE == 0 */
113 #define TTBCR_PD0 BIT32(4)
114 #define TTBCR_PD1 BIT32(5)
115
116 /* When TTBCR.EAE == 1 */
117 #define TTBCR_T0SZ_SHIFT U(0)
118 #define TTBCR_EPD0 BIT32(7)
119 #define TTBCR_IRGN0_SHIFT U(8)
120 #define TTBCR_ORGN0_SHIFT U(10)
121 #define TTBCR_SH0_SHIFT U(12)
122 #define TTBCR_T1SZ_SHIFT U(16)
123 #define TTBCR_A1 BIT32(22)
124 #define TTBCR_EPD1 BIT32(23)
125 #define TTBCR_IRGN1_SHIFT U(24)
126 #define TTBCR_ORGN1_SHIFT U(26)
127 #define TTBCR_SH1_SHIFT U(28)
128
129 /* Normal memory, Inner/Outer Non-cacheable */
130 #define TTBCR_XRGNX_NC U(0x0)
131 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */
132 #define TTBCR_XRGNX_WB U(0x1)
133 /* Normal memory, Inner/Outer Write-Through Cacheable */
134 #define TTBCR_XRGNX_WT U(0x2)
135 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */
136 #define TTBCR_XRGNX_WBWA U(0x3)
137
138 /* Non-shareable */
139 #define TTBCR_SHX_NSH U(0x0)
140 /* Outer Shareable */
141 #define TTBCR_SHX_OSH U(0x2)
142 /* Inner Shareable */
143 #define TTBCR_SHX_ISH U(0x3)
144
145 #define TTBR_ASID_MASK U(0xff)
146 #define TTBR_ASID_SHIFT U(48)
147
148 #define TLBI_MVA_SHIFT U(12)
149 #define TLBI_ASID_MASK U(0xff)
150
151 #define FSR_LPAE BIT32(9)
152 #define FSR_WNR BIT32(11)
153
154 /* Valid if FSR.LPAE is 1 */
155 #define FSR_STATUS_MASK (BIT32(6) - 1)
156
157 /* Valid if FSR.LPAE is 0 */
158 #define FSR_FS_MASK (BIT32(10) | (BIT32(4) - 1))
159
160 /* ID_PFR1 bit fields */
161 #define IDPFR1_VIRT_SHIFT U(12)
162 #define IDPFR1_VIRT_MASK SHIFT_U32(0xF, IDPFR1_VIRT_SHIFT)
163 #define IDPFR1_GENTIMER_SHIFT U(16)
164 #define IDPFR1_GENTIMER_MASK SHIFT_U32(0xF, IDPFR1_GENTIMER_SHIFT)
165
166 #ifndef __ASSEMBLER__
167 #include <generated/arm32_sysreg.h>
168 #ifdef CFG_ARM_GICV3
169 #include <generated/arm32_gicv3_sysreg.h>
170 #endif
171
isb(void)172 static inline __noprof void isb(void)
173 {
174 asm volatile ("isb" : : : "memory");
175 }
176
dsb(void)177 static inline __noprof void dsb(void)
178 {
179 asm volatile ("dsb" : : : "memory");
180 }
181
dsb_ish(void)182 static inline __noprof void dsb_ish(void)
183 {
184 asm volatile ("dsb ish" : : : "memory");
185 }
186
dsb_ishst(void)187 static inline __noprof void dsb_ishst(void)
188 {
189 asm volatile ("dsb ishst" : : : "memory");
190 }
191
dmb(void)192 static inline __noprof void dmb(void)
193 {
194 asm volatile ("dmb" : : : "memory");
195 }
196
sev(void)197 static inline __noprof void sev(void)
198 {
199 asm volatile ("sev" : : : "memory");
200 }
201
wfe(void)202 static inline __noprof void wfe(void)
203 {
204 asm volatile ("wfe" : : : "memory");
205 }
206
read_cpsr(void)207 static inline __noprof uint32_t read_cpsr(void)
208 {
209 uint32_t cpsr;
210
211 asm volatile ("mrs %[cpsr], cpsr"
212 : [cpsr] "=r" (cpsr)
213 );
214 return cpsr;
215 }
216
write_cpsr(uint32_t cpsr)217 static inline __noprof void write_cpsr(uint32_t cpsr)
218 {
219 asm volatile ("msr cpsr_fsxc, %[cpsr]"
220 : : [cpsr] "r" (cpsr)
221 );
222 }
223
read_spsr(void)224 static inline __noprof uint32_t read_spsr(void)
225 {
226 uint32_t spsr;
227
228 asm volatile ("mrs %[spsr], spsr"
229 : [spsr] "=r" (spsr)
230 );
231 return spsr;
232 }
233
wfi(void)234 static inline __noprof void wfi(void)
235 {
236 asm volatile("wfi" : : : "memory");
237 }
238
read_pc(void)239 static __always_inline __noprof uint32_t read_pc(void)
240 {
241 uint32_t val;
242
243 asm volatile ("adr %0, ." : "=r" (val));
244 return val;
245 }
246
read_sp(void)247 static __always_inline __noprof uint32_t read_sp(void)
248 {
249 uint32_t val;
250
251 asm volatile ("mov %0, sp" : "=r" (val));
252 return val;
253 }
254
read_lr(void)255 static __always_inline __noprof uint32_t read_lr(void)
256 {
257 uint32_t val;
258
259 asm volatile ("mov %0, lr" : "=r" (val));
260 return val;
261 }
262
read_fp(void)263 static __always_inline __noprof uint32_t read_fp(void)
264 {
265 uint32_t val;
266
267 asm volatile ("mov %0, fp" : "=r" (val));
268 return val;
269 }
270
read_r7(void)271 static __always_inline __noprof uint32_t read_r7(void)
272 {
273 uint32_t val;
274
275 asm volatile ("mov %0, r7" : "=r" (val));
276 return val;
277 }
278
279 #endif /*__ASSEMBLER__*/
280
281 #endif /*ARM32_H*/
282