1 /*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef MT_SPM_INTERNAL
8 #define MT_SPM_INTERNAL
9
10 #include "mt_spm.h"
11
12 /* Config and Parameter */
13 #define POWER_ON_VAL0_DEF (0x0000F100)
14 #define POWER_ON_VAL1_DEF (0x80015860)
15 #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
16 #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
17
18 /* Define and Declare */
19 /* PCM_PWR_IO_EN */
20 #define PCM_PWRIO_EN_R0 BIT(0)
21 #define PCM_PWRIO_EN_R7 BIT(7)
22 #define PCM_RF_SYNC_R0 BIT(16)
23 #define PCM_RF_SYNC_R6 BIT(22)
24 #define PCM_RF_SYNC_R7 BIT(23)
25
26 /* SPM_SWINT */
27 #define PCM_SW_INT0 BIT(0)
28 #define PCM_SW_INT1 BIT(1)
29 #define PCM_SW_INT2 BIT(2)
30 #define PCM_SW_INT3 BIT(3)
31 #define PCM_SW_INT4 BIT(4)
32 #define PCM_SW_INT5 BIT(5)
33 #define PCM_SW_INT6 BIT(6)
34 #define PCM_SW_INT7 BIT(7)
35 #define PCM_SW_INT8 BIT(8)
36 #define PCM_SW_INT9 BIT(9)
37 #define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
38 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
39 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
40 PCM_SW_INT0)
41
42 /* SPM_AP_STANDBY_CON */
43 #define WFI_OP_AND (1U)
44 #define WFI_OP_OR (0U)
45
46 /* SPM_IRQ_MASK */
47 #define ISRM_TWAM (1U << 2)
48 #define ISRM_PCM_RETURN (1U << 3)
49 #define ISRM_RET_IRQ0 (1U << 8)
50 #define ISRM_RET_IRQ1 (1U << 9)
51 #define ISRM_RET_IRQ2 (1U << 10)
52 #define ISRM_RET_IRQ3 (1U << 11)
53 #define ISRM_RET_IRQ4 (1U << 12)
54 #define ISRM_RET_IRQ5 (1U << 13)
55 #define ISRM_RET_IRQ6 (1U << 14)
56 #define ISRM_RET_IRQ7 (1U << 15)
57 #define ISRM_RET_IRQ8 (1U << 16)
58 #define ISRM_RET_IRQ9 (1U << 17)
59 #define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
60 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
61 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
62 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
63 (ISRM_RET_IRQ1))
64 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
65 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
66
67 /* SPM_IRQ_STA */
68 #define ISRS_TWAM BIT(2)
69 #define ISRS_PCM_RETURN BIT(3)
70 #define ISRC_TWAM ISRS_TWAM
71 #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
72 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
73
74 /* SPM_WAKEUP_MISC */
75 #define WAKE_MISC_GIC_WAKEUP (0x3FF)
76 #define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
77 #define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
78 #define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
79 #define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20))
80 #define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
81 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
82 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
83 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
84 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
85 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
86 #define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
87 #define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
88
89 /* ABORT MASK for DEBUG FOORTPRINT */
90 #define DEBUG_ABORT_MASK \
91 (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
92 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
93
94 #define DEBUG_ABORT_MASK_1 \
95 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
96 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
97 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
98 SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
99 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
100 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
101 SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
102
103 #define MCUPM_MBOX_WAKEUP_CPU (0x0C55FD10)
104
105 struct pwr_ctrl {
106 uint32_t pcm_flags;
107 uint32_t pcm_flags_cust;
108 uint32_t pcm_flags_cust_set;
109 uint32_t pcm_flags_cust_clr;
110 uint32_t pcm_flags1;
111 uint32_t pcm_flags1_cust;
112 uint32_t pcm_flags1_cust_set;
113 uint32_t pcm_flags1_cust_clr;
114 uint32_t timer_val;
115 uint32_t timer_val_cust;
116 uint32_t timer_val_ramp_en;
117 uint32_t timer_val_ramp_en_sec;
118 uint32_t wake_src;
119 uint32_t wake_src_cust;
120 uint32_t wakelock_timer_val;
121 uint8_t wdt_disable;
122
123 /* Auto-gen Start */
124
125 /* SPM_AP_STANDBY_CON */
126 uint8_t reg_wfi_op;
127 uint8_t reg_wfi_type;
128 uint8_t reg_mp0_cputop_idle_mask;
129 uint8_t reg_mp1_cputop_idle_mask;
130 uint8_t reg_mcusys_idle_mask;
131 uint8_t reg_md_apsrc_1_sel;
132 uint8_t reg_md_apsrc_0_sel;
133 uint8_t reg_conn_apsrc_sel;
134
135 /* SPM_SRC6_MASK */
136 uint32_t reg_ccif_event_infra_req_mask_b;
137 uint32_t reg_ccif_event_apsrc_req_mask_b;
138
139 /* SPM_SRC_REQ */
140 uint8_t reg_spm_apsrc_req;
141 uint8_t reg_spm_f26m_req;
142 uint8_t reg_spm_infra_req;
143 uint8_t reg_spm_vrf18_req;
144 uint8_t reg_spm_ddren_req;
145 uint8_t reg_spm_dvfs_req;
146 uint8_t reg_spm_sw_mailbox_req;
147 uint8_t reg_spm_sspm_mailbox_req;
148 uint8_t reg_spm_adsp_mailbox_req;
149 uint8_t reg_spm_scp_mailbox_req;
150
151 /* SPM_SRC_MASK */
152 uint8_t reg_md_0_srcclkena_mask_b;
153 uint8_t reg_md_0_infra_req_mask_b;
154 uint8_t reg_md_0_apsrc_req_mask_b;
155 uint8_t reg_md_0_vrf18_req_mask_b;
156 uint8_t reg_md_0_ddren_req_mask_b;
157 uint8_t reg_md_1_srcclkena_mask_b;
158 uint8_t reg_md_1_infra_req_mask_b;
159 uint8_t reg_md_1_apsrc_req_mask_b;
160 uint8_t reg_md_1_vrf18_req_mask_b;
161 uint8_t reg_md_1_ddren_req_mask_b;
162 uint8_t reg_conn_srcclkena_mask_b;
163 uint8_t reg_conn_srcclkenb_mask_b;
164 uint8_t reg_conn_infra_req_mask_b;
165 uint8_t reg_conn_apsrc_req_mask_b;
166 uint8_t reg_conn_vrf18_req_mask_b;
167 uint8_t reg_conn_ddren_req_mask_b;
168 uint8_t reg_conn_vfe28_mask_b;
169 uint8_t reg_srcclkeni_srcclkena_mask_b;
170 uint8_t reg_srcclkeni_infra_req_mask_b;
171 uint8_t reg_infrasys_apsrc_req_mask_b;
172 uint8_t reg_infrasys_ddren_req_mask_b;
173 uint8_t reg_sspm_srcclkena_mask_b;
174 uint8_t reg_sspm_infra_req_mask_b;
175 uint8_t reg_sspm_apsrc_req_mask_b;
176 uint8_t reg_sspm_vrf18_req_mask_b;
177 uint8_t reg_sspm_ddren_req_mask_b;
178
179 /* SPM_SRC2_MASK */
180 uint8_t reg_scp_srcclkena_mask_b;
181 uint8_t reg_scp_infra_req_mask_b;
182 uint8_t reg_scp_apsrc_req_mask_b;
183 uint8_t reg_scp_vrf18_req_mask_b;
184 uint8_t reg_scp_ddren_req_mask_b;
185 uint8_t reg_audio_dsp_srcclkena_mask_b;
186 uint8_t reg_audio_dsp_infra_req_mask_b;
187 uint8_t reg_audio_dsp_apsrc_req_mask_b;
188 uint8_t reg_audio_dsp_vrf18_req_mask_b;
189 uint8_t reg_audio_dsp_ddren_req_mask_b;
190 uint8_t reg_ufs_srcclkena_mask_b;
191 uint8_t reg_ufs_infra_req_mask_b;
192 uint8_t reg_ufs_apsrc_req_mask_b;
193 uint8_t reg_ufs_vrf18_req_mask_b;
194 uint8_t reg_ufs_ddren_req_mask_b;
195 uint8_t reg_disp0_apsrc_req_mask_b;
196 uint8_t reg_disp0_ddren_req_mask_b;
197 uint8_t reg_disp1_apsrc_req_mask_b;
198 uint8_t reg_disp1_ddren_req_mask_b;
199 uint8_t reg_gce_infra_req_mask_b;
200 uint8_t reg_gce_apsrc_req_mask_b;
201 uint8_t reg_gce_vrf18_req_mask_b;
202 uint8_t reg_gce_ddren_req_mask_b;
203 uint8_t reg_apu_srcclkena_mask_b;
204 uint8_t reg_apu_infra_req_mask_b;
205 uint8_t reg_apu_apsrc_req_mask_b;
206 uint8_t reg_apu_vrf18_req_mask_b;
207 uint8_t reg_apu_ddren_req_mask_b;
208 uint8_t reg_cg_check_srcclkena_mask_b;
209 uint8_t reg_cg_check_apsrc_req_mask_b;
210 uint8_t reg_cg_check_vrf18_req_mask_b;
211 uint8_t reg_cg_check_ddren_req_mask_b;
212
213 /* SPM_SRC3_MASK */
214 uint8_t reg_dvfsrc_event_trigger_mask_b;
215 uint8_t reg_sw2spm_wakeup_mask_b;
216 uint8_t reg_adsp2spm_wakeup_mask_b;
217 uint8_t reg_sspm2spm_wakeup_mask_b;
218 uint8_t reg_scp2spm_wakeup_mask_b;
219 uint8_t reg_csyspwrup_ack_mask;
220 uint8_t reg_spm_reserved_srcclkena_mask_b;
221 uint8_t reg_spm_reserved_infra_req_mask_b;
222 uint8_t reg_spm_reserved_apsrc_req_mask_b;
223 uint8_t reg_spm_reserved_vrf18_req_mask_b;
224 uint8_t reg_spm_reserved_ddren_req_mask_b;
225 uint8_t reg_mcupm_srcclkena_mask_b;
226 uint8_t reg_mcupm_infra_req_mask_b;
227 uint8_t reg_mcupm_apsrc_req_mask_b;
228 uint8_t reg_mcupm_vrf18_req_mask_b;
229 uint8_t reg_mcupm_ddren_req_mask_b;
230 uint8_t reg_msdc0_srcclkena_mask_b;
231 uint8_t reg_msdc0_infra_req_mask_b;
232 uint8_t reg_msdc0_apsrc_req_mask_b;
233 uint8_t reg_msdc0_vrf18_req_mask_b;
234 uint8_t reg_msdc0_ddren_req_mask_b;
235 uint8_t reg_msdc1_srcclkena_mask_b;
236 uint8_t reg_msdc1_infra_req_mask_b;
237 uint8_t reg_msdc1_apsrc_req_mask_b;
238 uint8_t reg_msdc1_vrf18_req_mask_b;
239 uint8_t reg_msdc1_ddren_req_mask_b;
240
241 /* SPM_SRC4_MASK */
242 uint32_t reg_ccif_event_srcclkena_mask_b;
243 uint8_t reg_bak_psri_srcclkena_mask_b;
244 uint8_t reg_bak_psri_infra_req_mask_b;
245 uint8_t reg_bak_psri_apsrc_req_mask_b;
246 uint8_t reg_bak_psri_vrf18_req_mask_b;
247 uint8_t reg_bak_psri_ddren_req_mask_b;
248 uint8_t reg_dramc_md32_infra_req_mask_b;
249 uint8_t reg_dramc_md32_vrf18_req_mask_b;
250 uint8_t reg_conn_srcclkenb2pwrap_mask_b;
251 uint8_t reg_dramc_md32_apsrc_req_mask_b;
252
253 /* SPM_SRC5_MASK */
254 uint32_t reg_mcusys_merge_apsrc_req_mask_b;
255 uint32_t reg_mcusys_merge_ddren_req_mask_b;
256 uint8_t reg_afe_srcclkena_mask_b;
257 uint8_t reg_afe_infra_req_mask_b;
258 uint8_t reg_afe_apsrc_req_mask_b;
259 uint8_t reg_afe_vrf18_req_mask_b;
260 uint8_t reg_afe_ddren_req_mask_b;
261 uint8_t reg_msdc2_srcclkena_mask_b;
262 uint8_t reg_msdc2_infra_req_mask_b;
263 uint8_t reg_msdc2_apsrc_req_mask_b;
264 uint8_t reg_msdc2_vrf18_req_mask_b;
265 uint8_t reg_msdc2_ddren_req_mask_b;
266
267 /* SPM_WAKEUP_EVENT_MASK */
268 uint32_t reg_wakeup_event_mask;
269
270 /* SPM_WAKEUP_EVENT_EXT_MASK */
271 uint32_t reg_ext_wakeup_event_mask;
272
273 /* SPM_SRC7_MASK */
274 uint8_t reg_pcie_srcclkena_mask_b;
275 uint8_t reg_pcie_infra_req_mask_b;
276 uint8_t reg_pcie_apsrc_req_mask_b;
277 uint8_t reg_pcie_vrf18_req_mask_b;
278 uint8_t reg_pcie_ddren_req_mask_b;
279 uint8_t reg_dpmaif_srcclkena_mask_b;
280 uint8_t reg_dpmaif_infra_req_mask_b;
281 uint8_t reg_dpmaif_apsrc_req_mask_b;
282 uint8_t reg_dpmaif_vrf18_req_mask_b;
283 uint8_t reg_dpmaif_ddren_req_mask_b;
284
285 /* Auto-gen End */
286 };
287
288 /* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
289 enum pwr_ctrl_enum {
290 PW_PCM_FLAGS,
291 PW_PCM_FLAGS_CUST,
292 PW_PCM_FLAGS_CUST_SET,
293 PW_PCM_FLAGS_CUST_CLR,
294 PW_PCM_FLAGS1,
295 PW_PCM_FLAGS1_CUST,
296 PW_PCM_FLAGS1_CUST_SET,
297 PW_PCM_FLAGS1_CUST_CLR,
298 PW_TIMER_VAL,
299 PW_TIMER_VAL_CUST,
300 PW_TIMER_VAL_RAMP_EN,
301 PW_TIMER_VAL_RAMP_EN_SEC,
302 PW_WAKE_SRC,
303 PW_WAKE_SRC_CUST,
304 PW_WAKELOCK_TIMER_VAL,
305 PW_WDT_DISABLE,
306
307 /* SPM_AP_STANDBY_CON */
308 PW_REG_WFI_OP,
309 PW_REG_WFI_TYPE,
310 PW_REG_MP0_CPUTOP_IDLE_MASK,
311 PW_REG_MP1_CPUTOP_IDLE_MASK,
312 PW_REG_MCUSYS_IDLE_MASK,
313 PW_REG_MD_APSRC_1_SEL,
314 PW_REG_MD_APSRC_0_SEL,
315 PW_REG_CONN_APSRC_SEL,
316
317 /* SPM_SRC6_MASK */
318 PW_REG_CCIF_EVENT_INFRA_REQ_MASK_B,
319 PW_REG_CCIF_EVENT_APSRC_REQ_MASK_B,
320
321 /* SPM_WAKEUP_EVENT_SENS */
322 PW_REG_WAKEUP_EVENT_SENS,
323
324 /* SPM_SRC_REQ */
325 PW_REG_SPM_APSRC_REQ,
326 PW_REG_SPM_F26M_REQ,
327 PW_REG_SPM_INFRA_REQ,
328 PW_REG_SPM_VRF18_REQ,
329 PW_REG_SPM_DDREN_REQ,
330 PW_REG_SPM_DVFS_REQ,
331 PW_REG_SPM_SW_MAILBOX_REQ,
332 PW_REG_SPM_SSPM_MAILBOX_REQ,
333 PW_REG_SPM_ADSP_MAILBOX_REQ,
334 PW_REG_SPM_SCP_MAILBOX_REQ,
335
336 /* SPM_SRC_MASK */
337 PW_REG_MD_0_SRCCLKENA_MASK_B,
338 PW_REG_MD_0_INFRA_REQ_MASK_B,
339 PW_REG_MD_0_APSRC_REQ_MASK_B,
340 PW_REG_MD_0_VRF18_REQ_MASK_B,
341 PW_REG_MD_0_DDREN_REQ_MASK_B,
342 PW_REG_MD_1_SRCCLKENA_MASK_B,
343 PW_REG_MD_1_INFRA_REQ_MASK_B,
344 PW_REG_MD_1_APSRC_REQ_MASK_B,
345 PW_REG_MD_1_VRF18_REQ_MASK_B,
346 PW_REG_MD_1_DDREN_REQ_MASK_B,
347 PW_REG_CONN_SRCCLKENA_MASK_B,
348 PW_REG_CONN_SRCCLKENB_MASK_B,
349 PW_REG_CONN_INFRA_REQ_MASK_B,
350 PW_REG_CONN_APSRC_REQ_MASK_B,
351 PW_REG_CONN_VRF18_REQ_MASK_B,
352 PW_REG_CONN_DDREN_REQ_MASK_B,
353 PW_REG_CONN_VFE28_MASK_B,
354 PW_REG_SRCCLKENI_SRCCLKENA_MASK_B,
355 PW_REG_SRCCLKENI_INFRA_REQ_MASK_B,
356 PW_REG_INFRASYS_APSRC_REQ_MASK_B,
357 PW_REG_INFRASYS_DDREN_REQ_MASK_B,
358 PW_REG_SSPM_SRCCLKENA_MASK_B,
359 PW_REG_SSPM_INFRA_REQ_MASK_B,
360 PW_REG_SSPM_APSRC_REQ_MASK_B,
361 PW_REG_SSPM_VRF18_REQ_MASK_B,
362 PW_REG_SSPM_DDREN_REQ_MASK_B,
363
364 /* SPM_SRC2_MASK */
365 PW_REG_SCP_SRCCLKENA_MASK_B,
366 PW_REG_SCP_INFRA_REQ_MASK_B,
367 PW_REG_SCP_APSRC_REQ_MASK_B,
368 PW_REG_SCP_VRF18_REQ_MASK_B,
369 PW_REG_SCP_DDREN_REQ_MASK_B,
370 PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
371 PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
372 PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
373 PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
374 PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B,
375 PW_REG_UFS_SRCCLKENA_MASK_B,
376 PW_REG_UFS_INFRA_REQ_MASK_B,
377 PW_REG_UFS_APSRC_REQ_MASK_B,
378 PW_REG_UFS_VRF18_REQ_MASK_B,
379 PW_REG_UFS_DDREN_REQ_MASK_B,
380 PW_REG_DISP0_APSRC_REQ_MASK_B,
381 PW_REG_DISP0_DDREN_REQ_MASK_B,
382 PW_REG_DISP1_APSRC_REQ_MASK_B,
383 PW_REG_DISP1_DDREN_REQ_MASK_B,
384 PW_REG_GCE_INFRA_REQ_MASK_B,
385 PW_REG_GCE_APSRC_REQ_MASK_B,
386 PW_REG_GCE_VRF18_REQ_MASK_B,
387 PW_REG_GCE_DDREN_REQ_MASK_B,
388 PW_REG_APU_SRCCLKENA_MASK_B,
389 PW_REG_APU_INFRA_REQ_MASK_B,
390 PW_REG_APU_APSRC_REQ_MASK_B,
391 PW_REG_APU_VRF18_REQ_MASK_B,
392 PW_REG_APU_DDREN_REQ_MASK_B,
393 PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
394 PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
395 PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
396 PW_REG_CG_CHECK_DDREN_REQ_MASK_B,
397
398 /* SPM_SRC3_MASK */
399 PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
400 PW_REG_SW2SPM_WAKEUP_MASK_B,
401 PW_REG_ADSP2SPM_WAKEUP_MASK_B,
402 PW_REG_SSPM2SPM_WAKEUP_MASK_B,
403 PW_REG_SCP2SPM_WAKEUP_MASK_B,
404 PW_REG_CSYSPWRUP_ACK_MASK,
405 PW_REG_SPM_RESERVED_SRCCLKENA_MASK_B,
406 PW_REG_SPM_RESERVED_INFRA_REQ_MASK_B,
407 PW_REG_SPM_RESERVED_APSRC_REQ_MASK_B,
408 PW_REG_SPM_RESERVED_VRF18_REQ_MASK_B,
409 PW_REG_SPM_RESERVED_DDREN_REQ_MASK_B,
410 PW_REG_MCUPM_SRCCLKENA_MASK_B,
411 PW_REG_MCUPM_INFRA_REQ_MASK_B,
412 PW_REG_MCUPM_APSRC_REQ_MASK_B,
413 PW_REG_MCUPM_VRF18_REQ_MASK_B,
414 PW_REG_MCUPM_DDREN_REQ_MASK_B,
415 PW_REG_MSDC0_SRCCLKENA_MASK_B,
416 PW_REG_MSDC0_INFRA_REQ_MASK_B,
417 PW_REG_MSDC0_APSRC_REQ_MASK_B,
418 PW_REG_MSDC0_VRF18_REQ_MASK_B,
419 PW_REG_MSDC0_DDREN_REQ_MASK_B,
420 PW_REG_MSDC1_SRCCLKENA_MASK_B,
421 PW_REG_MSDC1_INFRA_REQ_MASK_B,
422 PW_REG_MSDC1_APSRC_REQ_MASK_B,
423 PW_REG_MSDC1_VRF18_REQ_MASK_B,
424 PW_REG_MSDC1_DDREN_REQ_MASK_B,
425
426 /* SPM_SRC4_MASK */
427 PW_REG_CCIF_EVENT_SRCCLKENA_MASK_B,
428 PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
429 PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
430 PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
431 PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
432 PW_REG_BAK_PSRI_DDREN_REQ_MASK_B,
433 PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
434 PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
435 PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
436 PW_REG_DRAMC_MD32_APSRC_REQ_MASK_B,
437
438 /* SPM_SRC5_MASK */
439 PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
440 PW_REG_MCUSYS_MERGE_DDREN_REQ_MASK_B,
441 PW_REG_AFE_SRCCLKENA_MASK_B,
442 PW_REG_AFE_INFRA_REQ_MASK_B,
443 PW_REG_AFE_APSRC_REQ_MASK_B,
444 PW_REG_AFE_VRF18_REQ_MASK_B,
445 PW_REG_AFE_DDREN_REQ_MASK_B,
446 PW_REG_MSDC2_SRCCLKENA_MASK_B,
447 PW_REG_MSDC2_INFRA_REQ_MASK_B,
448 PW_REG_MSDC2_APSRC_REQ_MASK_B,
449 PW_REG_MSDC2_VRF18_REQ_MASK_B,
450 PW_REG_MSDC2_DDREN_REQ_MASK_B,
451
452 /* SPM_WAKEUP_EVENT_MASK */
453 PW_REG_WAKEUP_EVENT_MASK,
454
455 /* SPM_WAKEUP_EVENT_EXT_MASK */
456 PW_REG_EXT_WAKEUP_EVENT_MASK,
457
458 /* SPM_SRC7_MASK */
459 PW_REG_PCIE_SRCCLKENA_MASK_B,
460 PW_REG_PCIE_INFRA_REQ_MASK_B,
461 PW_REG_PCIE_APSRC_REQ_MASK_B,
462 PW_REG_PCIE_VRF18_REQ_MASK_B,
463 PW_REG_PCIE_DDREN_REQ_MASK_B,
464 PW_REG_DPMAIF_SRCCLKENA_MASK_B,
465 PW_REG_DPMAIF_INFRA_REQ_MASK_B,
466 PW_REG_DPMAIF_APSRC_REQ_MASK_B,
467 PW_REG_DPMAIF_VRF18_REQ_MASK_B,
468 PW_REG_DPMAIF_DDREN_REQ_MASK_B,
469
470 PW_MAX_COUNT,
471 };
472
473 /*
474 * ACK HW MODE SETTING
475 * 0: trigger(1)
476 * 1: trigger(0)
477 * 2: trigger(1) and target(0)
478 * 3: trigger(0) and target(1)
479 * 4: trigger(1) and target(1)
480 * 5: trigger(0) and target(0)
481 */
482 #define TRIG_H_TAR_L (2U)
483 #define TRIG_L_TAR_H (3U)
484 #define TRIG_H_TAR_H (4U)
485 #define TRIG_L_TAR_L (5U)
486
487 #define SPM_INTERNAL_STATUS_HW_S1 (1U << 0)
488 #define SPM_ACK_CHK_3_SEL_HW_S1 (0x00350098)
489 #define SPM_ACK_CHK_3_HW_S1_CNT (1U)
490 #define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (TRIG_L_TAR_H << 9u)
491 #define SPM_ACK_CHK_3_CON_EN (0x110)
492 #define SPM_ACK_CHK_3_CON_CLR_ALL (0x2)
493 #define SPM_ACK_CHK_3_CON_RESULT (0x8000)
494
495 struct wake_status_trace_comm {
496 uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
497 uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
498 uint32_t timer_out; /* SPM_SW_RSV_6*/
499 uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
500 uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */
501 uint32_t r12; /* SPM_SW_RSV_0 */
502 uint32_t r13; /* PCM_REG13_DATA */
503 uint32_t req_sta0; /* SRC_REQ_STA_0 */
504 uint32_t req_sta1; /* SRC_REQ_STA_1 */
505 uint32_t req_sta2; /* SRC_REQ_STA_2 */
506 uint32_t req_sta3; /* SRC_REQ_STA_3 */
507 uint32_t req_sta4; /* SRC_REQ_STA_4 */
508 uint32_t raw_sta; /* SPM_WAKEUP_STA */
509 uint32_t times_h; /* timestamp high bits */
510 uint32_t times_l; /* timestamp low bits */
511 uint32_t resumetime; /* timestamp low bits */
512 };
513
514 struct wake_status_trace {
515 struct wake_status_trace_comm comm;
516 };
517
518 struct wake_status {
519 struct wake_status_trace tr;
520 uint32_t r12; /* SPM_BK_WAKE_EVENT */
521 uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */
522 uint32_t raw_sta; /* SPM_WAKEUP_STA */
523 uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
524 uint32_t md32pcm_wakeup_sta; /* MD32CPM_WAKEUP_STA */
525 uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
526 uint32_t wake_misc; /* SPM_BK_WAKE_MISC */
527 uint32_t timer_out; /* SPM_BK_PCM_TIMER */
528 uint32_t r13; /* PCM_REG13_DATA */
529 uint32_t idle_sta; /* SUBSYS_IDLE_STA */
530 uint32_t req_sta0; /* SRC_REQ_STA_0 */
531 uint32_t req_sta1; /* SRC_REQ_STA_1 */
532 uint32_t req_sta2; /* SRC_REQ_STA_2 */
533 uint32_t req_sta3; /* SRC_REQ_STA_3 */
534 uint32_t req_sta4; /* SRC_REQ_STA_4 */
535 uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
536 uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
537 uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
538 uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
539 uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
540 uint32_t isr; /* SPM_IRQ_STA */
541 uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
542 uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
543 uint32_t clk_settle; /* SPM_CLK_SETTLE */
544 uint32_t src_req; /* SPM_SRC_REQ */
545 uint32_t log_index;
546 uint32_t abort;
547 uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
548 uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
549 uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
550 uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
551 uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
552 uint32_t mcupm_req_sta;
553 };
554
555 struct spm_lp_scen {
556 struct pcm_desc *pcmdesc;
557 struct pwr_ctrl *pwrctrl;
558 };
559
560 extern struct spm_lp_scen __spm_vcorefs;
561
562 extern void __spm_set_cpu_status(unsigned int cpu);
563 extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
564 extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
565 extern void __spm_init_pcm_register(void);
566 extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
567 unsigned int resource_usage);
568 extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
569 extern void __spm_disable_pcm_timer(void);
570 extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
571 extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
572 extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
573 extern void __spm_send_cpu_wakeup_event(void);
574
575 extern void __spm_get_wakeup_status(struct wake_status *wakesta,
576 unsigned int ext_status);
577 extern void __spm_clean_after_wakeup(void);
578 extern wake_reason_t __spm_output_wake_reason(int state_id,
579 const struct wake_status *wakesta);
580 extern void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
581 const struct pwr_ctrl *src_pwr_ctrl);
582 extern void __spm_set_pcm_wdt(int en);
583 extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
584 extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
585 extern void __spm_ext_int_wakeup_req_clr(void);
586 extern void __spm_xo_soc_bblpm(int en);
587
set_pwrctrl_pcm_flags(struct pwr_ctrl * pwrctrl,uint32_t flags)588 static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
589 uint32_t flags)
590 {
591 if (pwrctrl->pcm_flags_cust == 0U) {
592 pwrctrl->pcm_flags = flags;
593 } else {
594 pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
595 }
596 }
597
set_pwrctrl_pcm_flags1(struct pwr_ctrl * pwrctrl,uint32_t flags)598 static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
599 uint32_t flags)
600 {
601 if (pwrctrl->pcm_flags1_cust == 0U) {
602 pwrctrl->pcm_flags1 = flags;
603 } else {
604 pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
605 }
606 }
607
608 extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
609
spm_hw_s1_state_monitor_resume(void)610 static inline void spm_hw_s1_state_monitor_resume(void)
611 {
612 __spm_hw_s1_state_monitor(1, NULL);
613 }
614
spm_hw_s1_state_monitor_pause(unsigned int * status)615 static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
616 {
617 __spm_hw_s1_state_monitor(0, status);
618 }
619
620 #endif /* MT_SPM_INTERNAL_H */
621