1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Samsung S5P Multi Format Codec v 5.1
4 *
5 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
6 * Kamil Debski, <k.debski@samsung.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/videodev2.h>
18 #include <media/v4l2-event.h>
19 #include <linux/workqueue.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_reserved_mem.h>
23 #include <media/videobuf2-v4l2.h>
24 #include "s5p_mfc_common.h"
25 #include "s5p_mfc_ctrl.h"
26 #include "s5p_mfc_debug.h"
27 #include "s5p_mfc_dec.h"
28 #include "s5p_mfc_enc.h"
29 #include "s5p_mfc_intr.h"
30 #include "s5p_mfc_iommu.h"
31 #include "s5p_mfc_opr.h"
32 #include "s5p_mfc_cmd.h"
33 #include "s5p_mfc_pm.h"
34
35 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
36 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
37
38 int mfc_debug_level;
39 module_param_named(debug, mfc_debug_level, int, 0644);
40 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
41
42 static char *mfc_mem_size;
43 module_param_named(mem, mfc_mem_size, charp, 0644);
44 MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
45
46 /* Helper functions for interrupt processing */
47
48 /* Remove from hw execution round robin */
clear_work_bit(struct s5p_mfc_ctx * ctx)49 void clear_work_bit(struct s5p_mfc_ctx *ctx)
50 {
51 struct s5p_mfc_dev *dev = ctx->dev;
52
53 spin_lock(&dev->condlock);
54 __clear_bit(ctx->num, &dev->ctx_work_bits);
55 spin_unlock(&dev->condlock);
56 }
57
58 /* Add to hw execution round robin */
set_work_bit(struct s5p_mfc_ctx * ctx)59 void set_work_bit(struct s5p_mfc_ctx *ctx)
60 {
61 struct s5p_mfc_dev *dev = ctx->dev;
62
63 spin_lock(&dev->condlock);
64 __set_bit(ctx->num, &dev->ctx_work_bits);
65 spin_unlock(&dev->condlock);
66 }
67
68 /* Remove from hw execution round robin */
clear_work_bit_irqsave(struct s5p_mfc_ctx * ctx)69 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
70 {
71 struct s5p_mfc_dev *dev = ctx->dev;
72 unsigned long flags;
73
74 spin_lock_irqsave(&dev->condlock, flags);
75 __clear_bit(ctx->num, &dev->ctx_work_bits);
76 spin_unlock_irqrestore(&dev->condlock, flags);
77 }
78
79 /* Add to hw execution round robin */
set_work_bit_irqsave(struct s5p_mfc_ctx * ctx)80 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
81 {
82 struct s5p_mfc_dev *dev = ctx->dev;
83 unsigned long flags;
84
85 spin_lock_irqsave(&dev->condlock, flags);
86 __set_bit(ctx->num, &dev->ctx_work_bits);
87 spin_unlock_irqrestore(&dev->condlock, flags);
88 }
89
s5p_mfc_get_new_ctx(struct s5p_mfc_dev * dev)90 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
91 {
92 unsigned long flags;
93 int ctx;
94
95 spin_lock_irqsave(&dev->condlock, flags);
96 ctx = dev->curr_ctx;
97 do {
98 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
99 if (ctx == dev->curr_ctx) {
100 if (!test_bit(ctx, &dev->ctx_work_bits))
101 ctx = -EAGAIN;
102 break;
103 }
104 } while (!test_bit(ctx, &dev->ctx_work_bits));
105 spin_unlock_irqrestore(&dev->condlock, flags);
106
107 return ctx;
108 }
109
110 /* Wake up context wait_queue */
wake_up_ctx(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)111 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
112 unsigned int err)
113 {
114 ctx->int_cond = 1;
115 ctx->int_type = reason;
116 ctx->int_err = err;
117 wake_up(&ctx->queue);
118 }
119
120 /* Wake up device wait_queue */
wake_up_dev(struct s5p_mfc_dev * dev,unsigned int reason,unsigned int err)121 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
122 unsigned int err)
123 {
124 dev->int_cond = 1;
125 dev->int_type = reason;
126 dev->int_err = err;
127 wake_up(&dev->queue);
128 }
129
s5p_mfc_cleanup_queue(struct list_head * lh,struct vb2_queue * vq)130 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
131 {
132 struct s5p_mfc_buf *b;
133 int i;
134
135 while (!list_empty(lh)) {
136 b = list_entry(lh->next, struct s5p_mfc_buf, list);
137 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
138 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
139 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
140 list_del(&b->list);
141 }
142 }
143
s5p_mfc_watchdog(struct timer_list * t)144 static void s5p_mfc_watchdog(struct timer_list *t)
145 {
146 struct s5p_mfc_dev *dev = from_timer(dev, t, watchdog_timer);
147
148 if (test_bit(0, &dev->hw_lock))
149 atomic_inc(&dev->watchdog_cnt);
150 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
151 /*
152 * This means that hw is busy and no interrupts were
153 * generated by hw for the Nth time of running this
154 * watchdog timer. This usually means a serious hw
155 * error. Now it is time to kill all instances and
156 * reset the MFC.
157 */
158 mfc_err("Time out during waiting for HW\n");
159 schedule_work(&dev->watchdog_work);
160 }
161 dev->watchdog_timer.expires = jiffies +
162 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
163 add_timer(&dev->watchdog_timer);
164 }
165
s5p_mfc_watchdog_worker(struct work_struct * work)166 static void s5p_mfc_watchdog_worker(struct work_struct *work)
167 {
168 struct s5p_mfc_dev *dev;
169 struct s5p_mfc_ctx *ctx;
170 unsigned long flags;
171 int mutex_locked;
172 int i, ret;
173
174 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
175
176 mfc_err("Driver timeout error handling\n");
177 /*
178 * Lock the mutex that protects open and release.
179 * This is necessary as they may load and unload firmware.
180 */
181 mutex_locked = mutex_trylock(&dev->mfc_mutex);
182 if (!mutex_locked)
183 mfc_err("Error: some instance may be closing/opening\n");
184 spin_lock_irqsave(&dev->irqlock, flags);
185
186 s5p_mfc_clock_off();
187
188 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
189 ctx = dev->ctx[i];
190 if (!ctx)
191 continue;
192 ctx->state = MFCINST_ERROR;
193 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
194 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
195 clear_work_bit(ctx);
196 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
197 }
198 clear_bit(0, &dev->hw_lock);
199 spin_unlock_irqrestore(&dev->irqlock, flags);
200
201 /* De-init MFC */
202 s5p_mfc_deinit_hw(dev);
203
204 /*
205 * Double check if there is at least one instance running.
206 * If no instance is in memory than no firmware should be present
207 */
208 if (dev->num_inst > 0) {
209 ret = s5p_mfc_load_firmware(dev);
210 if (ret) {
211 mfc_err("Failed to reload FW\n");
212 goto unlock;
213 }
214 s5p_mfc_clock_on();
215 ret = s5p_mfc_init_hw(dev);
216 s5p_mfc_clock_off();
217 if (ret)
218 mfc_err("Failed to reinit FW\n");
219 }
220 unlock:
221 if (mutex_locked)
222 mutex_unlock(&dev->mfc_mutex);
223 }
224
s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx * ctx)225 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
226 {
227 struct s5p_mfc_buf *dst_buf;
228 struct s5p_mfc_dev *dev = ctx->dev;
229
230 ctx->state = MFCINST_FINISHED;
231 ctx->sequence++;
232 while (!list_empty(&ctx->dst_queue)) {
233 dst_buf = list_entry(ctx->dst_queue.next,
234 struct s5p_mfc_buf, list);
235 mfc_debug(2, "Cleaning up buffer: %d\n",
236 dst_buf->b->vb2_buf.index);
237 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
238 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
239 list_del(&dst_buf->list);
240 dst_buf->flags |= MFC_BUF_FLAG_EOS;
241 ctx->dst_queue_cnt--;
242 dst_buf->b->sequence = (ctx->sequence++);
243
244 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
245 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
246 dst_buf->b->field = V4L2_FIELD_NONE;
247 else
248 dst_buf->b->field = V4L2_FIELD_INTERLACED;
249 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
250
251 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
252 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
253 }
254 }
255
s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx * ctx)256 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
257 {
258 struct s5p_mfc_dev *dev = ctx->dev;
259 struct s5p_mfc_buf *dst_buf, *src_buf;
260 u32 dec_y_addr;
261 unsigned int frame_type;
262
263 /* Make sure we actually have a new frame before continuing. */
264 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
265 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
266 return;
267 dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
268
269 /*
270 * Copy timestamp / timecode from decoded src to dst and set
271 * appropriate flags.
272 */
273 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
274 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
275 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
276
277 if (addr == dec_y_addr) {
278 dst_buf->b->timecode = src_buf->b->timecode;
279 dst_buf->b->vb2_buf.timestamp =
280 src_buf->b->vb2_buf.timestamp;
281 dst_buf->b->flags &=
282 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
283 dst_buf->b->flags |=
284 src_buf->b->flags
285 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
286 switch (frame_type) {
287 case S5P_FIMV_DECODE_FRAME_I_FRAME:
288 dst_buf->b->flags |=
289 V4L2_BUF_FLAG_KEYFRAME;
290 break;
291 case S5P_FIMV_DECODE_FRAME_P_FRAME:
292 dst_buf->b->flags |=
293 V4L2_BUF_FLAG_PFRAME;
294 break;
295 case S5P_FIMV_DECODE_FRAME_B_FRAME:
296 dst_buf->b->flags |=
297 V4L2_BUF_FLAG_BFRAME;
298 break;
299 default:
300 /*
301 * Don't know how to handle
302 * S5P_FIMV_DECODE_FRAME_OTHER_FRAME.
303 */
304 mfc_debug(2, "Unexpected frame type: %d\n",
305 frame_type);
306 }
307 break;
308 }
309 }
310 }
311
s5p_mfc_handle_frame_new(struct s5p_mfc_ctx * ctx,unsigned int err)312 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
313 {
314 struct s5p_mfc_dev *dev = ctx->dev;
315 struct s5p_mfc_buf *dst_buf;
316 u32 dspl_y_addr;
317 unsigned int frame_type;
318
319 dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
320 if (IS_MFCV6_PLUS(dev))
321 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
322 get_disp_frame_type, ctx);
323 else
324 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
325 get_dec_frame_type, dev);
326
327 /* If frame is same as previous then skip and do not dequeue */
328 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
329 if (!ctx->after_packed_pb)
330 ctx->sequence++;
331 ctx->after_packed_pb = 0;
332 return;
333 }
334 ctx->sequence++;
335 /*
336 * The MFC returns address of the buffer, now we have to
337 * check which vb2_buffer does it correspond to
338 */
339 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
340 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
341
342 /* Check if this is the buffer we're looking for */
343 if (addr == dspl_y_addr) {
344 list_del(&dst_buf->list);
345 ctx->dst_queue_cnt--;
346 dst_buf->b->sequence = ctx->sequence;
347 if (s5p_mfc_hw_call(dev->mfc_ops,
348 get_pic_type_top, ctx) ==
349 s5p_mfc_hw_call(dev->mfc_ops,
350 get_pic_type_bot, ctx))
351 dst_buf->b->field = V4L2_FIELD_NONE;
352 else
353 dst_buf->b->field =
354 V4L2_FIELD_INTERLACED;
355 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
356 ctx->luma_size);
357 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
358 ctx->chroma_size);
359 clear_bit(dst_buf->b->vb2_buf.index,
360 &ctx->dec_dst_flag);
361
362 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
363 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
364
365 break;
366 }
367 }
368 }
369
370 /* Handle frame decoding interrupt */
s5p_mfc_handle_frame(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)371 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
372 unsigned int reason, unsigned int err)
373 {
374 struct s5p_mfc_dev *dev = ctx->dev;
375 unsigned int dst_frame_status;
376 unsigned int dec_frame_status;
377 struct s5p_mfc_buf *src_buf;
378 unsigned int res_change;
379
380 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
381 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
382 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
383 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
384 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
385 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
386 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
387 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
388 if (ctx->state == MFCINST_RES_CHANGE_INIT)
389 ctx->state = MFCINST_RES_CHANGE_FLUSH;
390 if (res_change == S5P_FIMV_RES_INCREASE ||
391 res_change == S5P_FIMV_RES_DECREASE) {
392 ctx->state = MFCINST_RES_CHANGE_INIT;
393 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
394 wake_up_ctx(ctx, reason, err);
395 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
396 s5p_mfc_clock_off();
397 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
398 return;
399 }
400 if (ctx->dpb_flush_flag)
401 ctx->dpb_flush_flag = 0;
402
403 /* All frames remaining in the buffer have been extracted */
404 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
405 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
406 static const struct v4l2_event ev_src_ch = {
407 .type = V4L2_EVENT_SOURCE_CHANGE,
408 .u.src_change.changes =
409 V4L2_EVENT_SRC_CH_RESOLUTION,
410 };
411
412 s5p_mfc_handle_frame_all_extracted(ctx);
413 ctx->state = MFCINST_RES_CHANGE_END;
414 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
415
416 goto leave_handle_frame;
417 } else {
418 s5p_mfc_handle_frame_all_extracted(ctx);
419 }
420 }
421
422 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
423 s5p_mfc_handle_frame_copy_time(ctx);
424
425 /* A frame has been decoded and is in the buffer */
426 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
427 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
428 s5p_mfc_handle_frame_new(ctx, err);
429 } else {
430 mfc_debug(2, "No frame decode\n");
431 }
432 /* Mark source buffer as complete */
433 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
434 && !list_empty(&ctx->src_queue)) {
435 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
436 list);
437 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
438 get_consumed_stream, dev);
439 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
440 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
441 ctx->consumed_stream + STUFF_BYTE <
442 src_buf->b->vb2_buf.planes[0].bytesused) {
443 /* Run MFC again on the same buffer */
444 mfc_debug(2, "Running again the same buffer\n");
445 ctx->after_packed_pb = 1;
446 } else {
447 mfc_debug(2, "MFC needs next buffer\n");
448 ctx->consumed_stream = 0;
449 if (src_buf->flags & MFC_BUF_FLAG_EOS)
450 ctx->state = MFCINST_FINISHING;
451 list_del(&src_buf->list);
452 ctx->src_queue_cnt--;
453 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
454 vb2_buffer_done(&src_buf->b->vb2_buf,
455 VB2_BUF_STATE_ERROR);
456 else
457 vb2_buffer_done(&src_buf->b->vb2_buf,
458 VB2_BUF_STATE_DONE);
459 }
460 }
461 leave_handle_frame:
462 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
463 || ctx->dst_queue_cnt < ctx->pb_count)
464 clear_work_bit(ctx);
465 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
466 wake_up_ctx(ctx, reason, err);
467 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
468 s5p_mfc_clock_off();
469 /* if suspending, wake up device and do not try_run again*/
470 if (test_bit(0, &dev->enter_suspend))
471 wake_up_dev(dev, reason, err);
472 else
473 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
474 }
475
476 /* Error handling for interrupt */
s5p_mfc_handle_error(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)477 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
478 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
479 {
480 mfc_err("Interrupt Error: %08x\n", err);
481
482 if (ctx) {
483 /* Error recovery is dependent on the state of context */
484 switch (ctx->state) {
485 case MFCINST_RES_CHANGE_INIT:
486 case MFCINST_RES_CHANGE_FLUSH:
487 case MFCINST_RES_CHANGE_END:
488 case MFCINST_FINISHING:
489 case MFCINST_FINISHED:
490 case MFCINST_RUNNING:
491 /*
492 * It is highly probable that an error occurred
493 * while decoding a frame
494 */
495 clear_work_bit(ctx);
496 ctx->state = MFCINST_ERROR;
497 /* Mark all dst buffers as having an error */
498 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
499 /* Mark all src buffers as having an error */
500 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
501 wake_up_ctx(ctx, reason, err);
502 break;
503 default:
504 clear_work_bit(ctx);
505 ctx->state = MFCINST_ERROR;
506 wake_up_ctx(ctx, reason, err);
507 break;
508 }
509 }
510 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
511 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
512 s5p_mfc_clock_off();
513 wake_up_dev(dev, reason, err);
514 }
515
516 /* Header parsing interrupt handling */
s5p_mfc_handle_seq_done(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)517 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
518 unsigned int reason, unsigned int err)
519 {
520 struct s5p_mfc_dev *dev;
521
522 if (!ctx)
523 return;
524 dev = ctx->dev;
525 if (ctx->c_ops->post_seq_start) {
526 if (ctx->c_ops->post_seq_start(ctx))
527 mfc_err("post_seq_start() failed\n");
528 } else {
529 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
530 dev);
531 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
532 dev);
533
534 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
535
536 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
537 dev);
538 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
539 dev);
540 if (FW_HAS_E_MIN_SCRATCH_BUF(dev))
541 ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
542 get_min_scratch_buf_size, dev);
543 if (ctx->img_width == 0 || ctx->img_height == 0)
544 ctx->state = MFCINST_ERROR;
545 else
546 ctx->state = MFCINST_HEAD_PARSED;
547
548 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
549 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
550 !list_empty(&ctx->src_queue)) {
551 struct s5p_mfc_buf *src_buf;
552
553 src_buf = list_entry(ctx->src_queue.next,
554 struct s5p_mfc_buf, list);
555 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
556 dev) <
557 src_buf->b->vb2_buf.planes[0].bytesused)
558 ctx->head_processed = 0;
559 else
560 ctx->head_processed = 1;
561 } else {
562 ctx->head_processed = 1;
563 }
564 }
565 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
566 clear_work_bit(ctx);
567 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
568 s5p_mfc_clock_off();
569 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
570 wake_up_ctx(ctx, reason, err);
571 }
572
573 /* Header parsing interrupt handling */
s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)574 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
575 unsigned int reason, unsigned int err)
576 {
577 struct s5p_mfc_buf *src_buf;
578 struct s5p_mfc_dev *dev;
579
580 if (!ctx)
581 return;
582 dev = ctx->dev;
583 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
584 ctx->int_type = reason;
585 ctx->int_err = err;
586 ctx->int_cond = 1;
587 clear_work_bit(ctx);
588 if (err == 0) {
589 ctx->state = MFCINST_RUNNING;
590 if (!ctx->dpb_flush_flag && ctx->head_processed) {
591 if (!list_empty(&ctx->src_queue)) {
592 src_buf = list_entry(ctx->src_queue.next,
593 struct s5p_mfc_buf, list);
594 list_del(&src_buf->list);
595 ctx->src_queue_cnt--;
596 vb2_buffer_done(&src_buf->b->vb2_buf,
597 VB2_BUF_STATE_DONE);
598 }
599 } else {
600 ctx->dpb_flush_flag = 0;
601 }
602 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
603
604 s5p_mfc_clock_off();
605
606 wake_up(&ctx->queue);
607 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
608 } else {
609 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
610
611 s5p_mfc_clock_off();
612
613 wake_up(&ctx->queue);
614 }
615 }
616
s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx * ctx)617 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
618 {
619 struct s5p_mfc_dev *dev = ctx->dev;
620 struct s5p_mfc_buf *mb_entry;
621
622 mfc_debug(2, "Stream completed\n");
623
624 ctx->state = MFCINST_FINISHED;
625
626 if (!list_empty(&ctx->dst_queue)) {
627 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
628 list);
629 list_del(&mb_entry->list);
630 ctx->dst_queue_cnt--;
631 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
632 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
633 }
634
635 clear_work_bit(ctx);
636
637 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
638
639 s5p_mfc_clock_off();
640 wake_up(&ctx->queue);
641 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
642 }
643
644 /* Interrupt processing */
s5p_mfc_irq(int irq,void * priv)645 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
646 {
647 struct s5p_mfc_dev *dev = priv;
648 struct s5p_mfc_ctx *ctx;
649 unsigned int reason;
650 unsigned int err;
651
652 mfc_debug_enter();
653 /* Reset the timeout watchdog */
654 atomic_set(&dev->watchdog_cnt, 0);
655 spin_lock(&dev->irqlock);
656 ctx = dev->ctx[dev->curr_ctx];
657 /* Get the reason of interrupt and the error code */
658 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
659 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
660 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
661 switch (reason) {
662 case S5P_MFC_R2H_CMD_ERR_RET:
663 /* An error has occurred */
664 if (ctx->state == MFCINST_RUNNING &&
665 (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
666 dev->warn_start ||
667 err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
668 err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
669 err == S5P_FIMV_ERR_TIMEOUT))
670 s5p_mfc_handle_frame(ctx, reason, err);
671 else
672 s5p_mfc_handle_error(dev, ctx, reason, err);
673 clear_bit(0, &dev->enter_suspend);
674 break;
675
676 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
677 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
678 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
679 if (ctx->c_ops->post_frame_start) {
680 if (ctx->c_ops->post_frame_start(ctx))
681 mfc_err("post_frame_start() failed\n");
682
683 if (ctx->state == MFCINST_FINISHING &&
684 list_empty(&ctx->ref_queue)) {
685 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
686 s5p_mfc_handle_stream_complete(ctx);
687 break;
688 }
689 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
690 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
691 s5p_mfc_clock_off();
692 wake_up_ctx(ctx, reason, err);
693 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
694 } else {
695 s5p_mfc_handle_frame(ctx, reason, err);
696 }
697 break;
698
699 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
700 s5p_mfc_handle_seq_done(ctx, reason, err);
701 break;
702
703 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
704 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
705 ctx->state = MFCINST_GOT_INST;
706 goto irq_cleanup_hw;
707
708 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
709 ctx->inst_no = MFC_NO_INSTANCE_SET;
710 ctx->state = MFCINST_FREE;
711 goto irq_cleanup_hw;
712
713 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
714 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
715 case S5P_MFC_R2H_CMD_SLEEP_RET:
716 case S5P_MFC_R2H_CMD_WAKEUP_RET:
717 if (ctx)
718 clear_work_bit(ctx);
719 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
720 clear_bit(0, &dev->hw_lock);
721 clear_bit(0, &dev->enter_suspend);
722 wake_up_dev(dev, reason, err);
723 break;
724
725 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
726 s5p_mfc_handle_init_buffers(ctx, reason, err);
727 break;
728
729 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
730 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
731 ctx->int_type = reason;
732 ctx->int_err = err;
733 s5p_mfc_handle_stream_complete(ctx);
734 break;
735
736 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
737 ctx->state = MFCINST_RUNNING;
738 goto irq_cleanup_hw;
739
740 default:
741 mfc_debug(2, "Unknown int reason\n");
742 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
743 }
744 spin_unlock(&dev->irqlock);
745 mfc_debug_leave();
746 return IRQ_HANDLED;
747 irq_cleanup_hw:
748 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
749 ctx->int_type = reason;
750 ctx->int_err = err;
751 ctx->int_cond = 1;
752 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
753 mfc_err("Failed to unlock hw\n");
754
755 s5p_mfc_clock_off();
756 clear_work_bit(ctx);
757 wake_up(&ctx->queue);
758
759 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
760 spin_unlock(&dev->irqlock);
761 mfc_debug(2, "Exit via irq_cleanup_hw\n");
762 return IRQ_HANDLED;
763 }
764
765 /* Open an MFC node */
s5p_mfc_open(struct file * file)766 static int s5p_mfc_open(struct file *file)
767 {
768 struct video_device *vdev = video_devdata(file);
769 struct s5p_mfc_dev *dev = video_drvdata(file);
770 struct s5p_mfc_ctx *ctx = NULL;
771 struct vb2_queue *q;
772 int ret = 0;
773
774 mfc_debug_enter();
775 if (mutex_lock_interruptible(&dev->mfc_mutex))
776 return -ERESTARTSYS;
777 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
778 /* Allocate memory for context */
779 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
780 if (!ctx) {
781 ret = -ENOMEM;
782 goto err_alloc;
783 }
784 init_waitqueue_head(&ctx->queue);
785 v4l2_fh_init(&ctx->fh, vdev);
786 file->private_data = &ctx->fh;
787 v4l2_fh_add(&ctx->fh);
788 ctx->dev = dev;
789 INIT_LIST_HEAD(&ctx->src_queue);
790 INIT_LIST_HEAD(&ctx->dst_queue);
791 ctx->src_queue_cnt = 0;
792 ctx->dst_queue_cnt = 0;
793 /* Get context number */
794 ctx->num = 0;
795 while (dev->ctx[ctx->num]) {
796 ctx->num++;
797 if (ctx->num >= MFC_NUM_CONTEXTS) {
798 mfc_debug(2, "Too many open contexts\n");
799 ret = -EBUSY;
800 goto err_no_ctx;
801 }
802 }
803 /* Mark context as idle */
804 clear_work_bit_irqsave(ctx);
805 dev->ctx[ctx->num] = ctx;
806 if (vdev == dev->vfd_dec) {
807 ctx->type = MFCINST_DECODER;
808 ctx->c_ops = get_dec_codec_ops();
809 s5p_mfc_dec_init(ctx);
810 /* Setup ctrl handler */
811 ret = s5p_mfc_dec_ctrls_setup(ctx);
812 if (ret) {
813 mfc_err("Failed to setup mfc controls\n");
814 goto err_ctrls_setup;
815 }
816 } else if (vdev == dev->vfd_enc) {
817 ctx->type = MFCINST_ENCODER;
818 ctx->c_ops = get_enc_codec_ops();
819 /* only for encoder */
820 INIT_LIST_HEAD(&ctx->ref_queue);
821 ctx->ref_queue_cnt = 0;
822 s5p_mfc_enc_init(ctx);
823 /* Setup ctrl handler */
824 ret = s5p_mfc_enc_ctrls_setup(ctx);
825 if (ret) {
826 mfc_err("Failed to setup mfc controls\n");
827 goto err_ctrls_setup;
828 }
829 } else {
830 ret = -ENOENT;
831 goto err_bad_node;
832 }
833 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
834 ctx->inst_no = MFC_NO_INSTANCE_SET;
835 /* Load firmware if this is the first instance */
836 if (dev->num_inst == 1) {
837 dev->watchdog_timer.expires = jiffies +
838 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
839 add_timer(&dev->watchdog_timer);
840 ret = s5p_mfc_power_on();
841 if (ret < 0) {
842 mfc_err("power on failed\n");
843 goto err_pwr_enable;
844 }
845 s5p_mfc_clock_on();
846 ret = s5p_mfc_load_firmware(dev);
847 if (ret) {
848 s5p_mfc_clock_off();
849 goto err_load_fw;
850 }
851 /* Init the FW */
852 ret = s5p_mfc_init_hw(dev);
853 s5p_mfc_clock_off();
854 if (ret)
855 goto err_init_hw;
856 }
857 /* Init videobuf2 queue for CAPTURE */
858 q = &ctx->vq_dst;
859 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
860 q->drv_priv = &ctx->fh;
861 q->lock = &dev->mfc_mutex;
862 if (vdev == dev->vfd_dec) {
863 q->io_modes = VB2_MMAP;
864 q->ops = get_dec_queue_ops();
865 } else if (vdev == dev->vfd_enc) {
866 q->io_modes = VB2_MMAP | VB2_USERPTR;
867 q->ops = get_enc_queue_ops();
868 } else {
869 ret = -ENOENT;
870 goto err_queue_init;
871 }
872 /*
873 * We'll do mostly sequential access, so sacrifice TLB efficiency for
874 * faster allocation.
875 */
876 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
877 q->mem_ops = &vb2_dma_contig_memops;
878 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
879 ret = vb2_queue_init(q);
880 if (ret) {
881 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
882 goto err_queue_init;
883 }
884 /* Init videobuf2 queue for OUTPUT */
885 q = &ctx->vq_src;
886 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
887 q->drv_priv = &ctx->fh;
888 q->lock = &dev->mfc_mutex;
889 if (vdev == dev->vfd_dec) {
890 q->io_modes = VB2_MMAP;
891 q->ops = get_dec_queue_ops();
892 } else if (vdev == dev->vfd_enc) {
893 q->io_modes = VB2_MMAP | VB2_USERPTR;
894 q->ops = get_enc_queue_ops();
895 } else {
896 ret = -ENOENT;
897 goto err_queue_init;
898 }
899 /* One way to indicate end-of-stream for MFC is to set the
900 * bytesused == 0. However by default videobuf2 handles bytesused
901 * equal to 0 as a special case and changes its value to the size
902 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
903 * will keep the value of bytesused intact.
904 */
905 q->allow_zero_bytesused = 1;
906
907 /*
908 * We'll do mostly sequential access, so sacrifice TLB efficiency for
909 * faster allocation.
910 */
911 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
912 q->mem_ops = &vb2_dma_contig_memops;
913 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
914 ret = vb2_queue_init(q);
915 if (ret) {
916 mfc_err("Failed to initialize videobuf2 queue(output)\n");
917 goto err_queue_init;
918 }
919 mutex_unlock(&dev->mfc_mutex);
920 mfc_debug_leave();
921 return ret;
922 /* Deinit when failure occurred */
923 err_queue_init:
924 if (dev->num_inst == 1)
925 s5p_mfc_deinit_hw(dev);
926 err_init_hw:
927 err_load_fw:
928 err_pwr_enable:
929 if (dev->num_inst == 1) {
930 if (s5p_mfc_power_off() < 0)
931 mfc_err("power off failed\n");
932 del_timer_sync(&dev->watchdog_timer);
933 }
934 err_ctrls_setup:
935 s5p_mfc_dec_ctrls_delete(ctx);
936 err_bad_node:
937 dev->ctx[ctx->num] = NULL;
938 err_no_ctx:
939 v4l2_fh_del(&ctx->fh);
940 v4l2_fh_exit(&ctx->fh);
941 kfree(ctx);
942 err_alloc:
943 dev->num_inst--;
944 mutex_unlock(&dev->mfc_mutex);
945 mfc_debug_leave();
946 return ret;
947 }
948
949 /* Release MFC context */
s5p_mfc_release(struct file * file)950 static int s5p_mfc_release(struct file *file)
951 {
952 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
953 struct s5p_mfc_dev *dev = ctx->dev;
954
955 /* if dev is null, do cleanup that doesn't need dev */
956 mfc_debug_enter();
957 if (dev)
958 mutex_lock(&dev->mfc_mutex);
959 vb2_queue_release(&ctx->vq_src);
960 vb2_queue_release(&ctx->vq_dst);
961 if (dev) {
962 s5p_mfc_clock_on();
963
964 /* Mark context as idle */
965 clear_work_bit_irqsave(ctx);
966 /*
967 * If instance was initialised and not yet freed,
968 * return instance and free resources
969 */
970 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
971 mfc_debug(2, "Has to free instance\n");
972 s5p_mfc_close_mfc_inst(dev, ctx);
973 }
974 /* hardware locking scheme */
975 if (dev->curr_ctx == ctx->num)
976 clear_bit(0, &dev->hw_lock);
977 dev->num_inst--;
978 if (dev->num_inst == 0) {
979 mfc_debug(2, "Last instance\n");
980 s5p_mfc_deinit_hw(dev);
981 del_timer_sync(&dev->watchdog_timer);
982 s5p_mfc_clock_off();
983 if (s5p_mfc_power_off() < 0)
984 mfc_err("Power off failed\n");
985 } else {
986 mfc_debug(2, "Shutting down clock\n");
987 s5p_mfc_clock_off();
988 }
989 }
990 if (dev)
991 dev->ctx[ctx->num] = NULL;
992 s5p_mfc_dec_ctrls_delete(ctx);
993 v4l2_fh_del(&ctx->fh);
994 /* vdev is gone if dev is null */
995 if (dev)
996 v4l2_fh_exit(&ctx->fh);
997 kfree(ctx);
998 mfc_debug_leave();
999 if (dev)
1000 mutex_unlock(&dev->mfc_mutex);
1001
1002 return 0;
1003 }
1004
1005 /* Poll */
s5p_mfc_poll(struct file * file,struct poll_table_struct * wait)1006 static __poll_t s5p_mfc_poll(struct file *file,
1007 struct poll_table_struct *wait)
1008 {
1009 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1010 struct s5p_mfc_dev *dev = ctx->dev;
1011 struct vb2_queue *src_q, *dst_q;
1012 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
1013 __poll_t rc = 0;
1014 unsigned long flags;
1015
1016 mutex_lock(&dev->mfc_mutex);
1017 src_q = &ctx->vq_src;
1018 dst_q = &ctx->vq_dst;
1019 /*
1020 * There has to be at least one buffer queued on each queued_list, which
1021 * means either in driver already or waiting for driver to claim it
1022 * and start processing.
1023 */
1024 if ((!vb2_is_streaming(src_q) || list_empty(&src_q->queued_list)) &&
1025 (!vb2_is_streaming(dst_q) || list_empty(&dst_q->queued_list))) {
1026 rc = EPOLLERR;
1027 goto end;
1028 }
1029 mutex_unlock(&dev->mfc_mutex);
1030 poll_wait(file, &ctx->fh.wait, wait);
1031 poll_wait(file, &src_q->done_wq, wait);
1032 poll_wait(file, &dst_q->done_wq, wait);
1033 mutex_lock(&dev->mfc_mutex);
1034 if (v4l2_event_pending(&ctx->fh))
1035 rc |= EPOLLPRI;
1036 spin_lock_irqsave(&src_q->done_lock, flags);
1037 if (!list_empty(&src_q->done_list))
1038 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1039 done_entry);
1040 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1041 || src_vb->state == VB2_BUF_STATE_ERROR))
1042 rc |= EPOLLOUT | EPOLLWRNORM;
1043 spin_unlock_irqrestore(&src_q->done_lock, flags);
1044 spin_lock_irqsave(&dst_q->done_lock, flags);
1045 if (!list_empty(&dst_q->done_list))
1046 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1047 done_entry);
1048 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1049 || dst_vb->state == VB2_BUF_STATE_ERROR))
1050 rc |= EPOLLIN | EPOLLRDNORM;
1051 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1052 end:
1053 mutex_unlock(&dev->mfc_mutex);
1054 return rc;
1055 }
1056
1057 /* Mmap */
s5p_mfc_mmap(struct file * file,struct vm_area_struct * vma)1058 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1059 {
1060 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1061 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1062 int ret;
1063
1064 if (offset < DST_QUEUE_OFF_BASE) {
1065 mfc_debug(2, "mmapping source\n");
1066 ret = vb2_mmap(&ctx->vq_src, vma);
1067 } else { /* capture */
1068 mfc_debug(2, "mmapping destination\n");
1069 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1070 ret = vb2_mmap(&ctx->vq_dst, vma);
1071 }
1072 return ret;
1073 }
1074
1075 /* v4l2 ops */
1076 static const struct v4l2_file_operations s5p_mfc_fops = {
1077 .owner = THIS_MODULE,
1078 .open = s5p_mfc_open,
1079 .release = s5p_mfc_release,
1080 .poll = s5p_mfc_poll,
1081 .unlocked_ioctl = video_ioctl2,
1082 .mmap = s5p_mfc_mmap,
1083 };
1084
1085 /* DMA memory related helper functions */
s5p_mfc_memdev_release(struct device * dev)1086 static void s5p_mfc_memdev_release(struct device *dev)
1087 {
1088 of_reserved_mem_device_release(dev);
1089 }
1090
s5p_mfc_alloc_memdev(struct device * dev,const char * name,unsigned int idx)1091 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1092 const char *name, unsigned int idx)
1093 {
1094 struct device *child;
1095 int ret;
1096
1097 child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL);
1098 if (!child)
1099 return NULL;
1100
1101 device_initialize(child);
1102 dev_set_name(child, "%s:%s", dev_name(dev), name);
1103 child->parent = dev;
1104 child->coherent_dma_mask = dev->coherent_dma_mask;
1105 child->dma_mask = dev->dma_mask;
1106 child->release = s5p_mfc_memdev_release;
1107 child->dma_parms = devm_kzalloc(dev, sizeof(*child->dma_parms),
1108 GFP_KERNEL);
1109 if (!child->dma_parms)
1110 goto err;
1111
1112 /*
1113 * The memdevs are not proper OF platform devices, so in order for them
1114 * to be treated as valid DMA masters we need a bit of a hack to force
1115 * them to inherit the MFC node's DMA configuration.
1116 */
1117 of_dma_configure(child, dev->of_node, true);
1118
1119 if (device_add(child) == 0) {
1120 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1121 idx);
1122 if (ret == 0)
1123 return child;
1124 device_del(child);
1125 }
1126 err:
1127 put_device(child);
1128 return NULL;
1129 }
1130
s5p_mfc_configure_2port_memory(struct s5p_mfc_dev * mfc_dev)1131 static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1132 {
1133 struct device *dev = &mfc_dev->plat_dev->dev;
1134 void *bank2_virt;
1135 dma_addr_t bank2_dma_addr;
1136 unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1137 int ret;
1138
1139 /*
1140 * Create and initialize virtual devices for accessing
1141 * reserved memory regions.
1142 */
1143 mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1144 BANK_L_CTX);
1145 if (!mfc_dev->mem_dev[BANK_L_CTX])
1146 return -ENODEV;
1147 mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1148 BANK_R_CTX);
1149 if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1150 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1151 return -ENODEV;
1152 }
1153
1154 /* Allocate memory for firmware and initialize both banks addresses */
1155 ret = s5p_mfc_alloc_firmware(mfc_dev);
1156 if (ret) {
1157 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1158 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1159 return ret;
1160 }
1161
1162 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1163
1164 bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1165 align_size, &bank2_dma_addr, GFP_KERNEL);
1166 if (!bank2_virt) {
1167 s5p_mfc_release_firmware(mfc_dev);
1168 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1169 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1170 return -ENOMEM;
1171 }
1172
1173 /* Valid buffers passed to MFC encoder with LAST_FRAME command
1174 * should not have address of bank2 - MFC will treat it as a null frame.
1175 * To avoid such situation we set bank2 address below the pool address.
1176 */
1177 mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1178
1179 dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1180 bank2_dma_addr);
1181
1182 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1183 DMA_BIT_MASK(32));
1184 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1185 DMA_BIT_MASK(32));
1186
1187 return 0;
1188 }
1189
s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev * mfc_dev)1190 static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1191 {
1192 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1193 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1194 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1195 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1196 }
1197
s5p_mfc_configure_common_memory(struct s5p_mfc_dev * mfc_dev)1198 static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1199 {
1200 struct device *dev = &mfc_dev->plat_dev->dev;
1201 unsigned long mem_size = SZ_4M;
1202
1203 if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1204 mem_size = SZ_8M;
1205
1206 if (mfc_mem_size)
1207 mem_size = memparse(mfc_mem_size, NULL);
1208
1209 mfc_dev->mem_bitmap = bitmap_zalloc(mem_size >> PAGE_SHIFT, GFP_KERNEL);
1210 if (!mfc_dev->mem_bitmap)
1211 return -ENOMEM;
1212
1213 mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1214 &mfc_dev->mem_base, GFP_KERNEL);
1215 if (!mfc_dev->mem_virt) {
1216 bitmap_free(mfc_dev->mem_bitmap);
1217 dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1218 (mem_size / SZ_1M));
1219 return -ENOMEM;
1220 }
1221 mfc_dev->mem_size = mem_size;
1222 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1223 mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1224
1225 /*
1226 * MFC hardware cannot handle 0 as a base address, so mark first 128K
1227 * as used (to keep required base alignment) and adjust base address
1228 */
1229 if (mfc_dev->mem_base == (dma_addr_t)0) {
1230 unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1231
1232 bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1233 mfc_dev->dma_base[BANK_L_CTX] += offset;
1234 mfc_dev->dma_base[BANK_R_CTX] += offset;
1235 }
1236
1237 /* Firmware allocation cannot fail in this case */
1238 s5p_mfc_alloc_firmware(mfc_dev);
1239
1240 mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1241 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1242
1243 dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1244 (mem_size / SZ_1M));
1245
1246 return 0;
1247 }
1248
s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev * mfc_dev)1249 static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1250 {
1251 struct device *dev = &mfc_dev->plat_dev->dev;
1252
1253 dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1254 mfc_dev->mem_base);
1255 bitmap_free(mfc_dev->mem_bitmap);
1256 vb2_dma_contig_clear_max_seg_size(dev);
1257 }
1258
s5p_mfc_configure_dma_memory(struct s5p_mfc_dev * mfc_dev)1259 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1260 {
1261 struct device *dev = &mfc_dev->plat_dev->dev;
1262
1263 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1264 return s5p_mfc_configure_common_memory(mfc_dev);
1265 else
1266 return s5p_mfc_configure_2port_memory(mfc_dev);
1267 }
1268
s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev * mfc_dev)1269 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1270 {
1271 struct device *dev = &mfc_dev->plat_dev->dev;
1272
1273 s5p_mfc_release_firmware(mfc_dev);
1274 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1275 s5p_mfc_unconfigure_common_memory(mfc_dev);
1276 else
1277 s5p_mfc_unconfigure_2port_memory(mfc_dev);
1278 }
1279
1280 /* MFC probe function */
s5p_mfc_probe(struct platform_device * pdev)1281 static int s5p_mfc_probe(struct platform_device *pdev)
1282 {
1283 struct s5p_mfc_dev *dev;
1284 struct video_device *vfd;
1285 int ret;
1286
1287 pr_debug("%s++\n", __func__);
1288 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1289 if (!dev)
1290 return -ENOMEM;
1291
1292 spin_lock_init(&dev->irqlock);
1293 spin_lock_init(&dev->condlock);
1294 dev->plat_dev = pdev;
1295 if (!dev->plat_dev) {
1296 mfc_err("No platform data specified\n");
1297 return -ENODEV;
1298 }
1299
1300 dev->variant = of_device_get_match_data(&pdev->dev);
1301 if (!dev->variant) {
1302 dev_err(&pdev->dev, "Failed to get device MFC hardware variant information\n");
1303 return -ENOENT;
1304 }
1305
1306 dev->regs_base = devm_platform_ioremap_resource(pdev, 0);
1307 if (IS_ERR(dev->regs_base))
1308 return PTR_ERR(dev->regs_base);
1309
1310 ret = platform_get_irq(pdev, 0);
1311 if (ret < 0)
1312 return ret;
1313 dev->irq = ret;
1314 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1315 0, pdev->name, dev);
1316 if (ret) {
1317 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1318 return ret;
1319 }
1320
1321 ret = s5p_mfc_configure_dma_memory(dev);
1322 if (ret < 0) {
1323 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1324 return ret;
1325 }
1326
1327 ret = s5p_mfc_init_pm(dev);
1328 if (ret < 0) {
1329 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1330 goto err_dma;
1331 }
1332
1333 /*
1334 * Load fails if fs isn't mounted. Try loading anyway.
1335 * _open() will load it, it fails now. Ignore failure.
1336 */
1337 s5p_mfc_load_firmware(dev);
1338
1339 mutex_init(&dev->mfc_mutex);
1340 init_waitqueue_head(&dev->queue);
1341 dev->hw_lock = 0;
1342 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1343 atomic_set(&dev->watchdog_cnt, 0);
1344 timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0);
1345
1346 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1347 if (ret)
1348 goto err_v4l2_dev_reg;
1349
1350 /* decoder */
1351 vfd = video_device_alloc();
1352 if (!vfd) {
1353 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1354 ret = -ENOMEM;
1355 goto err_dec_alloc;
1356 }
1357 vfd->fops = &s5p_mfc_fops;
1358 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1359 vfd->release = video_device_release;
1360 vfd->lock = &dev->mfc_mutex;
1361 vfd->v4l2_dev = &dev->v4l2_dev;
1362 vfd->vfl_dir = VFL_DIR_M2M;
1363 vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1364 set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags);
1365 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1366 dev->vfd_dec = vfd;
1367 video_set_drvdata(vfd, dev);
1368
1369 /* encoder */
1370 vfd = video_device_alloc();
1371 if (!vfd) {
1372 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1373 ret = -ENOMEM;
1374 goto err_enc_alloc;
1375 }
1376 vfd->fops = &s5p_mfc_fops;
1377 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1378 vfd->release = video_device_release;
1379 vfd->lock = &dev->mfc_mutex;
1380 vfd->v4l2_dev = &dev->v4l2_dev;
1381 vfd->vfl_dir = VFL_DIR_M2M;
1382 vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1383 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1384 dev->vfd_enc = vfd;
1385 video_set_drvdata(vfd, dev);
1386 platform_set_drvdata(pdev, dev);
1387
1388 /* Initialize HW ops and commands based on MFC version */
1389 s5p_mfc_init_hw_ops(dev);
1390 s5p_mfc_init_hw_cmds(dev);
1391 s5p_mfc_init_regs(dev);
1392
1393 /* Register decoder and encoder */
1394 ret = video_register_device(dev->vfd_dec, VFL_TYPE_VIDEO, 0);
1395 if (ret) {
1396 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1397 goto err_dec_reg;
1398 }
1399 v4l2_info(&dev->v4l2_dev,
1400 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1401
1402 ret = video_register_device(dev->vfd_enc, VFL_TYPE_VIDEO, 0);
1403 if (ret) {
1404 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1405 goto err_enc_reg;
1406 }
1407 v4l2_info(&dev->v4l2_dev,
1408 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1409
1410 pr_debug("%s--\n", __func__);
1411 return 0;
1412
1413 /* Deinit MFC if probe had failed */
1414 err_enc_reg:
1415 video_unregister_device(dev->vfd_dec);
1416 dev->vfd_dec = NULL;
1417 err_dec_reg:
1418 video_device_release(dev->vfd_enc);
1419 err_enc_alloc:
1420 video_device_release(dev->vfd_dec);
1421 err_dec_alloc:
1422 v4l2_device_unregister(&dev->v4l2_dev);
1423 err_v4l2_dev_reg:
1424 s5p_mfc_final_pm(dev);
1425 err_dma:
1426 s5p_mfc_unconfigure_dma_memory(dev);
1427
1428 pr_debug("%s-- with error\n", __func__);
1429 return ret;
1430
1431 }
1432
1433 /* Remove the driver */
s5p_mfc_remove(struct platform_device * pdev)1434 static int s5p_mfc_remove(struct platform_device *pdev)
1435 {
1436 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1437 struct s5p_mfc_ctx *ctx;
1438 int i;
1439
1440 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1441
1442 /*
1443 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1444 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1445 * after s5p_mfc_remove() is run during unbind.
1446 */
1447 mutex_lock(&dev->mfc_mutex);
1448 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1449 ctx = dev->ctx[i];
1450 if (!ctx)
1451 continue;
1452 /* clear ctx->dev */
1453 ctx->dev = NULL;
1454 }
1455 mutex_unlock(&dev->mfc_mutex);
1456
1457 del_timer_sync(&dev->watchdog_timer);
1458 flush_work(&dev->watchdog_work);
1459
1460 video_unregister_device(dev->vfd_enc);
1461 video_unregister_device(dev->vfd_dec);
1462 v4l2_device_unregister(&dev->v4l2_dev);
1463 s5p_mfc_unconfigure_dma_memory(dev);
1464
1465 s5p_mfc_final_pm(dev);
1466 return 0;
1467 }
1468
1469 #ifdef CONFIG_PM_SLEEP
1470
s5p_mfc_suspend(struct device * dev)1471 static int s5p_mfc_suspend(struct device *dev)
1472 {
1473 struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1474 int ret;
1475
1476 if (m_dev->num_inst == 0)
1477 return 0;
1478
1479 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1480 mfc_err("Error: going to suspend for a second time\n");
1481 return -EIO;
1482 }
1483
1484 /* Check if we're processing then wait if it necessary. */
1485 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1486 /* Try and lock the HW */
1487 /* Wait on the interrupt waitqueue */
1488 ret = wait_event_interruptible_timeout(m_dev->queue,
1489 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1490 if (ret == 0) {
1491 mfc_err("Waiting for hardware to finish timed out\n");
1492 clear_bit(0, &m_dev->enter_suspend);
1493 return -EIO;
1494 }
1495 }
1496
1497 ret = s5p_mfc_sleep(m_dev);
1498 if (ret) {
1499 clear_bit(0, &m_dev->enter_suspend);
1500 clear_bit(0, &m_dev->hw_lock);
1501 }
1502 return ret;
1503 }
1504
s5p_mfc_resume(struct device * dev)1505 static int s5p_mfc_resume(struct device *dev)
1506 {
1507 struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1508
1509 if (m_dev->num_inst == 0)
1510 return 0;
1511 return s5p_mfc_wakeup(m_dev);
1512 }
1513 #endif
1514
1515 /* Power management */
1516 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1517 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1518 };
1519
1520 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1521 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1522 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1523 .dsc = DESC_BUF_SIZE,
1524 .shm = SHARED_BUF_SIZE,
1525 };
1526
1527 static struct s5p_mfc_buf_size buf_size_v5 = {
1528 .fw = MAX_FW_SIZE,
1529 .cpb = MAX_CPB_SIZE,
1530 .priv = &mfc_buf_size_v5,
1531 };
1532
1533 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1534 .version = MFC_VERSION,
1535 .version_bit = MFC_V5_BIT,
1536 .port_num = MFC_NUM_PORTS,
1537 .buf_size = &buf_size_v5,
1538 .fw_name[0] = "s5p-mfc.fw",
1539 .clk_names = {"mfc", "sclk_mfc"},
1540 .num_clocks = 2,
1541 .use_clock_gating = true,
1542 };
1543
1544 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1545 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1546 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1547 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1548 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1549 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1550 };
1551
1552 static struct s5p_mfc_buf_size buf_size_v6 = {
1553 .fw = MAX_FW_SIZE_V6,
1554 .cpb = MAX_CPB_SIZE_V6,
1555 .priv = &mfc_buf_size_v6,
1556 };
1557
1558 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1559 .version = MFC_VERSION_V6,
1560 .version_bit = MFC_V6_BIT,
1561 .port_num = MFC_NUM_PORTS_V6,
1562 .buf_size = &buf_size_v6,
1563 .fw_name[0] = "s5p-mfc-v6.fw",
1564 /*
1565 * v6-v2 firmware contains bug fixes and interface change
1566 * for init buffer command
1567 */
1568 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1569 .clk_names = {"mfc"},
1570 .num_clocks = 1,
1571 };
1572
1573 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1574 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1575 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1576 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1577 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1578 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1579 };
1580
1581 static struct s5p_mfc_buf_size buf_size_v7 = {
1582 .fw = MAX_FW_SIZE_V7,
1583 .cpb = MAX_CPB_SIZE_V7,
1584 .priv = &mfc_buf_size_v7,
1585 };
1586
1587 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1588 .version = MFC_VERSION_V7,
1589 .version_bit = MFC_V7_BIT,
1590 .port_num = MFC_NUM_PORTS_V7,
1591 .buf_size = &buf_size_v7,
1592 .fw_name[0] = "s5p-mfc-v7.fw",
1593 .clk_names = {"mfc"},
1594 .num_clocks = 1,
1595 };
1596
1597 static struct s5p_mfc_variant mfc_drvdata_v7_3250 = {
1598 .version = MFC_VERSION_V7,
1599 .version_bit = MFC_V7_BIT,
1600 .port_num = MFC_NUM_PORTS_V7,
1601 .buf_size = &buf_size_v7,
1602 .fw_name[0] = "s5p-mfc-v7.fw",
1603 .clk_names = {"mfc", "sclk_mfc"},
1604 .num_clocks = 2,
1605 };
1606
1607 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1608 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1609 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1610 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1611 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1612 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1613 };
1614
1615 static struct s5p_mfc_buf_size buf_size_v8 = {
1616 .fw = MAX_FW_SIZE_V8,
1617 .cpb = MAX_CPB_SIZE_V8,
1618 .priv = &mfc_buf_size_v8,
1619 };
1620
1621 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1622 .version = MFC_VERSION_V8,
1623 .version_bit = MFC_V8_BIT,
1624 .port_num = MFC_NUM_PORTS_V8,
1625 .buf_size = &buf_size_v8,
1626 .fw_name[0] = "s5p-mfc-v8.fw",
1627 .clk_names = {"mfc"},
1628 .num_clocks = 1,
1629 };
1630
1631 static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1632 .version = MFC_VERSION_V8,
1633 .version_bit = MFC_V8_BIT,
1634 .port_num = MFC_NUM_PORTS_V8,
1635 .buf_size = &buf_size_v8,
1636 .fw_name[0] = "s5p-mfc-v8.fw",
1637 .clk_names = {"pclk", "aclk", "aclk_xiu"},
1638 .num_clocks = 3,
1639 };
1640
1641 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
1642 .dev_ctx = MFC_CTX_BUF_SIZE_V10,
1643 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V10,
1644 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
1645 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V10,
1646 .hevc_enc_ctx = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
1647 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
1648 };
1649
1650 static struct s5p_mfc_buf_size buf_size_v10 = {
1651 .fw = MAX_FW_SIZE_V10,
1652 .cpb = MAX_CPB_SIZE_V10,
1653 .priv = &mfc_buf_size_v10,
1654 };
1655
1656 static struct s5p_mfc_variant mfc_drvdata_v10 = {
1657 .version = MFC_VERSION_V10,
1658 .version_bit = MFC_V10_BIT,
1659 .port_num = MFC_NUM_PORTS_V10,
1660 .buf_size = &buf_size_v10,
1661 .fw_name[0] = "s5p-mfc-v10.fw",
1662 };
1663
1664 static const struct of_device_id exynos_mfc_match[] = {
1665 {
1666 .compatible = "samsung,mfc-v5",
1667 .data = &mfc_drvdata_v5,
1668 }, {
1669 .compatible = "samsung,mfc-v6",
1670 .data = &mfc_drvdata_v6,
1671 }, {
1672 .compatible = "samsung,mfc-v7",
1673 .data = &mfc_drvdata_v7,
1674 }, {
1675 .compatible = "samsung,exynos3250-mfc",
1676 .data = &mfc_drvdata_v7_3250,
1677 }, {
1678 .compatible = "samsung,mfc-v8",
1679 .data = &mfc_drvdata_v8,
1680 }, {
1681 .compatible = "samsung,exynos5433-mfc",
1682 .data = &mfc_drvdata_v8_5433,
1683 }, {
1684 .compatible = "samsung,mfc-v10",
1685 .data = &mfc_drvdata_v10,
1686 },
1687 {},
1688 };
1689 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1690
1691 static struct platform_driver s5p_mfc_driver = {
1692 .probe = s5p_mfc_probe,
1693 .remove = s5p_mfc_remove,
1694 .driver = {
1695 .name = S5P_MFC_NAME,
1696 .pm = &s5p_mfc_pm_ops,
1697 .of_match_table = exynos_mfc_match,
1698 },
1699 };
1700
1701 module_platform_driver(s5p_mfc_driver);
1702
1703 MODULE_LICENSE("GPL");
1704 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1705 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1706
1707