1 /*
2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <cdefs.h>
9 #include <drivers/arm/smmu_v3.h>
10 #include <drivers/delay_timer.h>
11 #include <lib/mmio.h>
12 #include <arch_features.h>
13
14 /* SMMU poll number of retries */
15 #define SMMU_POLL_TIMEOUT_US U(1000)
16
smmuv3_poll(uintptr_t smmu_reg,uint32_t mask,uint32_t value)17 static int smmuv3_poll(uintptr_t smmu_reg, uint32_t mask,
18 uint32_t value)
19 {
20 uint32_t reg_val;
21 uint64_t timeout;
22
23 /* Set 1ms timeout value */
24 timeout = timeout_init_us(SMMU_POLL_TIMEOUT_US);
25 do {
26 reg_val = mmio_read_32(smmu_reg);
27 if ((reg_val & mask) == value)
28 return 0;
29 } while (!timeout_elapsed(timeout));
30
31 ERROR("Timeout polling SMMUv3 register @%p\n", (void *)smmu_reg);
32 ERROR("Read value 0x%x, expected 0x%x\n", reg_val,
33 value == 0U ? reg_val & ~mask : reg_val | mask);
34 return -1;
35 }
36
37 /*
38 * Abort all incoming transactions in order to implement a default
39 * deny policy on reset.
40 */
smmuv3_security_init(uintptr_t smmu_base)41 int __init smmuv3_security_init(uintptr_t smmu_base)
42 {
43 /* Attribute update has completed when SMMU_(S)_GBPA.Update bit is 0 */
44 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U)
45 return -1;
46
47 /*
48 * SMMU_(S)_CR0 resets to zero with all streams bypassing the SMMU,
49 * so just abort all incoming transactions.
50 */
51 mmio_setbits_32(smmu_base + SMMU_GBPA,
52 SMMU_GBPA_UPDATE | SMMU_GBPA_ABORT);
53
54 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U)
55 return -1;
56
57 /* Check if the SMMU supports secure state */
58 if ((mmio_read_32(smmu_base + SMMU_S_IDR1) &
59 SMMU_S_IDR1_SECURE_IMPL) == 0U)
60 return 0;
61
62 /* Abort all incoming secure transactions */
63 if (smmuv3_poll(smmu_base + SMMU_S_GBPA, SMMU_S_GBPA_UPDATE, 0U) != 0U)
64 return -1;
65
66 mmio_setbits_32(smmu_base + SMMU_S_GBPA,
67 SMMU_S_GBPA_UPDATE | SMMU_S_GBPA_ABORT);
68
69 return smmuv3_poll(smmu_base + SMMU_S_GBPA, SMMU_S_GBPA_UPDATE, 0U);
70 }
71
72 /*
73 * Initialize the SMMU by invalidating all secure caches and TLBs.
74 * Abort all incoming transactions in order to implement a default
75 * deny policy on reset
76 */
smmuv3_init(uintptr_t smmu_base)77 int __init smmuv3_init(uintptr_t smmu_base)
78 {
79 /* Abort all incoming transactions */
80 if (smmuv3_security_init(smmu_base) != 0)
81 return -1;
82
83 #if ENABLE_RME
84
85 if (get_armv9_2_feat_rme_support() != 0U) {
86 if ((mmio_read_32(smmu_base + SMMU_ROOT_IDR0) &
87 SMMU_ROOT_IDR0_ROOT_IMPL) == 0U) {
88 WARN("Skip SMMU GPC configuration.\n");
89 } else {
90 uint64_t gpccr_el3 = read_gpccr_el3();
91 uint64_t gptbr_el3 = read_gptbr_el3();
92
93 /* SMMU_ROOT_GPT_BASE_CFG[16] is RES0. */
94 gpccr_el3 &= ~(1UL << 16);
95
96 /*
97 * TODO: SMMU_ROOT_GPT_BASE_CFG is 64b in the spec,
98 * but SMMU model only accepts 32b access.
99 */
100 mmio_write_32(smmu_base + SMMU_ROOT_GPT_BASE_CFG,
101 gpccr_el3);
102
103 /*
104 * pa_gpt_table_base[51:12] maps to GPTBR_EL3[39:0]
105 * whereas it maps to SMMU_ROOT_GPT_BASE[51:12]
106 * hence needs a 12 bit left shit.
107 */
108 mmio_write_64(smmu_base + SMMU_ROOT_GPT_BASE,
109 gptbr_el3 << 12);
110
111 /*
112 * ACCESSEN=1: SMMU- and client-originated accesses are
113 * not terminated by this mechanism.
114 * GPCEN=1: All clients and SMMU-originated accesses,
115 * except GPT-walks, are subject to GPC.
116 */
117 mmio_setbits_32(smmu_base + SMMU_ROOT_CR0,
118 SMMU_ROOT_CR0_GPCEN |
119 SMMU_ROOT_CR0_ACCESSEN);
120
121 /* Poll for ACCESSEN and GPCEN ack bits. */
122 if (smmuv3_poll(smmu_base + SMMU_ROOT_CR0ACK,
123 SMMU_ROOT_CR0_GPCEN |
124 SMMU_ROOT_CR0_ACCESSEN,
125 SMMU_ROOT_CR0_GPCEN |
126 SMMU_ROOT_CR0_ACCESSEN) != 0) {
127 WARN("Failed enabling SMMU GPC.\n");
128
129 /*
130 * Do not return in error, but fall back to
131 * invalidating all entries through the secure
132 * register file.
133 */
134 }
135 }
136 }
137
138 #endif /* ENABLE_RME */
139
140 /*
141 * Initiate invalidation of secure caches and TLBs if the SMMU
142 * supports secure state. If not, it's implementation defined
143 * as to how SMMU_S_INIT register is accessed.
144 * Arm SMMU Arch RME supplement, section 3.4: all SMMU registers
145 * specified to be accessible only in secure physical address space are
146 * additionally accessible in root physical address space in an SMMU
147 * with RME.
148 * Section 3.3: as GPT information is permitted to be cached in a TLB,
149 * the SMMU_S_INIT.INV_ALL mechanism also invalidates GPT information
150 * cached in TLBs.
151 */
152 mmio_write_32(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL);
153
154 /* Wait for global invalidation operation to finish */
155 return smmuv3_poll(smmu_base + SMMU_S_INIT,
156 SMMU_S_INIT_INV_ALL, 0U);
157 }
158
smmuv3_ns_set_abort_all(uintptr_t smmu_base)159 int smmuv3_ns_set_abort_all(uintptr_t smmu_base)
160 {
161 /* Attribute update has completed when SMMU_GBPA.Update bit is 0 */
162 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) {
163 return -1;
164 }
165
166 /*
167 * Set GBPA's ABORT bit. Other GBPA fields are presumably ignored then,
168 * so simply preserve their value.
169 */
170 mmio_setbits_32(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE | SMMU_GBPA_ABORT);
171 if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) {
172 return -1;
173 }
174
175 /* Disable the SMMU to engage the GBPA fields previously configured. */
176 mmio_clrbits_32(smmu_base + SMMU_CR0, SMMU_CR0_SMMUEN);
177 if (smmuv3_poll(smmu_base + SMMU_CR0ACK, SMMU_CR0_SMMUEN, 0U) != 0U) {
178 return -1;
179 }
180
181 return 0;
182 }
183