1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_smu.h"
30 #include "smu_internal.h"
31 #include "atom.h"
32 #include "arcturus_ppt.h"
33 #include "navi10_ppt.h"
34 #include "sienna_cichlid_ppt.h"
35 #include "renoir_ppt.h"
36 #include "vangogh_ppt.h"
37 #include "aldebaran_ppt.h"
38 #include "yellow_carp_ppt.h"
39 #include "cyan_skillfish_ppt.h"
40 #include "smu_v13_0_0_ppt.h"
41 #include "smu_v13_0_4_ppt.h"
42 #include "smu_v13_0_5_ppt.h"
43 #include "smu_v13_0_7_ppt.h"
44 #include "amd_pcie.h"
45
46 /*
47 * DO NOT use these for err/warn/info/debug messages.
48 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
49 * They are more MGPU friendly.
50 */
51 #undef pr_err
52 #undef pr_warn
53 #undef pr_info
54 #undef pr_debug
55
56 static const struct amd_pm_funcs swsmu_pm_funcs;
57 static int smu_force_smuclk_levels(struct smu_context *smu,
58 enum smu_clk_type clk_type,
59 uint32_t mask);
60 static int smu_handle_task(struct smu_context *smu,
61 enum amd_dpm_forced_level level,
62 enum amd_pp_task task_id);
63 static int smu_reset(struct smu_context *smu);
64 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
65 static int smu_set_fan_control_mode(void *handle, u32 value);
66 static int smu_set_power_limit(void *handle, uint32_t limit);
67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
70
smu_sys_get_pp_feature_mask(void * handle,char * buf)71 static int smu_sys_get_pp_feature_mask(void *handle,
72 char *buf)
73 {
74 struct smu_context *smu = handle;
75
76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
77 return -EOPNOTSUPP;
78
79 return smu_get_pp_feature_mask(smu, buf);
80 }
81
smu_sys_set_pp_feature_mask(void * handle,uint64_t new_mask)82 static int smu_sys_set_pp_feature_mask(void *handle,
83 uint64_t new_mask)
84 {
85 struct smu_context *smu = handle;
86
87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
88 return -EOPNOTSUPP;
89
90 return smu_set_pp_feature_mask(smu, new_mask);
91 }
92
smu_set_residency_gfxoff(struct smu_context * smu,bool value)93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
94 {
95 if (!smu->ppt_funcs->set_gfx_off_residency)
96 return -EINVAL;
97
98 return smu_set_gfx_off_residency(smu, value);
99 }
100
smu_get_residency_gfxoff(struct smu_context * smu,u32 * value)101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
102 {
103 if (!smu->ppt_funcs->get_gfx_off_residency)
104 return -EINVAL;
105
106 return smu_get_gfx_off_residency(smu, value);
107 }
108
smu_get_entrycount_gfxoff(struct smu_context * smu,u64 * value)109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
110 {
111 if (!smu->ppt_funcs->get_gfx_off_entrycount)
112 return -EINVAL;
113
114 return smu_get_gfx_off_entrycount(smu, value);
115 }
116
smu_get_status_gfxoff(struct smu_context * smu,uint32_t * value)117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
118 {
119 if (!smu->ppt_funcs->get_gfx_off_status)
120 return -EINVAL;
121
122 *value = smu_get_gfx_off_status(smu);
123
124 return 0;
125 }
126
smu_set_soft_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)127 int smu_set_soft_freq_range(struct smu_context *smu,
128 enum smu_clk_type clk_type,
129 uint32_t min,
130 uint32_t max)
131 {
132 int ret = 0;
133
134 if (smu->ppt_funcs->set_soft_freq_limited_range)
135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
136 clk_type,
137 min,
138 max);
139
140 return ret;
141 }
142
smu_get_dpm_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)143 int smu_get_dpm_freq_range(struct smu_context *smu,
144 enum smu_clk_type clk_type,
145 uint32_t *min,
146 uint32_t *max)
147 {
148 int ret = -ENOTSUPP;
149
150 if (!min && !max)
151 return -EINVAL;
152
153 if (smu->ppt_funcs->get_dpm_ultimate_freq)
154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
155 clk_type,
156 min,
157 max);
158
159 return ret;
160 }
161
smu_set_gfx_power_up_by_imu(struct smu_context * smu)162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
163 {
164 if (!smu->ppt_funcs || !smu->ppt_funcs->set_gfx_power_up_by_imu)
165 return -EOPNOTSUPP;
166
167 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
168 }
169
smu_get_mclk(void * handle,bool low)170 static u32 smu_get_mclk(void *handle, bool low)
171 {
172 struct smu_context *smu = handle;
173 uint32_t clk_freq;
174 int ret = 0;
175
176 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
177 low ? &clk_freq : NULL,
178 !low ? &clk_freq : NULL);
179 if (ret)
180 return 0;
181 return clk_freq * 100;
182 }
183
smu_get_sclk(void * handle,bool low)184 static u32 smu_get_sclk(void *handle, bool low)
185 {
186 struct smu_context *smu = handle;
187 uint32_t clk_freq;
188 int ret = 0;
189
190 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
191 low ? &clk_freq : NULL,
192 !low ? &clk_freq : NULL);
193 if (ret)
194 return 0;
195 return clk_freq * 100;
196 }
197
smu_dpm_set_vcn_enable(struct smu_context * smu,bool enable)198 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
199 bool enable)
200 {
201 struct smu_power_context *smu_power = &smu->smu_power;
202 struct smu_power_gate *power_gate = &smu_power->power_gate;
203 int ret = 0;
204
205 if (!smu->ppt_funcs->dpm_set_vcn_enable)
206 return 0;
207
208 if (atomic_read(&power_gate->vcn_gated) ^ enable)
209 return 0;
210
211 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
212 if (!ret)
213 atomic_set(&power_gate->vcn_gated, !enable);
214
215 return ret;
216 }
217
smu_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)218 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
219 bool enable)
220 {
221 struct smu_power_context *smu_power = &smu->smu_power;
222 struct smu_power_gate *power_gate = &smu_power->power_gate;
223 int ret = 0;
224
225 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
226 return 0;
227
228 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
229 return 0;
230
231 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
232 if (!ret)
233 atomic_set(&power_gate->jpeg_gated, !enable);
234
235 return ret;
236 }
237
238 /**
239 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
240 *
241 * @handle: smu_context pointer
242 * @block_type: the IP block to power gate/ungate
243 * @gate: to power gate if true, ungate otherwise
244 *
245 * This API uses no smu->mutex lock protection due to:
246 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
247 * This is guarded to be race condition free by the caller.
248 * 2. Or get called on user setting request of power_dpm_force_performance_level.
249 * Under this case, the smu->mutex lock protection is already enforced on
250 * the parent API smu_force_performance_level of the call path.
251 */
smu_dpm_set_power_gate(void * handle,uint32_t block_type,bool gate)252 static int smu_dpm_set_power_gate(void *handle,
253 uint32_t block_type,
254 bool gate)
255 {
256 struct smu_context *smu = handle;
257 int ret = 0;
258
259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
260 dev_WARN(smu->adev->dev,
261 "SMU uninitialized but power %s requested for %u!\n",
262 gate ? "gate" : "ungate", block_type);
263 return -EOPNOTSUPP;
264 }
265
266 switch (block_type) {
267 /*
268 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
269 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
270 */
271 case AMD_IP_BLOCK_TYPE_UVD:
272 case AMD_IP_BLOCK_TYPE_VCN:
273 ret = smu_dpm_set_vcn_enable(smu, !gate);
274 if (ret)
275 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
276 gate ? "gate" : "ungate");
277 break;
278 case AMD_IP_BLOCK_TYPE_GFX:
279 ret = smu_gfx_off_control(smu, gate);
280 if (ret)
281 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
282 gate ? "enable" : "disable");
283 break;
284 case AMD_IP_BLOCK_TYPE_SDMA:
285 ret = smu_powergate_sdma(smu, gate);
286 if (ret)
287 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
288 gate ? "gate" : "ungate");
289 break;
290 case AMD_IP_BLOCK_TYPE_JPEG:
291 ret = smu_dpm_set_jpeg_enable(smu, !gate);
292 if (ret)
293 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
294 gate ? "gate" : "ungate");
295 break;
296 default:
297 dev_err(smu->adev->dev, "Unsupported block type!\n");
298 return -EINVAL;
299 }
300
301 return ret;
302 }
303
304 /**
305 * smu_set_user_clk_dependencies - set user profile clock dependencies
306 *
307 * @smu: smu_context pointer
308 * @clk: enum smu_clk_type type
309 *
310 * Enable/Disable the clock dependency for the @clk type.
311 */
smu_set_user_clk_dependencies(struct smu_context * smu,enum smu_clk_type clk)312 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
313 {
314 if (smu->adev->in_suspend)
315 return;
316
317 if (clk == SMU_MCLK) {
318 smu->user_dpm_profile.clk_dependency = 0;
319 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
320 } else if (clk == SMU_FCLK) {
321 /* MCLK takes precedence over FCLK */
322 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
323 return;
324
325 smu->user_dpm_profile.clk_dependency = 0;
326 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
327 } else if (clk == SMU_SOCCLK) {
328 /* MCLK takes precedence over SOCCLK */
329 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
330 return;
331
332 smu->user_dpm_profile.clk_dependency = 0;
333 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
334 } else
335 /* Add clk dependencies here, if any */
336 return;
337 }
338
339 /**
340 * smu_restore_dpm_user_profile - reinstate user dpm profile
341 *
342 * @smu: smu_context pointer
343 *
344 * Restore the saved user power configurations include power limit,
345 * clock frequencies, fan control mode and fan speed.
346 */
smu_restore_dpm_user_profile(struct smu_context * smu)347 static void smu_restore_dpm_user_profile(struct smu_context *smu)
348 {
349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
350 int ret = 0;
351
352 if (!smu->adev->in_suspend)
353 return;
354
355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
356 return;
357
358 /* Enable restore flag */
359 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
360
361 /* set the user dpm power limit */
362 if (smu->user_dpm_profile.power_limit) {
363 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
364 if (ret)
365 dev_err(smu->adev->dev, "Failed to set power limit value\n");
366 }
367
368 /* set the user dpm clock configurations */
369 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
370 enum smu_clk_type clk_type;
371
372 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
373 /*
374 * Iterate over smu clk type and force the saved user clk
375 * configs, skip if clock dependency is enabled
376 */
377 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
378 smu->user_dpm_profile.clk_mask[clk_type]) {
379 ret = smu_force_smuclk_levels(smu, clk_type,
380 smu->user_dpm_profile.clk_mask[clk_type]);
381 if (ret)
382 dev_err(smu->adev->dev,
383 "Failed to set clock type = %d\n", clk_type);
384 }
385 }
386 }
387
388 /* set the user dpm fan configurations */
389 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
390 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
392 if (ret != -EOPNOTSUPP) {
393 smu->user_dpm_profile.fan_speed_pwm = 0;
394 smu->user_dpm_profile.fan_speed_rpm = 0;
395 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
396 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
397 }
398
399 if (smu->user_dpm_profile.fan_speed_pwm) {
400 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
401 if (ret != -EOPNOTSUPP)
402 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
403 }
404
405 if (smu->user_dpm_profile.fan_speed_rpm) {
406 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
407 if (ret != -EOPNOTSUPP)
408 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
409 }
410 }
411
412 /* Restore user customized OD settings */
413 if (smu->user_dpm_profile.user_od) {
414 if (smu->ppt_funcs->restore_user_od_settings) {
415 ret = smu->ppt_funcs->restore_user_od_settings(smu);
416 if (ret)
417 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
418 }
419 }
420
421 /* Disable restore flag */
422 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
423 }
424
smu_get_power_num_states(void * handle,struct pp_states_info * state_info)425 static int smu_get_power_num_states(void *handle,
426 struct pp_states_info *state_info)
427 {
428 if (!state_info)
429 return -EINVAL;
430
431 /* not support power state */
432 memset(state_info, 0, sizeof(struct pp_states_info));
433 state_info->nums = 1;
434 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
435
436 return 0;
437 }
438
is_support_sw_smu(struct amdgpu_device * adev)439 bool is_support_sw_smu(struct amdgpu_device *adev)
440 {
441 /* vega20 is 11.0.2, but it's supported via the powerplay code */
442 if (adev->asic_type == CHIP_VEGA20)
443 return false;
444
445 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
446 return true;
447
448 return false;
449 }
450
is_support_cclk_dpm(struct amdgpu_device * adev)451 bool is_support_cclk_dpm(struct amdgpu_device *adev)
452 {
453 struct smu_context *smu = adev->powerplay.pp_handle;
454
455 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
456 return false;
457
458 return true;
459 }
460
461
smu_sys_get_pp_table(void * handle,char ** table)462 static int smu_sys_get_pp_table(void *handle,
463 char **table)
464 {
465 struct smu_context *smu = handle;
466 struct smu_table_context *smu_table = &smu->smu_table;
467
468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
469 return -EOPNOTSUPP;
470
471 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
472 return -EINVAL;
473
474 if (smu_table->hardcode_pptable)
475 *table = smu_table->hardcode_pptable;
476 else
477 *table = smu_table->power_play_table;
478
479 return smu_table->power_play_table_size;
480 }
481
smu_sys_set_pp_table(void * handle,const char * buf,size_t size)482 static int smu_sys_set_pp_table(void *handle,
483 const char *buf,
484 size_t size)
485 {
486 struct smu_context *smu = handle;
487 struct smu_table_context *smu_table = &smu->smu_table;
488 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
489 int ret = 0;
490
491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
492 return -EOPNOTSUPP;
493
494 if (header->usStructureSize != size) {
495 dev_err(smu->adev->dev, "pp table size not matched !\n");
496 return -EIO;
497 }
498
499 if (!smu_table->hardcode_pptable) {
500 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
501 if (!smu_table->hardcode_pptable)
502 return -ENOMEM;
503 }
504
505 memcpy(smu_table->hardcode_pptable, buf, size);
506 smu_table->power_play_table = smu_table->hardcode_pptable;
507 smu_table->power_play_table_size = size;
508
509 /*
510 * Special hw_fini action(for Navi1x, the DPMs disablement will be
511 * skipped) may be needed for custom pptable uploading.
512 */
513 smu->uploading_custom_pp_table = true;
514
515 ret = smu_reset(smu);
516 if (ret)
517 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
518
519 smu->uploading_custom_pp_table = false;
520
521 return ret;
522 }
523
smu_get_driver_allowed_feature_mask(struct smu_context * smu)524 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
525 {
526 struct smu_feature *feature = &smu->smu_feature;
527 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
528 int ret = 0;
529
530 /*
531 * With SCPM enabled, the allowed featuremasks setting(via
532 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
533 * That means there is no way to let PMFW knows the settings below.
534 * Thus, we just assume all the features are allowed under
535 * such scenario.
536 */
537 if (smu->adev->scpm_enabled) {
538 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
539 return 0;
540 }
541
542 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
543
544 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
545 SMU_FEATURE_MAX/32);
546 if (ret)
547 return ret;
548
549 bitmap_or(feature->allowed, feature->allowed,
550 (unsigned long *)allowed_feature_mask,
551 feature->feature_num);
552
553 return ret;
554 }
555
smu_set_funcs(struct amdgpu_device * adev)556 static int smu_set_funcs(struct amdgpu_device *adev)
557 {
558 struct smu_context *smu = adev->powerplay.pp_handle;
559
560 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
561 smu->od_enabled = true;
562
563 switch (adev->ip_versions[MP1_HWIP][0]) {
564 case IP_VERSION(11, 0, 0):
565 case IP_VERSION(11, 0, 5):
566 case IP_VERSION(11, 0, 9):
567 navi10_set_ppt_funcs(smu);
568 break;
569 case IP_VERSION(11, 0, 7):
570 case IP_VERSION(11, 0, 11):
571 case IP_VERSION(11, 0, 12):
572 case IP_VERSION(11, 0, 13):
573 sienna_cichlid_set_ppt_funcs(smu);
574 break;
575 case IP_VERSION(12, 0, 0):
576 case IP_VERSION(12, 0, 1):
577 renoir_set_ppt_funcs(smu);
578 break;
579 case IP_VERSION(11, 5, 0):
580 vangogh_set_ppt_funcs(smu);
581 break;
582 case IP_VERSION(13, 0, 1):
583 case IP_VERSION(13, 0, 3):
584 case IP_VERSION(13, 0, 8):
585 yellow_carp_set_ppt_funcs(smu);
586 break;
587 case IP_VERSION(13, 0, 4):
588 case IP_VERSION(13, 0, 11):
589 smu_v13_0_4_set_ppt_funcs(smu);
590 break;
591 case IP_VERSION(13, 0, 5):
592 smu_v13_0_5_set_ppt_funcs(smu);
593 break;
594 case IP_VERSION(11, 0, 8):
595 cyan_skillfish_set_ppt_funcs(smu);
596 break;
597 case IP_VERSION(11, 0, 2):
598 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
599 arcturus_set_ppt_funcs(smu);
600 /* OD is not supported on Arcturus */
601 smu->od_enabled =false;
602 break;
603 case IP_VERSION(13, 0, 2):
604 aldebaran_set_ppt_funcs(smu);
605 /* Enable pp_od_clk_voltage node */
606 smu->od_enabled = true;
607 break;
608 case IP_VERSION(13, 0, 0):
609 case IP_VERSION(13, 0, 10):
610 smu_v13_0_0_set_ppt_funcs(smu);
611 break;
612 case IP_VERSION(13, 0, 7):
613 smu_v13_0_7_set_ppt_funcs(smu);
614 break;
615 default:
616 return -EINVAL;
617 }
618
619 return 0;
620 }
621
smu_early_init(void * handle)622 static int smu_early_init(void *handle)
623 {
624 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
625 struct smu_context *smu;
626 int r;
627
628 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
629 if (!smu)
630 return -ENOMEM;
631
632 smu->adev = adev;
633 smu->pm_enabled = !!amdgpu_dpm;
634 smu->is_apu = false;
635 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
636 smu->smu_baco.platform_support = false;
637 smu->user_dpm_profile.fan_mode = -1;
638
639 mutex_init(&smu->message_lock);
640
641 adev->powerplay.pp_handle = smu;
642 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
643
644 r = smu_set_funcs(adev);
645 if (r)
646 return r;
647 return smu_init_microcode(smu);
648 }
649
smu_set_default_dpm_table(struct smu_context * smu)650 static int smu_set_default_dpm_table(struct smu_context *smu)
651 {
652 struct smu_power_context *smu_power = &smu->smu_power;
653 struct smu_power_gate *power_gate = &smu_power->power_gate;
654 int vcn_gate, jpeg_gate;
655 int ret = 0;
656
657 if (!smu->ppt_funcs->set_default_dpm_table)
658 return 0;
659
660 vcn_gate = atomic_read(&power_gate->vcn_gated);
661 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
662
663 ret = smu_dpm_set_vcn_enable(smu, true);
664 if (ret)
665 return ret;
666
667 ret = smu_dpm_set_jpeg_enable(smu, true);
668 if (ret)
669 goto err_out;
670
671 ret = smu->ppt_funcs->set_default_dpm_table(smu);
672 if (ret)
673 dev_err(smu->adev->dev,
674 "Failed to setup default dpm clock tables!\n");
675
676 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
677 err_out:
678 smu_dpm_set_vcn_enable(smu, !vcn_gate);
679 return ret;
680 }
681
smu_apply_default_config_table_settings(struct smu_context * smu)682 static int smu_apply_default_config_table_settings(struct smu_context *smu)
683 {
684 struct amdgpu_device *adev = smu->adev;
685 int ret = 0;
686
687 ret = smu_get_default_config_table_settings(smu,
688 &adev->pm.config_table);
689 if (ret)
690 return ret;
691
692 return smu_set_config_table(smu, &adev->pm.config_table);
693 }
694
smu_late_init(void * handle)695 static int smu_late_init(void *handle)
696 {
697 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
698 struct smu_context *smu = adev->powerplay.pp_handle;
699 int ret = 0;
700
701 smu_set_fine_grain_gfx_freq_parameters(smu);
702
703 if (!smu->pm_enabled)
704 return 0;
705
706 ret = smu_post_init(smu);
707 if (ret) {
708 dev_err(adev->dev, "Failed to post smu init!\n");
709 return ret;
710 }
711
712 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
713 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
714 return 0;
715
716 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
717 ret = smu_set_default_od_settings(smu);
718 if (ret) {
719 dev_err(adev->dev, "Failed to setup default OD settings!\n");
720 return ret;
721 }
722 }
723
724 ret = smu_populate_umd_state_clk(smu);
725 if (ret) {
726 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
727 return ret;
728 }
729
730 ret = smu_get_asic_power_limits(smu,
731 &smu->current_power_limit,
732 &smu->default_power_limit,
733 &smu->max_power_limit);
734 if (ret) {
735 dev_err(adev->dev, "Failed to get asic power limits!\n");
736 return ret;
737 }
738
739 if (!amdgpu_sriov_vf(adev))
740 smu_get_unique_id(smu);
741
742 smu_get_fan_parameters(smu);
743
744 smu_handle_task(smu,
745 smu->smu_dpm.dpm_level,
746 AMD_PP_TASK_COMPLETE_INIT);
747
748 ret = smu_apply_default_config_table_settings(smu);
749 if (ret && (ret != -EOPNOTSUPP)) {
750 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
751 return ret;
752 }
753
754 smu_restore_dpm_user_profile(smu);
755
756 return 0;
757 }
758
smu_init_fb_allocations(struct smu_context * smu)759 static int smu_init_fb_allocations(struct smu_context *smu)
760 {
761 struct amdgpu_device *adev = smu->adev;
762 struct smu_table_context *smu_table = &smu->smu_table;
763 struct smu_table *tables = smu_table->tables;
764 struct smu_table *driver_table = &(smu_table->driver_table);
765 uint32_t max_table_size = 0;
766 int ret, i;
767
768 /* VRAM allocation for tool table */
769 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
770 ret = amdgpu_bo_create_kernel(adev,
771 tables[SMU_TABLE_PMSTATUSLOG].size,
772 tables[SMU_TABLE_PMSTATUSLOG].align,
773 tables[SMU_TABLE_PMSTATUSLOG].domain,
774 &tables[SMU_TABLE_PMSTATUSLOG].bo,
775 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
776 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
777 if (ret) {
778 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
779 return ret;
780 }
781 }
782
783 /* VRAM allocation for driver table */
784 for (i = 0; i < SMU_TABLE_COUNT; i++) {
785 if (tables[i].size == 0)
786 continue;
787
788 if (i == SMU_TABLE_PMSTATUSLOG)
789 continue;
790
791 if (max_table_size < tables[i].size)
792 max_table_size = tables[i].size;
793 }
794
795 driver_table->size = max_table_size;
796 driver_table->align = PAGE_SIZE;
797 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
798
799 ret = amdgpu_bo_create_kernel(adev,
800 driver_table->size,
801 driver_table->align,
802 driver_table->domain,
803 &driver_table->bo,
804 &driver_table->mc_address,
805 &driver_table->cpu_addr);
806 if (ret) {
807 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
808 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
809 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
810 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
811 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
812 }
813
814 return ret;
815 }
816
smu_fini_fb_allocations(struct smu_context * smu)817 static int smu_fini_fb_allocations(struct smu_context *smu)
818 {
819 struct smu_table_context *smu_table = &smu->smu_table;
820 struct smu_table *tables = smu_table->tables;
821 struct smu_table *driver_table = &(smu_table->driver_table);
822
823 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
824 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
825 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
826 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
827
828 amdgpu_bo_free_kernel(&driver_table->bo,
829 &driver_table->mc_address,
830 &driver_table->cpu_addr);
831
832 return 0;
833 }
834
835 /**
836 * smu_alloc_memory_pool - allocate memory pool in the system memory
837 *
838 * @smu: amdgpu_device pointer
839 *
840 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
841 * and DramLogSetDramAddr can notify it changed.
842 *
843 * Returns 0 on success, error on failure.
844 */
smu_alloc_memory_pool(struct smu_context * smu)845 static int smu_alloc_memory_pool(struct smu_context *smu)
846 {
847 struct amdgpu_device *adev = smu->adev;
848 struct smu_table_context *smu_table = &smu->smu_table;
849 struct smu_table *memory_pool = &smu_table->memory_pool;
850 uint64_t pool_size = smu->pool_size;
851 int ret = 0;
852
853 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
854 return ret;
855
856 memory_pool->size = pool_size;
857 memory_pool->align = PAGE_SIZE;
858 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
859
860 switch (pool_size) {
861 case SMU_MEMORY_POOL_SIZE_256_MB:
862 case SMU_MEMORY_POOL_SIZE_512_MB:
863 case SMU_MEMORY_POOL_SIZE_1_GB:
864 case SMU_MEMORY_POOL_SIZE_2_GB:
865 ret = amdgpu_bo_create_kernel(adev,
866 memory_pool->size,
867 memory_pool->align,
868 memory_pool->domain,
869 &memory_pool->bo,
870 &memory_pool->mc_address,
871 &memory_pool->cpu_addr);
872 if (ret)
873 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
874 break;
875 default:
876 break;
877 }
878
879 return ret;
880 }
881
smu_free_memory_pool(struct smu_context * smu)882 static int smu_free_memory_pool(struct smu_context *smu)
883 {
884 struct smu_table_context *smu_table = &smu->smu_table;
885 struct smu_table *memory_pool = &smu_table->memory_pool;
886
887 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
888 return 0;
889
890 amdgpu_bo_free_kernel(&memory_pool->bo,
891 &memory_pool->mc_address,
892 &memory_pool->cpu_addr);
893
894 memset(memory_pool, 0, sizeof(struct smu_table));
895
896 return 0;
897 }
898
smu_alloc_dummy_read_table(struct smu_context * smu)899 static int smu_alloc_dummy_read_table(struct smu_context *smu)
900 {
901 struct smu_table_context *smu_table = &smu->smu_table;
902 struct smu_table *dummy_read_1_table =
903 &smu_table->dummy_read_1_table;
904 struct amdgpu_device *adev = smu->adev;
905 int ret = 0;
906
907 if (!dummy_read_1_table->size)
908 return 0;
909
910 ret = amdgpu_bo_create_kernel(adev,
911 dummy_read_1_table->size,
912 dummy_read_1_table->align,
913 dummy_read_1_table->domain,
914 &dummy_read_1_table->bo,
915 &dummy_read_1_table->mc_address,
916 &dummy_read_1_table->cpu_addr);
917 if (ret)
918 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
919
920 return ret;
921 }
922
smu_free_dummy_read_table(struct smu_context * smu)923 static void smu_free_dummy_read_table(struct smu_context *smu)
924 {
925 struct smu_table_context *smu_table = &smu->smu_table;
926 struct smu_table *dummy_read_1_table =
927 &smu_table->dummy_read_1_table;
928
929
930 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
931 &dummy_read_1_table->mc_address,
932 &dummy_read_1_table->cpu_addr);
933
934 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
935 }
936
smu_smc_table_sw_init(struct smu_context * smu)937 static int smu_smc_table_sw_init(struct smu_context *smu)
938 {
939 int ret;
940
941 /**
942 * Create smu_table structure, and init smc tables such as
943 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
944 */
945 ret = smu_init_smc_tables(smu);
946 if (ret) {
947 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
948 return ret;
949 }
950
951 /**
952 * Create smu_power_context structure, and allocate smu_dpm_context and
953 * context size to fill the smu_power_context data.
954 */
955 ret = smu_init_power(smu);
956 if (ret) {
957 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
958 return ret;
959 }
960
961 /*
962 * allocate vram bos to store smc table contents.
963 */
964 ret = smu_init_fb_allocations(smu);
965 if (ret)
966 return ret;
967
968 ret = smu_alloc_memory_pool(smu);
969 if (ret)
970 return ret;
971
972 ret = smu_alloc_dummy_read_table(smu);
973 if (ret)
974 return ret;
975
976 ret = smu_i2c_init(smu);
977 if (ret)
978 return ret;
979
980 return 0;
981 }
982
smu_smc_table_sw_fini(struct smu_context * smu)983 static int smu_smc_table_sw_fini(struct smu_context *smu)
984 {
985 int ret;
986
987 smu_i2c_fini(smu);
988
989 smu_free_dummy_read_table(smu);
990
991 ret = smu_free_memory_pool(smu);
992 if (ret)
993 return ret;
994
995 ret = smu_fini_fb_allocations(smu);
996 if (ret)
997 return ret;
998
999 ret = smu_fini_power(smu);
1000 if (ret) {
1001 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1002 return ret;
1003 }
1004
1005 ret = smu_fini_smc_tables(smu);
1006 if (ret) {
1007 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1008 return ret;
1009 }
1010
1011 return 0;
1012 }
1013
smu_throttling_logging_work_fn(struct work_struct * work)1014 static void smu_throttling_logging_work_fn(struct work_struct *work)
1015 {
1016 struct smu_context *smu = container_of(work, struct smu_context,
1017 throttling_logging_work);
1018
1019 smu_log_thermal_throttling(smu);
1020 }
1021
smu_interrupt_work_fn(struct work_struct * work)1022 static void smu_interrupt_work_fn(struct work_struct *work)
1023 {
1024 struct smu_context *smu = container_of(work, struct smu_context,
1025 interrupt_work);
1026
1027 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1028 smu->ppt_funcs->interrupt_work(smu);
1029 }
1030
smu_sw_init(void * handle)1031 static int smu_sw_init(void *handle)
1032 {
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034 struct smu_context *smu = adev->powerplay.pp_handle;
1035 int ret;
1036
1037 smu->pool_size = adev->pm.smu_prv_buffer_size;
1038 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1039 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1040 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1041
1042 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1043 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1044 atomic64_set(&smu->throttle_int_counter, 0);
1045 smu->watermarks_bitmap = 0;
1046 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1047 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1048
1049 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1050 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1051
1052 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1053 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1054 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1055 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1056 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1057 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1058 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1059 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1060
1061 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1062 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1063 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1064 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1065 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1066 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1067 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1068 smu->display_config = &adev->pm.pm_display_cfg;
1069
1070 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1071 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1072
1073 ret = smu_smc_table_sw_init(smu);
1074 if (ret) {
1075 dev_err(adev->dev, "Failed to sw init smc table!\n");
1076 return ret;
1077 }
1078
1079 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1080 ret = smu_get_vbios_bootup_values(smu);
1081 if (ret) {
1082 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1083 return ret;
1084 }
1085
1086 ret = smu_init_pptable_microcode(smu);
1087 if (ret) {
1088 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1089 return ret;
1090 }
1091
1092 ret = smu_register_irq_handler(smu);
1093 if (ret) {
1094 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1095 return ret;
1096 }
1097
1098 /* If there is no way to query fan control mode, fan control is not supported */
1099 if (!smu->ppt_funcs->get_fan_control_mode)
1100 smu->adev->pm.no_fan = true;
1101
1102 return 0;
1103 }
1104
smu_sw_fini(void * handle)1105 static int smu_sw_fini(void *handle)
1106 {
1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1108 struct smu_context *smu = adev->powerplay.pp_handle;
1109 int ret;
1110
1111 ret = smu_smc_table_sw_fini(smu);
1112 if (ret) {
1113 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1114 return ret;
1115 }
1116
1117 smu_fini_microcode(smu);
1118
1119 return 0;
1120 }
1121
smu_get_thermal_temperature_range(struct smu_context * smu)1122 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1123 {
1124 struct amdgpu_device *adev = smu->adev;
1125 struct smu_temperature_range *range =
1126 &smu->thermal_range;
1127 int ret = 0;
1128
1129 if (!smu->ppt_funcs->get_thermal_temperature_range)
1130 return 0;
1131
1132 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1133 if (ret)
1134 return ret;
1135
1136 adev->pm.dpm.thermal.min_temp = range->min;
1137 adev->pm.dpm.thermal.max_temp = range->max;
1138 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1139 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1140 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1141 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1142 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1143 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1144 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1145
1146 return ret;
1147 }
1148
smu_smc_hw_setup(struct smu_context * smu)1149 static int smu_smc_hw_setup(struct smu_context *smu)
1150 {
1151 struct smu_feature *feature = &smu->smu_feature;
1152 struct amdgpu_device *adev = smu->adev;
1153 uint32_t pcie_gen = 0, pcie_width = 0;
1154 uint64_t features_supported;
1155 int ret = 0;
1156
1157 switch (adev->ip_versions[MP1_HWIP][0]) {
1158 case IP_VERSION(11, 0, 7):
1159 case IP_VERSION(11, 0, 11):
1160 case IP_VERSION(11, 5, 0):
1161 case IP_VERSION(11, 0, 12):
1162 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1163 dev_info(adev->dev, "dpm has been enabled\n");
1164 ret = smu_system_features_control(smu, true);
1165 if (ret)
1166 dev_err(adev->dev, "Failed system features control!\n");
1167 return ret;
1168 }
1169 break;
1170 default:
1171 break;
1172 }
1173
1174 ret = smu_init_display_count(smu, 0);
1175 if (ret) {
1176 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1177 return ret;
1178 }
1179
1180 ret = smu_set_driver_table_location(smu);
1181 if (ret) {
1182 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1183 return ret;
1184 }
1185
1186 /*
1187 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1188 */
1189 ret = smu_set_tool_table_location(smu);
1190 if (ret) {
1191 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1192 return ret;
1193 }
1194
1195 /*
1196 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1197 * pool location.
1198 */
1199 ret = smu_notify_memory_pool_location(smu);
1200 if (ret) {
1201 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1202 return ret;
1203 }
1204
1205 /*
1206 * It is assumed the pptable used before runpm is same as
1207 * the one used afterwards. Thus, we can reuse the stored
1208 * copy and do not need to resetup the pptable again.
1209 */
1210 if (!adev->in_runpm) {
1211 ret = smu_setup_pptable(smu);
1212 if (ret) {
1213 dev_err(adev->dev, "Failed to setup pptable!\n");
1214 return ret;
1215 }
1216 }
1217
1218 /* smu_dump_pptable(smu); */
1219
1220 /*
1221 * With SCPM enabled, PSP is responsible for the PPTable transferring
1222 * (to SMU). Driver involvement is not needed and permitted.
1223 */
1224 if (!adev->scpm_enabled) {
1225 /*
1226 * Copy pptable bo in the vram to smc with SMU MSGs such as
1227 * SetDriverDramAddr and TransferTableDram2Smu.
1228 */
1229 ret = smu_write_pptable(smu);
1230 if (ret) {
1231 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1232 return ret;
1233 }
1234 }
1235
1236 /* issue Run*Btc msg */
1237 ret = smu_run_btc(smu);
1238 if (ret)
1239 return ret;
1240
1241 /*
1242 * With SCPM enabled, these actions(and relevant messages) are
1243 * not needed and permitted.
1244 */
1245 if (!adev->scpm_enabled) {
1246 ret = smu_feature_set_allowed_mask(smu);
1247 if (ret) {
1248 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1249 return ret;
1250 }
1251 }
1252
1253 ret = smu_system_features_control(smu, true);
1254 if (ret) {
1255 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1256 return ret;
1257 }
1258
1259 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1260 if (ret) {
1261 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1262 return ret;
1263 }
1264 bitmap_copy(feature->supported,
1265 (unsigned long *)&features_supported,
1266 feature->feature_num);
1267
1268 if (!smu_is_dpm_running(smu))
1269 dev_info(adev->dev, "dpm has been disabled\n");
1270
1271 /*
1272 * Set initialized values (get from vbios) to dpm tables context such as
1273 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1274 * type of clks.
1275 */
1276 ret = smu_set_default_dpm_table(smu);
1277 if (ret) {
1278 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1279 return ret;
1280 }
1281
1282 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1283 pcie_gen = 3;
1284 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1285 pcie_gen = 2;
1286 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1287 pcie_gen = 1;
1288 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1289 pcie_gen = 0;
1290
1291 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1292 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1293 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1294 */
1295 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1296 pcie_width = 6;
1297 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1298 pcie_width = 5;
1299 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1300 pcie_width = 4;
1301 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1302 pcie_width = 3;
1303 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1304 pcie_width = 2;
1305 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1306 pcie_width = 1;
1307 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1308 if (ret) {
1309 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1310 return ret;
1311 }
1312
1313 ret = smu_get_thermal_temperature_range(smu);
1314 if (ret) {
1315 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1316 return ret;
1317 }
1318
1319 ret = smu_enable_thermal_alert(smu);
1320 if (ret) {
1321 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1322 return ret;
1323 }
1324
1325 ret = smu_notify_display_change(smu);
1326 if (ret) {
1327 dev_err(adev->dev, "Failed to notify display change!\n");
1328 return ret;
1329 }
1330
1331 /*
1332 * Set min deep sleep dce fclk with bootup value from vbios via
1333 * SetMinDeepSleepDcefclk MSG.
1334 */
1335 ret = smu_set_min_dcef_deep_sleep(smu,
1336 smu->smu_table.boot_values.dcefclk / 100);
1337
1338 return ret;
1339 }
1340
smu_start_smc_engine(struct smu_context * smu)1341 static int smu_start_smc_engine(struct smu_context *smu)
1342 {
1343 struct amdgpu_device *adev = smu->adev;
1344 int ret = 0;
1345
1346 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1347 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1348 if (smu->ppt_funcs->load_microcode) {
1349 ret = smu->ppt_funcs->load_microcode(smu);
1350 if (ret)
1351 return ret;
1352 }
1353 }
1354 }
1355
1356 if (smu->ppt_funcs->check_fw_status) {
1357 ret = smu->ppt_funcs->check_fw_status(smu);
1358 if (ret) {
1359 dev_err(adev->dev, "SMC is not ready\n");
1360 return ret;
1361 }
1362 }
1363
1364 /*
1365 * Send msg GetDriverIfVersion to check if the return value is equal
1366 * with DRIVER_IF_VERSION of smc header.
1367 */
1368 ret = smu_check_fw_version(smu);
1369 if (ret)
1370 return ret;
1371
1372 return ret;
1373 }
1374
smu_hw_init(void * handle)1375 static int smu_hw_init(void *handle)
1376 {
1377 int ret;
1378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1379 struct smu_context *smu = adev->powerplay.pp_handle;
1380
1381 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1382 smu->pm_enabled = false;
1383 return 0;
1384 }
1385
1386 ret = smu_start_smc_engine(smu);
1387 if (ret) {
1388 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1389 return ret;
1390 }
1391
1392 if (smu->is_apu) {
1393 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
1394 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1395 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
1396 if (ret) {
1397 dev_err(adev->dev, "Failed to Enable gfx imu!\n");
1398 return ret;
1399 }
1400 }
1401
1402 smu_dpm_set_vcn_enable(smu, true);
1403 smu_dpm_set_jpeg_enable(smu, true);
1404 smu_set_gfx_cgpg(smu, true);
1405 }
1406
1407 if (!smu->pm_enabled)
1408 return 0;
1409
1410 ret = smu_get_driver_allowed_feature_mask(smu);
1411 if (ret)
1412 return ret;
1413
1414 ret = smu_smc_hw_setup(smu);
1415 if (ret) {
1416 dev_err(adev->dev, "Failed to setup smc hw!\n");
1417 return ret;
1418 }
1419
1420 /*
1421 * Move maximum sustainable clock retrieving here considering
1422 * 1. It is not needed on resume(from S3).
1423 * 2. DAL settings come between .hw_init and .late_init of SMU.
1424 * And DAL needs to know the maximum sustainable clocks. Thus
1425 * it cannot be put in .late_init().
1426 */
1427 ret = smu_init_max_sustainable_clocks(smu);
1428 if (ret) {
1429 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1430 return ret;
1431 }
1432
1433 adev->pm.dpm_enabled = true;
1434
1435 dev_info(adev->dev, "SMU is initialized successfully!\n");
1436
1437 return 0;
1438 }
1439
smu_disable_dpms(struct smu_context * smu)1440 static int smu_disable_dpms(struct smu_context *smu)
1441 {
1442 struct amdgpu_device *adev = smu->adev;
1443 int ret = 0;
1444 bool use_baco = !smu->is_apu &&
1445 ((amdgpu_in_reset(adev) &&
1446 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1447 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1448
1449 /*
1450 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1451 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1452 */
1453 switch (adev->ip_versions[MP1_HWIP][0]) {
1454 case IP_VERSION(13, 0, 0):
1455 case IP_VERSION(13, 0, 7):
1456 case IP_VERSION(13, 0, 10):
1457 return 0;
1458 default:
1459 break;
1460 }
1461
1462 /*
1463 * For custom pptable uploading, skip the DPM features
1464 * disable process on Navi1x ASICs.
1465 * - As the gfx related features are under control of
1466 * RLC on those ASICs. RLC reinitialization will be
1467 * needed to reenable them. That will cost much more
1468 * efforts.
1469 *
1470 * - SMU firmware can handle the DPM reenablement
1471 * properly.
1472 */
1473 if (smu->uploading_custom_pp_table) {
1474 switch (adev->ip_versions[MP1_HWIP][0]) {
1475 case IP_VERSION(11, 0, 0):
1476 case IP_VERSION(11, 0, 5):
1477 case IP_VERSION(11, 0, 9):
1478 case IP_VERSION(11, 0, 7):
1479 case IP_VERSION(11, 0, 11):
1480 case IP_VERSION(11, 5, 0):
1481 case IP_VERSION(11, 0, 12):
1482 case IP_VERSION(11, 0, 13):
1483 return 0;
1484 default:
1485 break;
1486 }
1487 }
1488
1489 /*
1490 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1491 * on BACO in. Driver involvement is unnecessary.
1492 */
1493 if (use_baco) {
1494 switch (adev->ip_versions[MP1_HWIP][0]) {
1495 case IP_VERSION(11, 0, 7):
1496 case IP_VERSION(11, 0, 0):
1497 case IP_VERSION(11, 0, 5):
1498 case IP_VERSION(11, 0, 9):
1499 case IP_VERSION(13, 0, 7):
1500 return 0;
1501 default:
1502 break;
1503 }
1504 }
1505
1506 /*
1507 * For SMU 13.0.4/11, PMFW will handle the features disablement properly
1508 * for gpu reset case. Driver involvement is unnecessary.
1509 */
1510 if (amdgpu_in_reset(adev)) {
1511 switch (adev->ip_versions[MP1_HWIP][0]) {
1512 case IP_VERSION(13, 0, 4):
1513 case IP_VERSION(13, 0, 11):
1514 return 0;
1515 default:
1516 break;
1517 }
1518 }
1519
1520 /*
1521 * For gpu reset, runpm and hibernation through BACO,
1522 * BACO feature has to be kept enabled.
1523 */
1524 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1525 ret = smu_disable_all_features_with_exception(smu,
1526 SMU_FEATURE_BACO_BIT);
1527 if (ret)
1528 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1529 } else {
1530 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1531 if (!adev->scpm_enabled) {
1532 ret = smu_system_features_control(smu, false);
1533 if (ret)
1534 dev_err(adev->dev, "Failed to disable smu features.\n");
1535 }
1536 }
1537
1538 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1539 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
1540 adev->gfx.rlc.funcs->stop(adev);
1541
1542 return ret;
1543 }
1544
smu_smc_hw_cleanup(struct smu_context * smu)1545 static int smu_smc_hw_cleanup(struct smu_context *smu)
1546 {
1547 struct amdgpu_device *adev = smu->adev;
1548 int ret = 0;
1549
1550 cancel_work_sync(&smu->throttling_logging_work);
1551 cancel_work_sync(&smu->interrupt_work);
1552
1553 ret = smu_disable_thermal_alert(smu);
1554 if (ret) {
1555 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1556 return ret;
1557 }
1558
1559 ret = smu_disable_dpms(smu);
1560 if (ret) {
1561 dev_err(adev->dev, "Fail to disable dpm features!\n");
1562 return ret;
1563 }
1564
1565 return 0;
1566 }
1567
smu_hw_fini(void * handle)1568 static int smu_hw_fini(void *handle)
1569 {
1570 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1571 struct smu_context *smu = adev->powerplay.pp_handle;
1572
1573 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1574 return 0;
1575
1576 smu_dpm_set_vcn_enable(smu, false);
1577 smu_dpm_set_jpeg_enable(smu, false);
1578
1579 adev->vcn.cur_state = AMD_PG_STATE_GATE;
1580 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1581
1582 if (!smu->pm_enabled)
1583 return 0;
1584
1585 adev->pm.dpm_enabled = false;
1586
1587 return smu_smc_hw_cleanup(smu);
1588 }
1589
smu_late_fini(void * handle)1590 static void smu_late_fini(void *handle)
1591 {
1592 struct amdgpu_device *adev = handle;
1593 struct smu_context *smu = adev->powerplay.pp_handle;
1594
1595 kfree(smu);
1596 }
1597
smu_reset(struct smu_context * smu)1598 static int smu_reset(struct smu_context *smu)
1599 {
1600 struct amdgpu_device *adev = smu->adev;
1601 int ret;
1602
1603 ret = smu_hw_fini(adev);
1604 if (ret)
1605 return ret;
1606
1607 ret = smu_hw_init(adev);
1608 if (ret)
1609 return ret;
1610
1611 ret = smu_late_init(adev);
1612 if (ret)
1613 return ret;
1614
1615 return 0;
1616 }
1617
smu_suspend(void * handle)1618 static int smu_suspend(void *handle)
1619 {
1620 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1621 struct smu_context *smu = adev->powerplay.pp_handle;
1622 int ret;
1623 uint64_t count;
1624
1625 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1626 return 0;
1627
1628 if (!smu->pm_enabled)
1629 return 0;
1630
1631 adev->pm.dpm_enabled = false;
1632
1633 ret = smu_smc_hw_cleanup(smu);
1634 if (ret)
1635 return ret;
1636
1637 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1638
1639 smu_set_gfx_cgpg(smu, false);
1640
1641 /*
1642 * pwfw resets entrycount when device is suspended, so we save the
1643 * last value to be used when we resume to keep it consistent
1644 */
1645 ret = smu_get_entrycount_gfxoff(smu, &count);
1646 if (!ret)
1647 adev->gfx.gfx_off_entrycount = count;
1648
1649 return 0;
1650 }
1651
smu_resume(void * handle)1652 static int smu_resume(void *handle)
1653 {
1654 int ret;
1655 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1656 struct smu_context *smu = adev->powerplay.pp_handle;
1657
1658 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1659 return 0;
1660
1661 if (!smu->pm_enabled)
1662 return 0;
1663
1664 dev_info(adev->dev, "SMU is resuming...\n");
1665
1666 ret = smu_start_smc_engine(smu);
1667 if (ret) {
1668 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1669 return ret;
1670 }
1671
1672 ret = smu_smc_hw_setup(smu);
1673 if (ret) {
1674 dev_err(adev->dev, "Failed to setup smc hw!\n");
1675 return ret;
1676 }
1677
1678 smu_set_gfx_cgpg(smu, true);
1679
1680 smu->disable_uclk_switch = 0;
1681
1682 adev->pm.dpm_enabled = true;
1683
1684 dev_info(adev->dev, "SMU is resumed successfully!\n");
1685
1686 return 0;
1687 }
1688
smu_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)1689 static int smu_display_configuration_change(void *handle,
1690 const struct amd_pp_display_configuration *display_config)
1691 {
1692 struct smu_context *smu = handle;
1693 int index = 0;
1694 int num_of_active_display = 0;
1695
1696 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1697 return -EOPNOTSUPP;
1698
1699 if (!display_config)
1700 return -EINVAL;
1701
1702 smu_set_min_dcef_deep_sleep(smu,
1703 display_config->min_dcef_deep_sleep_set_clk / 100);
1704
1705 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1706 if (display_config->displays[index].controller_id != 0)
1707 num_of_active_display++;
1708 }
1709
1710 return 0;
1711 }
1712
smu_set_clockgating_state(void * handle,enum amd_clockgating_state state)1713 static int smu_set_clockgating_state(void *handle,
1714 enum amd_clockgating_state state)
1715 {
1716 return 0;
1717 }
1718
smu_set_powergating_state(void * handle,enum amd_powergating_state state)1719 static int smu_set_powergating_state(void *handle,
1720 enum amd_powergating_state state)
1721 {
1722 return 0;
1723 }
1724
smu_enable_umd_pstate(void * handle,enum amd_dpm_forced_level * level)1725 static int smu_enable_umd_pstate(void *handle,
1726 enum amd_dpm_forced_level *level)
1727 {
1728 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1729 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1730 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1731 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1732
1733 struct smu_context *smu = (struct smu_context*)(handle);
1734 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1735
1736 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1737 return -EINVAL;
1738
1739 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1740 /* enter umd pstate, save current level, disable gfx cg*/
1741 if (*level & profile_mode_mask) {
1742 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1743 smu_gpo_control(smu, false);
1744 smu_gfx_ulv_control(smu, false);
1745 smu_deep_sleep_control(smu, false);
1746 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1747 }
1748 } else {
1749 /* exit umd pstate, restore level, enable gfx cg*/
1750 if (!(*level & profile_mode_mask)) {
1751 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1752 *level = smu_dpm_ctx->saved_dpm_level;
1753 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1754 smu_deep_sleep_control(smu, true);
1755 smu_gfx_ulv_control(smu, true);
1756 smu_gpo_control(smu, true);
1757 }
1758 }
1759
1760 return 0;
1761 }
1762
smu_bump_power_profile_mode(struct smu_context * smu,long * param,uint32_t param_size)1763 static int smu_bump_power_profile_mode(struct smu_context *smu,
1764 long *param,
1765 uint32_t param_size)
1766 {
1767 int ret = 0;
1768
1769 if (smu->ppt_funcs->set_power_profile_mode)
1770 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1771
1772 return ret;
1773 }
1774
smu_adjust_power_state_dynamic(struct smu_context * smu,enum amd_dpm_forced_level level,bool skip_display_settings)1775 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1776 enum amd_dpm_forced_level level,
1777 bool skip_display_settings)
1778 {
1779 int ret = 0;
1780 int index = 0;
1781 long workload;
1782 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1783
1784 if (!skip_display_settings) {
1785 ret = smu_display_config_changed(smu);
1786 if (ret) {
1787 dev_err(smu->adev->dev, "Failed to change display config!");
1788 return ret;
1789 }
1790 }
1791
1792 ret = smu_apply_clocks_adjust_rules(smu);
1793 if (ret) {
1794 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1795 return ret;
1796 }
1797
1798 if (!skip_display_settings) {
1799 ret = smu_notify_smc_display_config(smu);
1800 if (ret) {
1801 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1802 return ret;
1803 }
1804 }
1805
1806 if (smu_dpm_ctx->dpm_level != level) {
1807 ret = smu_asic_set_performance_level(smu, level);
1808 if (ret) {
1809 dev_err(smu->adev->dev, "Failed to set performance level!");
1810 return ret;
1811 }
1812
1813 /* update the saved copy */
1814 smu_dpm_ctx->dpm_level = level;
1815 }
1816
1817 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1818 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1819 index = fls(smu->workload_mask);
1820 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1821 workload = smu->workload_setting[index];
1822
1823 if (smu->power_profile_mode != workload)
1824 smu_bump_power_profile_mode(smu, &workload, 0);
1825 }
1826
1827 return ret;
1828 }
1829
smu_handle_task(struct smu_context * smu,enum amd_dpm_forced_level level,enum amd_pp_task task_id)1830 static int smu_handle_task(struct smu_context *smu,
1831 enum amd_dpm_forced_level level,
1832 enum amd_pp_task task_id)
1833 {
1834 int ret = 0;
1835
1836 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1837 return -EOPNOTSUPP;
1838
1839 switch (task_id) {
1840 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1841 ret = smu_pre_display_config_changed(smu);
1842 if (ret)
1843 return ret;
1844 ret = smu_adjust_power_state_dynamic(smu, level, false);
1845 break;
1846 case AMD_PP_TASK_COMPLETE_INIT:
1847 case AMD_PP_TASK_READJUST_POWER_STATE:
1848 ret = smu_adjust_power_state_dynamic(smu, level, true);
1849 break;
1850 default:
1851 break;
1852 }
1853
1854 return ret;
1855 }
1856
smu_handle_dpm_task(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)1857 static int smu_handle_dpm_task(void *handle,
1858 enum amd_pp_task task_id,
1859 enum amd_pm_state_type *user_state)
1860 {
1861 struct smu_context *smu = handle;
1862 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1863
1864 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
1865
1866 }
1867
smu_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool en)1868 static int smu_switch_power_profile(void *handle,
1869 enum PP_SMC_POWER_PROFILE type,
1870 bool en)
1871 {
1872 struct smu_context *smu = handle;
1873 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1874 long workload;
1875 uint32_t index;
1876
1877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1878 return -EOPNOTSUPP;
1879
1880 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1881 return -EINVAL;
1882
1883 if (!en) {
1884 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1885 index = fls(smu->workload_mask);
1886 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1887 workload = smu->workload_setting[index];
1888 } else {
1889 smu->workload_mask |= (1 << smu->workload_prority[type]);
1890 index = fls(smu->workload_mask);
1891 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1892 workload = smu->workload_setting[index];
1893 }
1894
1895 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1896 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1897 smu_bump_power_profile_mode(smu, &workload, 0);
1898
1899 return 0;
1900 }
1901
smu_get_performance_level(void * handle)1902 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1903 {
1904 struct smu_context *smu = handle;
1905 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1906
1907 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1908 return -EOPNOTSUPP;
1909
1910 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1911 return -EINVAL;
1912
1913 return smu_dpm_ctx->dpm_level;
1914 }
1915
smu_force_performance_level(void * handle,enum amd_dpm_forced_level level)1916 static int smu_force_performance_level(void *handle,
1917 enum amd_dpm_forced_level level)
1918 {
1919 struct smu_context *smu = handle;
1920 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1921 int ret = 0;
1922
1923 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1924 return -EOPNOTSUPP;
1925
1926 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1927 return -EINVAL;
1928
1929 ret = smu_enable_umd_pstate(smu, &level);
1930 if (ret)
1931 return ret;
1932
1933 ret = smu_handle_task(smu, level,
1934 AMD_PP_TASK_READJUST_POWER_STATE);
1935
1936 /* reset user dpm clock state */
1937 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1938 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1939 smu->user_dpm_profile.clk_dependency = 0;
1940 }
1941
1942 return ret;
1943 }
1944
smu_set_display_count(void * handle,uint32_t count)1945 static int smu_set_display_count(void *handle, uint32_t count)
1946 {
1947 struct smu_context *smu = handle;
1948
1949 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1950 return -EOPNOTSUPP;
1951
1952 return smu_init_display_count(smu, count);
1953 }
1954
smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1955 static int smu_force_smuclk_levels(struct smu_context *smu,
1956 enum smu_clk_type clk_type,
1957 uint32_t mask)
1958 {
1959 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1960 int ret = 0;
1961
1962 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1963 return -EOPNOTSUPP;
1964
1965 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1966 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1967 return -EINVAL;
1968 }
1969
1970 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1971 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1972 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1973 smu->user_dpm_profile.clk_mask[clk_type] = mask;
1974 smu_set_user_clk_dependencies(smu, clk_type);
1975 }
1976 }
1977
1978 return ret;
1979 }
1980
smu_force_ppclk_levels(void * handle,enum pp_clock_type type,uint32_t mask)1981 static int smu_force_ppclk_levels(void *handle,
1982 enum pp_clock_type type,
1983 uint32_t mask)
1984 {
1985 struct smu_context *smu = handle;
1986 enum smu_clk_type clk_type;
1987
1988 switch (type) {
1989 case PP_SCLK:
1990 clk_type = SMU_SCLK; break;
1991 case PP_MCLK:
1992 clk_type = SMU_MCLK; break;
1993 case PP_PCIE:
1994 clk_type = SMU_PCIE; break;
1995 case PP_SOCCLK:
1996 clk_type = SMU_SOCCLK; break;
1997 case PP_FCLK:
1998 clk_type = SMU_FCLK; break;
1999 case PP_DCEFCLK:
2000 clk_type = SMU_DCEFCLK; break;
2001 case PP_VCLK:
2002 clk_type = SMU_VCLK; break;
2003 case PP_DCLK:
2004 clk_type = SMU_DCLK; break;
2005 case OD_SCLK:
2006 clk_type = SMU_OD_SCLK; break;
2007 case OD_MCLK:
2008 clk_type = SMU_OD_MCLK; break;
2009 case OD_VDDC_CURVE:
2010 clk_type = SMU_OD_VDDC_CURVE; break;
2011 case OD_RANGE:
2012 clk_type = SMU_OD_RANGE; break;
2013 default:
2014 return -EINVAL;
2015 }
2016
2017 return smu_force_smuclk_levels(smu, clk_type, mask);
2018 }
2019
2020 /*
2021 * On system suspending or resetting, the dpm_enabled
2022 * flag will be cleared. So that those SMU services which
2023 * are not supported will be gated.
2024 * However, the mp1 state setting should still be granted
2025 * even if the dpm_enabled cleared.
2026 */
smu_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)2027 static int smu_set_mp1_state(void *handle,
2028 enum pp_mp1_state mp1_state)
2029 {
2030 struct smu_context *smu = handle;
2031 int ret = 0;
2032
2033 if (!smu->pm_enabled)
2034 return -EOPNOTSUPP;
2035
2036 if (smu->ppt_funcs &&
2037 smu->ppt_funcs->set_mp1_state)
2038 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2039
2040 return ret;
2041 }
2042
smu_set_df_cstate(void * handle,enum pp_df_cstate state)2043 static int smu_set_df_cstate(void *handle,
2044 enum pp_df_cstate state)
2045 {
2046 struct smu_context *smu = handle;
2047 int ret = 0;
2048
2049 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2050 return -EOPNOTSUPP;
2051
2052 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2053 return 0;
2054
2055 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2056 if (ret)
2057 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2058
2059 return ret;
2060 }
2061
smu_allow_xgmi_power_down(struct smu_context * smu,bool en)2062 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2063 {
2064 int ret = 0;
2065
2066 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2067 return -EOPNOTSUPP;
2068
2069 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2070 return 0;
2071
2072 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2073 if (ret)
2074 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2075
2076 return ret;
2077 }
2078
smu_write_watermarks_table(struct smu_context * smu)2079 int smu_write_watermarks_table(struct smu_context *smu)
2080 {
2081 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2082 return -EOPNOTSUPP;
2083
2084 return smu_set_watermarks_table(smu, NULL);
2085 }
2086
smu_set_watermarks_for_clock_ranges(void * handle,struct pp_smu_wm_range_sets * clock_ranges)2087 static int smu_set_watermarks_for_clock_ranges(void *handle,
2088 struct pp_smu_wm_range_sets *clock_ranges)
2089 {
2090 struct smu_context *smu = handle;
2091
2092 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2093 return -EOPNOTSUPP;
2094
2095 if (smu->disable_watermark)
2096 return 0;
2097
2098 return smu_set_watermarks_table(smu, clock_ranges);
2099 }
2100
smu_set_ac_dc(struct smu_context * smu)2101 int smu_set_ac_dc(struct smu_context *smu)
2102 {
2103 int ret = 0;
2104
2105 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2106 return -EOPNOTSUPP;
2107
2108 /* controlled by firmware */
2109 if (smu->dc_controlled_by_gpio)
2110 return 0;
2111
2112 ret = smu_set_power_source(smu,
2113 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2114 SMU_POWER_SOURCE_DC);
2115 if (ret)
2116 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2117 smu->adev->pm.ac_power ? "AC" : "DC");
2118
2119 return ret;
2120 }
2121
2122 const struct amd_ip_funcs smu_ip_funcs = {
2123 .name = "smu",
2124 .early_init = smu_early_init,
2125 .late_init = smu_late_init,
2126 .sw_init = smu_sw_init,
2127 .sw_fini = smu_sw_fini,
2128 .hw_init = smu_hw_init,
2129 .hw_fini = smu_hw_fini,
2130 .late_fini = smu_late_fini,
2131 .suspend = smu_suspend,
2132 .resume = smu_resume,
2133 .is_idle = NULL,
2134 .check_soft_reset = NULL,
2135 .wait_for_idle = NULL,
2136 .soft_reset = NULL,
2137 .set_clockgating_state = smu_set_clockgating_state,
2138 .set_powergating_state = smu_set_powergating_state,
2139 };
2140
2141 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2142 {
2143 .type = AMD_IP_BLOCK_TYPE_SMC,
2144 .major = 11,
2145 .minor = 0,
2146 .rev = 0,
2147 .funcs = &smu_ip_funcs,
2148 };
2149
2150 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2151 {
2152 .type = AMD_IP_BLOCK_TYPE_SMC,
2153 .major = 12,
2154 .minor = 0,
2155 .rev = 0,
2156 .funcs = &smu_ip_funcs,
2157 };
2158
2159 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2160 {
2161 .type = AMD_IP_BLOCK_TYPE_SMC,
2162 .major = 13,
2163 .minor = 0,
2164 .rev = 0,
2165 .funcs = &smu_ip_funcs,
2166 };
2167
smu_load_microcode(void * handle)2168 static int smu_load_microcode(void *handle)
2169 {
2170 struct smu_context *smu = handle;
2171 struct amdgpu_device *adev = smu->adev;
2172 int ret = 0;
2173
2174 if (!smu->pm_enabled)
2175 return -EOPNOTSUPP;
2176
2177 /* This should be used for non PSP loading */
2178 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2179 return 0;
2180
2181 if (smu->ppt_funcs->load_microcode) {
2182 ret = smu->ppt_funcs->load_microcode(smu);
2183 if (ret) {
2184 dev_err(adev->dev, "Load microcode failed\n");
2185 return ret;
2186 }
2187 }
2188
2189 if (smu->ppt_funcs->check_fw_status) {
2190 ret = smu->ppt_funcs->check_fw_status(smu);
2191 if (ret) {
2192 dev_err(adev->dev, "SMC is not ready\n");
2193 return ret;
2194 }
2195 }
2196
2197 return ret;
2198 }
2199
smu_set_gfx_cgpg(struct smu_context * smu,bool enabled)2200 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2201 {
2202 int ret = 0;
2203
2204 if (smu->ppt_funcs->set_gfx_cgpg)
2205 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2206
2207 return ret;
2208 }
2209
smu_set_fan_speed_rpm(void * handle,uint32_t speed)2210 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2211 {
2212 struct smu_context *smu = handle;
2213 int ret = 0;
2214
2215 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2216 return -EOPNOTSUPP;
2217
2218 if (!smu->ppt_funcs->set_fan_speed_rpm)
2219 return -EOPNOTSUPP;
2220
2221 if (speed == U32_MAX)
2222 return -EINVAL;
2223
2224 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2225 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2226 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2227 smu->user_dpm_profile.fan_speed_rpm = speed;
2228
2229 /* Override custom PWM setting as they cannot co-exist */
2230 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2231 smu->user_dpm_profile.fan_speed_pwm = 0;
2232 }
2233
2234 return ret;
2235 }
2236
2237 /**
2238 * smu_get_power_limit - Request one of the SMU Power Limits
2239 *
2240 * @handle: pointer to smu context
2241 * @limit: requested limit is written back to this variable
2242 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2243 * @pp_power_type: &pp_power_type type of power
2244 * Return: 0 on success, <0 on error
2245 *
2246 */
smu_get_power_limit(void * handle,uint32_t * limit,enum pp_power_limit_level pp_limit_level,enum pp_power_type pp_power_type)2247 int smu_get_power_limit(void *handle,
2248 uint32_t *limit,
2249 enum pp_power_limit_level pp_limit_level,
2250 enum pp_power_type pp_power_type)
2251 {
2252 struct smu_context *smu = handle;
2253 struct amdgpu_device *adev = smu->adev;
2254 enum smu_ppt_limit_level limit_level;
2255 uint32_t limit_type;
2256 int ret = 0;
2257
2258 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2259 return -EOPNOTSUPP;
2260
2261 switch(pp_power_type) {
2262 case PP_PWR_TYPE_SUSTAINED:
2263 limit_type = SMU_DEFAULT_PPT_LIMIT;
2264 break;
2265 case PP_PWR_TYPE_FAST:
2266 limit_type = SMU_FAST_PPT_LIMIT;
2267 break;
2268 default:
2269 return -EOPNOTSUPP;
2270 break;
2271 }
2272
2273 switch(pp_limit_level){
2274 case PP_PWR_LIMIT_CURRENT:
2275 limit_level = SMU_PPT_LIMIT_CURRENT;
2276 break;
2277 case PP_PWR_LIMIT_DEFAULT:
2278 limit_level = SMU_PPT_LIMIT_DEFAULT;
2279 break;
2280 case PP_PWR_LIMIT_MAX:
2281 limit_level = SMU_PPT_LIMIT_MAX;
2282 break;
2283 case PP_PWR_LIMIT_MIN:
2284 default:
2285 return -EOPNOTSUPP;
2286 break;
2287 }
2288
2289 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2290 if (smu->ppt_funcs->get_ppt_limit)
2291 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2292 } else {
2293 switch (limit_level) {
2294 case SMU_PPT_LIMIT_CURRENT:
2295 switch (adev->ip_versions[MP1_HWIP][0]) {
2296 case IP_VERSION(13, 0, 2):
2297 case IP_VERSION(11, 0, 7):
2298 case IP_VERSION(11, 0, 11):
2299 case IP_VERSION(11, 0, 12):
2300 case IP_VERSION(11, 0, 13):
2301 ret = smu_get_asic_power_limits(smu,
2302 &smu->current_power_limit,
2303 NULL,
2304 NULL);
2305 break;
2306 default:
2307 break;
2308 }
2309 *limit = smu->current_power_limit;
2310 break;
2311 case SMU_PPT_LIMIT_DEFAULT:
2312 *limit = smu->default_power_limit;
2313 break;
2314 case SMU_PPT_LIMIT_MAX:
2315 *limit = smu->max_power_limit;
2316 break;
2317 default:
2318 break;
2319 }
2320 }
2321
2322 return ret;
2323 }
2324
smu_set_power_limit(void * handle,uint32_t limit)2325 static int smu_set_power_limit(void *handle, uint32_t limit)
2326 {
2327 struct smu_context *smu = handle;
2328 uint32_t limit_type = limit >> 24;
2329 int ret = 0;
2330
2331 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2332 return -EOPNOTSUPP;
2333
2334 limit &= (1<<24)-1;
2335 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2336 if (smu->ppt_funcs->set_power_limit)
2337 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2338
2339 if (limit > smu->max_power_limit) {
2340 dev_err(smu->adev->dev,
2341 "New power limit (%d) is over the max allowed %d\n",
2342 limit, smu->max_power_limit);
2343 return -EINVAL;
2344 }
2345
2346 if (!limit)
2347 limit = smu->current_power_limit;
2348
2349 if (smu->ppt_funcs->set_power_limit) {
2350 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2351 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2352 smu->user_dpm_profile.power_limit = limit;
2353 }
2354
2355 return ret;
2356 }
2357
smu_print_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)2358 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2359 {
2360 int ret = 0;
2361
2362 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2363 return -EOPNOTSUPP;
2364
2365 if (smu->ppt_funcs->print_clk_levels)
2366 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2367
2368 return ret;
2369 }
2370
smu_convert_to_smuclk(enum pp_clock_type type)2371 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2372 {
2373 enum smu_clk_type clk_type;
2374
2375 switch (type) {
2376 case PP_SCLK:
2377 clk_type = SMU_SCLK; break;
2378 case PP_MCLK:
2379 clk_type = SMU_MCLK; break;
2380 case PP_PCIE:
2381 clk_type = SMU_PCIE; break;
2382 case PP_SOCCLK:
2383 clk_type = SMU_SOCCLK; break;
2384 case PP_FCLK:
2385 clk_type = SMU_FCLK; break;
2386 case PP_DCEFCLK:
2387 clk_type = SMU_DCEFCLK; break;
2388 case PP_VCLK:
2389 clk_type = SMU_VCLK; break;
2390 case PP_DCLK:
2391 clk_type = SMU_DCLK; break;
2392 case OD_SCLK:
2393 clk_type = SMU_OD_SCLK; break;
2394 case OD_MCLK:
2395 clk_type = SMU_OD_MCLK; break;
2396 case OD_VDDC_CURVE:
2397 clk_type = SMU_OD_VDDC_CURVE; break;
2398 case OD_RANGE:
2399 clk_type = SMU_OD_RANGE; break;
2400 case OD_VDDGFX_OFFSET:
2401 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2402 case OD_CCLK:
2403 clk_type = SMU_OD_CCLK; break;
2404 default:
2405 clk_type = SMU_CLK_COUNT; break;
2406 }
2407
2408 return clk_type;
2409 }
2410
smu_print_ppclk_levels(void * handle,enum pp_clock_type type,char * buf)2411 static int smu_print_ppclk_levels(void *handle,
2412 enum pp_clock_type type,
2413 char *buf)
2414 {
2415 struct smu_context *smu = handle;
2416 enum smu_clk_type clk_type;
2417
2418 clk_type = smu_convert_to_smuclk(type);
2419 if (clk_type == SMU_CLK_COUNT)
2420 return -EINVAL;
2421
2422 return smu_print_smuclk_levels(smu, clk_type, buf);
2423 }
2424
smu_emit_ppclk_levels(void * handle,enum pp_clock_type type,char * buf,int * offset)2425 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2426 {
2427 struct smu_context *smu = handle;
2428 enum smu_clk_type clk_type;
2429
2430 clk_type = smu_convert_to_smuclk(type);
2431 if (clk_type == SMU_CLK_COUNT)
2432 return -EINVAL;
2433
2434 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2435 return -EOPNOTSUPP;
2436
2437 if (!smu->ppt_funcs->emit_clk_levels)
2438 return -ENOENT;
2439
2440 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2441
2442 }
2443
smu_od_edit_dpm_table(void * handle,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)2444 static int smu_od_edit_dpm_table(void *handle,
2445 enum PP_OD_DPM_TABLE_COMMAND type,
2446 long *input, uint32_t size)
2447 {
2448 struct smu_context *smu = handle;
2449 int ret = 0;
2450
2451 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2452 return -EOPNOTSUPP;
2453
2454 if (smu->ppt_funcs->od_edit_dpm_table) {
2455 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2456 }
2457
2458 return ret;
2459 }
2460
smu_read_sensor(void * handle,int sensor,void * data,int * size_arg)2461 static int smu_read_sensor(void *handle,
2462 int sensor,
2463 void *data,
2464 int *size_arg)
2465 {
2466 struct smu_context *smu = handle;
2467 struct smu_umd_pstate_table *pstate_table =
2468 &smu->pstate_table;
2469 int ret = 0;
2470 uint32_t *size, size_val;
2471
2472 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2473 return -EOPNOTSUPP;
2474
2475 if (!data || !size_arg)
2476 return -EINVAL;
2477
2478 size_val = *size_arg;
2479 size = &size_val;
2480
2481 if (smu->ppt_funcs->read_sensor)
2482 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2483 goto unlock;
2484
2485 switch (sensor) {
2486 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2487 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2488 *size = 4;
2489 break;
2490 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2491 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2492 *size = 4;
2493 break;
2494 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
2495 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;
2496 *size = 4;
2497 break;
2498 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
2499 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
2500 *size = 4;
2501 break;
2502 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2503 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2504 *size = 8;
2505 break;
2506 case AMDGPU_PP_SENSOR_UVD_POWER:
2507 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2508 *size = 4;
2509 break;
2510 case AMDGPU_PP_SENSOR_VCE_POWER:
2511 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2512 *size = 4;
2513 break;
2514 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2515 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2516 *size = 4;
2517 break;
2518 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2519 *(uint32_t *)data = 0;
2520 *size = 4;
2521 break;
2522 default:
2523 *size = 0;
2524 ret = -EOPNOTSUPP;
2525 break;
2526 }
2527
2528 unlock:
2529 // assign uint32_t to int
2530 *size_arg = size_val;
2531
2532 return ret;
2533 }
2534
smu_get_power_profile_mode(void * handle,char * buf)2535 static int smu_get_power_profile_mode(void *handle, char *buf)
2536 {
2537 struct smu_context *smu = handle;
2538
2539 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2540 !smu->ppt_funcs->get_power_profile_mode)
2541 return -EOPNOTSUPP;
2542 if (!buf)
2543 return -EINVAL;
2544
2545 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
2546 }
2547
smu_set_power_profile_mode(void * handle,long * param,uint32_t param_size)2548 static int smu_set_power_profile_mode(void *handle,
2549 long *param,
2550 uint32_t param_size)
2551 {
2552 struct smu_context *smu = handle;
2553
2554 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2555 !smu->ppt_funcs->set_power_profile_mode)
2556 return -EOPNOTSUPP;
2557
2558 return smu_bump_power_profile_mode(smu, param, param_size);
2559 }
2560
smu_get_fan_control_mode(void * handle,u32 * fan_mode)2561 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
2562 {
2563 struct smu_context *smu = handle;
2564
2565 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2566 return -EOPNOTSUPP;
2567
2568 if (!smu->ppt_funcs->get_fan_control_mode)
2569 return -EOPNOTSUPP;
2570
2571 if (!fan_mode)
2572 return -EINVAL;
2573
2574 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
2575
2576 return 0;
2577 }
2578
smu_set_fan_control_mode(void * handle,u32 value)2579 static int smu_set_fan_control_mode(void *handle, u32 value)
2580 {
2581 struct smu_context *smu = handle;
2582 int ret = 0;
2583
2584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2585 return -EOPNOTSUPP;
2586
2587 if (!smu->ppt_funcs->set_fan_control_mode)
2588 return -EOPNOTSUPP;
2589
2590 if (value == U32_MAX)
2591 return -EINVAL;
2592
2593 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2594 if (ret)
2595 goto out;
2596
2597 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2598 smu->user_dpm_profile.fan_mode = value;
2599
2600 /* reset user dpm fan speed */
2601 if (value != AMD_FAN_CTRL_MANUAL) {
2602 smu->user_dpm_profile.fan_speed_pwm = 0;
2603 smu->user_dpm_profile.fan_speed_rpm = 0;
2604 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2605 }
2606 }
2607
2608 out:
2609 return ret;
2610 }
2611
smu_get_fan_speed_pwm(void * handle,u32 * speed)2612 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2613 {
2614 struct smu_context *smu = handle;
2615 int ret = 0;
2616
2617 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2618 return -EOPNOTSUPP;
2619
2620 if (!smu->ppt_funcs->get_fan_speed_pwm)
2621 return -EOPNOTSUPP;
2622
2623 if (!speed)
2624 return -EINVAL;
2625
2626 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2627
2628 return ret;
2629 }
2630
smu_set_fan_speed_pwm(void * handle,u32 speed)2631 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2632 {
2633 struct smu_context *smu = handle;
2634 int ret = 0;
2635
2636 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2637 return -EOPNOTSUPP;
2638
2639 if (!smu->ppt_funcs->set_fan_speed_pwm)
2640 return -EOPNOTSUPP;
2641
2642 if (speed == U32_MAX)
2643 return -EINVAL;
2644
2645 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2646 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2647 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2648 smu->user_dpm_profile.fan_speed_pwm = speed;
2649
2650 /* Override custom RPM setting as they cannot co-exist */
2651 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2652 smu->user_dpm_profile.fan_speed_rpm = 0;
2653 }
2654
2655 return ret;
2656 }
2657
smu_get_fan_speed_rpm(void * handle,uint32_t * speed)2658 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2659 {
2660 struct smu_context *smu = handle;
2661 int ret = 0;
2662
2663 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2664 return -EOPNOTSUPP;
2665
2666 if (!smu->ppt_funcs->get_fan_speed_rpm)
2667 return -EOPNOTSUPP;
2668
2669 if (!speed)
2670 return -EINVAL;
2671
2672 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2673
2674 return ret;
2675 }
2676
smu_set_deep_sleep_dcefclk(void * handle,uint32_t clk)2677 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2678 {
2679 struct smu_context *smu = handle;
2680
2681 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2682 return -EOPNOTSUPP;
2683
2684 return smu_set_min_dcef_deep_sleep(smu, clk);
2685 }
2686
smu_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)2687 static int smu_get_clock_by_type_with_latency(void *handle,
2688 enum amd_pp_clock_type type,
2689 struct pp_clock_levels_with_latency *clocks)
2690 {
2691 struct smu_context *smu = handle;
2692 enum smu_clk_type clk_type;
2693 int ret = 0;
2694
2695 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2696 return -EOPNOTSUPP;
2697
2698 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2699 switch (type) {
2700 case amd_pp_sys_clock:
2701 clk_type = SMU_GFXCLK;
2702 break;
2703 case amd_pp_mem_clock:
2704 clk_type = SMU_MCLK;
2705 break;
2706 case amd_pp_dcef_clock:
2707 clk_type = SMU_DCEFCLK;
2708 break;
2709 case amd_pp_disp_clock:
2710 clk_type = SMU_DISPCLK;
2711 break;
2712 default:
2713 dev_err(smu->adev->dev, "Invalid clock type!\n");
2714 return -EINVAL;
2715 }
2716
2717 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2718 }
2719
2720 return ret;
2721 }
2722
smu_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock_req)2723 static int smu_display_clock_voltage_request(void *handle,
2724 struct pp_display_clock_request *clock_req)
2725 {
2726 struct smu_context *smu = handle;
2727 int ret = 0;
2728
2729 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2730 return -EOPNOTSUPP;
2731
2732 if (smu->ppt_funcs->display_clock_voltage_request)
2733 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2734
2735 return ret;
2736 }
2737
2738
smu_display_disable_memory_clock_switch(void * handle,bool disable_memory_clock_switch)2739 static int smu_display_disable_memory_clock_switch(void *handle,
2740 bool disable_memory_clock_switch)
2741 {
2742 struct smu_context *smu = handle;
2743 int ret = -EINVAL;
2744
2745 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2746 return -EOPNOTSUPP;
2747
2748 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2749 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2750
2751 return ret;
2752 }
2753
smu_set_xgmi_pstate(void * handle,uint32_t pstate)2754 static int smu_set_xgmi_pstate(void *handle,
2755 uint32_t pstate)
2756 {
2757 struct smu_context *smu = handle;
2758 int ret = 0;
2759
2760 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2761 return -EOPNOTSUPP;
2762
2763 if (smu->ppt_funcs->set_xgmi_pstate)
2764 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2765
2766 if(ret)
2767 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2768
2769 return ret;
2770 }
2771
smu_get_baco_capability(void * handle,bool * cap)2772 static int smu_get_baco_capability(void *handle, bool *cap)
2773 {
2774 struct smu_context *smu = handle;
2775
2776 *cap = false;
2777
2778 if (!smu->pm_enabled)
2779 return 0;
2780
2781 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2782 *cap = smu->ppt_funcs->baco_is_support(smu);
2783
2784 return 0;
2785 }
2786
smu_baco_set_state(void * handle,int state)2787 static int smu_baco_set_state(void *handle, int state)
2788 {
2789 struct smu_context *smu = handle;
2790 int ret = 0;
2791
2792 if (!smu->pm_enabled)
2793 return -EOPNOTSUPP;
2794
2795 if (state == 0) {
2796 if (smu->ppt_funcs->baco_exit)
2797 ret = smu->ppt_funcs->baco_exit(smu);
2798 } else if (state == 1) {
2799 if (smu->ppt_funcs->baco_enter)
2800 ret = smu->ppt_funcs->baco_enter(smu);
2801 } else {
2802 return -EINVAL;
2803 }
2804
2805 if (ret)
2806 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2807 (state)?"enter":"exit");
2808
2809 return ret;
2810 }
2811
smu_mode1_reset_is_support(struct smu_context * smu)2812 bool smu_mode1_reset_is_support(struct smu_context *smu)
2813 {
2814 bool ret = false;
2815
2816 if (!smu->pm_enabled)
2817 return false;
2818
2819 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2820 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2821
2822 return ret;
2823 }
2824
smu_mode2_reset_is_support(struct smu_context * smu)2825 bool smu_mode2_reset_is_support(struct smu_context *smu)
2826 {
2827 bool ret = false;
2828
2829 if (!smu->pm_enabled)
2830 return false;
2831
2832 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2833 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2834
2835 return ret;
2836 }
2837
smu_mode1_reset(struct smu_context * smu)2838 int smu_mode1_reset(struct smu_context *smu)
2839 {
2840 int ret = 0;
2841
2842 if (!smu->pm_enabled)
2843 return -EOPNOTSUPP;
2844
2845 if (smu->ppt_funcs->mode1_reset)
2846 ret = smu->ppt_funcs->mode1_reset(smu);
2847
2848 return ret;
2849 }
2850
smu_mode2_reset(void * handle)2851 static int smu_mode2_reset(void *handle)
2852 {
2853 struct smu_context *smu = handle;
2854 int ret = 0;
2855
2856 if (!smu->pm_enabled)
2857 return -EOPNOTSUPP;
2858
2859 if (smu->ppt_funcs->mode2_reset)
2860 ret = smu->ppt_funcs->mode2_reset(smu);
2861
2862 if (ret)
2863 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2864
2865 return ret;
2866 }
2867
smu_enable_gfx_features(void * handle)2868 static int smu_enable_gfx_features(void *handle)
2869 {
2870 struct smu_context *smu = handle;
2871 int ret = 0;
2872
2873 if (!smu->pm_enabled)
2874 return -EOPNOTSUPP;
2875
2876 if (smu->ppt_funcs->enable_gfx_features)
2877 ret = smu->ppt_funcs->enable_gfx_features(smu);
2878
2879 if (ret)
2880 dev_err(smu->adev->dev, "enable gfx features failed!\n");
2881
2882 return ret;
2883 }
2884
smu_get_max_sustainable_clocks_by_dc(void * handle,struct pp_smu_nv_clock_table * max_clocks)2885 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2886 struct pp_smu_nv_clock_table *max_clocks)
2887 {
2888 struct smu_context *smu = handle;
2889 int ret = 0;
2890
2891 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2892 return -EOPNOTSUPP;
2893
2894 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2895 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2896
2897 return ret;
2898 }
2899
smu_get_uclk_dpm_states(void * handle,unsigned int * clock_values_in_khz,unsigned int * num_states)2900 static int smu_get_uclk_dpm_states(void *handle,
2901 unsigned int *clock_values_in_khz,
2902 unsigned int *num_states)
2903 {
2904 struct smu_context *smu = handle;
2905 int ret = 0;
2906
2907 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2908 return -EOPNOTSUPP;
2909
2910 if (smu->ppt_funcs->get_uclk_dpm_states)
2911 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2912
2913 return ret;
2914 }
2915
smu_get_current_power_state(void * handle)2916 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2917 {
2918 struct smu_context *smu = handle;
2919 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2920
2921 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2922 return -EOPNOTSUPP;
2923
2924 if (smu->ppt_funcs->get_current_power_state)
2925 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2926
2927 return pm_state;
2928 }
2929
smu_get_dpm_clock_table(void * handle,struct dpm_clocks * clock_table)2930 static int smu_get_dpm_clock_table(void *handle,
2931 struct dpm_clocks *clock_table)
2932 {
2933 struct smu_context *smu = handle;
2934 int ret = 0;
2935
2936 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2937 return -EOPNOTSUPP;
2938
2939 if (smu->ppt_funcs->get_dpm_clock_table)
2940 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2941
2942 return ret;
2943 }
2944
smu_sys_get_gpu_metrics(void * handle,void ** table)2945 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2946 {
2947 struct smu_context *smu = handle;
2948
2949 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2950 return -EOPNOTSUPP;
2951
2952 if (!smu->ppt_funcs->get_gpu_metrics)
2953 return -EOPNOTSUPP;
2954
2955 return smu->ppt_funcs->get_gpu_metrics(smu, table);
2956 }
2957
smu_enable_mgpu_fan_boost(void * handle)2958 static int smu_enable_mgpu_fan_boost(void *handle)
2959 {
2960 struct smu_context *smu = handle;
2961 int ret = 0;
2962
2963 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2964 return -EOPNOTSUPP;
2965
2966 if (smu->ppt_funcs->enable_mgpu_fan_boost)
2967 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2968
2969 return ret;
2970 }
2971
smu_gfx_state_change_set(void * handle,uint32_t state)2972 static int smu_gfx_state_change_set(void *handle,
2973 uint32_t state)
2974 {
2975 struct smu_context *smu = handle;
2976 int ret = 0;
2977
2978 if (smu->ppt_funcs->gfx_state_change_set)
2979 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
2980
2981 return ret;
2982 }
2983
smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)2984 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
2985 {
2986 int ret = 0;
2987
2988 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
2989 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
2990
2991 return ret;
2992 }
2993
smu_get_ecc_info(struct smu_context * smu,void * umc_ecc)2994 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
2995 {
2996 int ret = -EOPNOTSUPP;
2997
2998 if (smu->ppt_funcs &&
2999 smu->ppt_funcs->get_ecc_info)
3000 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
3001
3002 return ret;
3003
3004 }
3005
smu_get_prv_buffer_details(void * handle,void ** addr,size_t * size)3006 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3007 {
3008 struct smu_context *smu = handle;
3009 struct smu_table_context *smu_table = &smu->smu_table;
3010 struct smu_table *memory_pool = &smu_table->memory_pool;
3011
3012 if (!addr || !size)
3013 return -EINVAL;
3014
3015 *addr = NULL;
3016 *size = 0;
3017 if (memory_pool->bo) {
3018 *addr = memory_pool->cpu_addr;
3019 *size = memory_pool->size;
3020 }
3021
3022 return 0;
3023 }
3024
3025 static const struct amd_pm_funcs swsmu_pm_funcs = {
3026 /* export for sysfs */
3027 .set_fan_control_mode = smu_set_fan_control_mode,
3028 .get_fan_control_mode = smu_get_fan_control_mode,
3029 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3030 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3031 .force_clock_level = smu_force_ppclk_levels,
3032 .print_clock_levels = smu_print_ppclk_levels,
3033 .emit_clock_levels = smu_emit_ppclk_levels,
3034 .force_performance_level = smu_force_performance_level,
3035 .read_sensor = smu_read_sensor,
3036 .get_performance_level = smu_get_performance_level,
3037 .get_current_power_state = smu_get_current_power_state,
3038 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3039 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3040 .get_pp_num_states = smu_get_power_num_states,
3041 .get_pp_table = smu_sys_get_pp_table,
3042 .set_pp_table = smu_sys_set_pp_table,
3043 .switch_power_profile = smu_switch_power_profile,
3044 /* export to amdgpu */
3045 .dispatch_tasks = smu_handle_dpm_task,
3046 .load_firmware = smu_load_microcode,
3047 .set_powergating_by_smu = smu_dpm_set_power_gate,
3048 .set_power_limit = smu_set_power_limit,
3049 .get_power_limit = smu_get_power_limit,
3050 .get_power_profile_mode = smu_get_power_profile_mode,
3051 .set_power_profile_mode = smu_set_power_profile_mode,
3052 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3053 .set_mp1_state = smu_set_mp1_state,
3054 .gfx_state_change_set = smu_gfx_state_change_set,
3055 /* export to DC */
3056 .get_sclk = smu_get_sclk,
3057 .get_mclk = smu_get_mclk,
3058 .display_configuration_change = smu_display_configuration_change,
3059 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3060 .display_clock_voltage_request = smu_display_clock_voltage_request,
3061 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3062 .set_active_display_count = smu_set_display_count,
3063 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3064 .get_asic_baco_capability = smu_get_baco_capability,
3065 .set_asic_baco_state = smu_baco_set_state,
3066 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3067 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3068 .asic_reset_mode_2 = smu_mode2_reset,
3069 .asic_reset_enable_gfx_features = smu_enable_gfx_features,
3070 .set_df_cstate = smu_set_df_cstate,
3071 .set_xgmi_pstate = smu_set_xgmi_pstate,
3072 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3073 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3074 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3075 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3076 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3077 .get_dpm_clock_table = smu_get_dpm_clock_table,
3078 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3079 };
3080
smu_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)3081 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3082 uint64_t event_arg)
3083 {
3084 int ret = -EINVAL;
3085
3086 if (smu->ppt_funcs->wait_for_event)
3087 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3088
3089 return ret;
3090 }
3091
smu_stb_collect_info(struct smu_context * smu,void * buf,uint32_t size)3092 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3093 {
3094
3095 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3096 return -EOPNOTSUPP;
3097
3098 /* Confirm the buffer allocated is of correct size */
3099 if (size != smu->stb_context.stb_buf_size)
3100 return -EINVAL;
3101
3102 /*
3103 * No need to lock smu mutex as we access STB directly through MMIO
3104 * and not going through SMU messaging route (for now at least).
3105 * For registers access rely on implementation internal locking.
3106 */
3107 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3108 }
3109
3110 #if defined(CONFIG_DEBUG_FS)
3111
smu_stb_debugfs_open(struct inode * inode,struct file * filp)3112 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3113 {
3114 struct amdgpu_device *adev = filp->f_inode->i_private;
3115 struct smu_context *smu = adev->powerplay.pp_handle;
3116 unsigned char *buf;
3117 int r;
3118
3119 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3120 if (!buf)
3121 return -ENOMEM;
3122
3123 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3124 if (r)
3125 goto out;
3126
3127 filp->private_data = buf;
3128
3129 return 0;
3130
3131 out:
3132 kvfree(buf);
3133 return r;
3134 }
3135
smu_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)3136 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3137 loff_t *pos)
3138 {
3139 struct amdgpu_device *adev = filp->f_inode->i_private;
3140 struct smu_context *smu = adev->powerplay.pp_handle;
3141
3142
3143 if (!filp->private_data)
3144 return -EINVAL;
3145
3146 return simple_read_from_buffer(buf,
3147 size,
3148 pos, filp->private_data,
3149 smu->stb_context.stb_buf_size);
3150 }
3151
smu_stb_debugfs_release(struct inode * inode,struct file * filp)3152 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3153 {
3154 kvfree(filp->private_data);
3155 filp->private_data = NULL;
3156
3157 return 0;
3158 }
3159
3160 /*
3161 * We have to define not only read method but also
3162 * open and release because .read takes up to PAGE_SIZE
3163 * data each time so and so is invoked multiple times.
3164 * We allocate the STB buffer in .open and release it
3165 * in .release
3166 */
3167 static const struct file_operations smu_stb_debugfs_fops = {
3168 .owner = THIS_MODULE,
3169 .open = smu_stb_debugfs_open,
3170 .read = smu_stb_debugfs_read,
3171 .release = smu_stb_debugfs_release,
3172 .llseek = default_llseek,
3173 };
3174
3175 #endif
3176
amdgpu_smu_stb_debug_fs_init(struct amdgpu_device * adev)3177 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3178 {
3179 #if defined(CONFIG_DEBUG_FS)
3180
3181 struct smu_context *smu = adev->powerplay.pp_handle;
3182
3183 if (!smu || (!smu->stb_context.stb_buf_size))
3184 return;
3185
3186 debugfs_create_file_size("amdgpu_smu_stb_dump",
3187 S_IRUSR,
3188 adev_to_drm(adev)->primary->debugfs_root,
3189 adev,
3190 &smu_stb_debugfs_fops,
3191 smu->stb_context.stb_buf_size);
3192 #endif
3193 }
3194
smu_send_hbm_bad_pages_num(struct smu_context * smu,uint32_t size)3195 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3196 {
3197 int ret = 0;
3198
3199 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3200 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3201
3202 return ret;
3203 }
3204
smu_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)3205 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3206 {
3207 int ret = 0;
3208
3209 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3210 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
3211
3212 return ret;
3213 }
3214