1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63
64 #define mmMP1_SMN_C2PMSG_66 0x0282
65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
66
67 #define mmMP1_SMN_C2PMSG_82 0x0292
68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
69
70 #define mmMP1_SMN_C2PMSG_90 0x029a
71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
72
73 #define SMU13_VOLTAGE_SCALE 4
74
75 #define LINK_WIDTH_MAX 6
76 #define LINK_SPEED_MAX 3
77
78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
81 #define smnPCIE_LC_SPEED_CNTL 0x11140290
82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
84
85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
86 static const int link_speed[] = {25, 50, 80, 160};
87
smu_v13_0_init_microcode(struct smu_context * smu)88 int smu_v13_0_init_microcode(struct smu_context *smu)
89 {
90 struct amdgpu_device *adev = smu->adev;
91 char fw_name[30];
92 char ucode_prefix[30];
93 int err = 0;
94 const struct smc_firmware_header_v1_0 *hdr;
95 const struct common_firmware_header *header;
96 struct amdgpu_firmware_info *ucode = NULL;
97
98 /* doesn't need to load smu firmware in IOV mode */
99 if (amdgpu_sriov_vf(adev))
100 return 0;
101
102 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
103
104 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
105
106 err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
107 if (err)
108 goto out;
109
110 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
111 amdgpu_ucode_print_smc_hdr(&hdr->header);
112 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
113
114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
115 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
116 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
117 ucode->fw = adev->pm.fw;
118 header = (const struct common_firmware_header *)ucode->fw->data;
119 adev->firmware.fw_size +=
120 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
121 }
122
123 out:
124 if (err)
125 amdgpu_ucode_release(&adev->pm.fw);
126 return err;
127 }
128
smu_v13_0_fini_microcode(struct smu_context * smu)129 void smu_v13_0_fini_microcode(struct smu_context *smu)
130 {
131 struct amdgpu_device *adev = smu->adev;
132
133 amdgpu_ucode_release(&adev->pm.fw);
134 adev->pm.fw_version = 0;
135 }
136
smu_v13_0_load_microcode(struct smu_context * smu)137 int smu_v13_0_load_microcode(struct smu_context *smu)
138 {
139 #if 0
140 struct amdgpu_device *adev = smu->adev;
141 const uint32_t *src;
142 const struct smc_firmware_header_v1_0 *hdr;
143 uint32_t addr_start = MP1_SRAM;
144 uint32_t i;
145 uint32_t smc_fw_size;
146 uint32_t mp1_fw_flags;
147
148 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
149 src = (const uint32_t *)(adev->pm.fw->data +
150 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
151 smc_fw_size = hdr->header.ucode_size_bytes;
152
153 for (i = 1; i < smc_fw_size/4 - 1; i++) {
154 WREG32_PCIE(addr_start, src[i]);
155 addr_start += 4;
156 }
157
158 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
159 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
160 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
161 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
162
163 for (i = 0; i < adev->usec_timeout; i++) {
164 mp1_fw_flags = RREG32_PCIE(MP1_Public |
165 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
166 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
167 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
168 break;
169 udelay(1);
170 }
171
172 if (i == adev->usec_timeout)
173 return -ETIME;
174 #endif
175
176 return 0;
177 }
178
smu_v13_0_init_pptable_microcode(struct smu_context * smu)179 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
180 {
181 struct amdgpu_device *adev = smu->adev;
182 struct amdgpu_firmware_info *ucode = NULL;
183 uint32_t size = 0, pptable_id = 0;
184 int ret = 0;
185 void *table;
186
187 /* doesn't need to load smu firmware in IOV mode */
188 if (amdgpu_sriov_vf(adev))
189 return 0;
190
191 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
192 return 0;
193
194 if (!adev->scpm_enabled)
195 return 0;
196
197 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) ||
198 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) ||
199 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)))
200 return 0;
201
202 /* override pptable_id from driver parameter */
203 if (amdgpu_smu_pptable_id >= 0) {
204 pptable_id = amdgpu_smu_pptable_id;
205 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
206 } else {
207 pptable_id = smu->smu_table.boot_values.pp_table_id;
208 }
209
210 /* "pptable_id == 0" means vbios carries the pptable. */
211 if (!pptable_id)
212 return 0;
213
214 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
215 if (ret)
216 return ret;
217
218 smu->pptable_firmware.data = table;
219 smu->pptable_firmware.size = size;
220
221 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
222 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
223 ucode->fw = &smu->pptable_firmware;
224 adev->firmware.fw_size +=
225 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
226
227 return 0;
228 }
229
smu_v13_0_check_fw_status(struct smu_context * smu)230 int smu_v13_0_check_fw_status(struct smu_context *smu)
231 {
232 struct amdgpu_device *adev = smu->adev;
233 uint32_t mp1_fw_flags;
234
235 switch (adev->ip_versions[MP1_HWIP][0]) {
236 case IP_VERSION(13, 0, 4):
237 case IP_VERSION(13, 0, 11):
238 mp1_fw_flags = RREG32_PCIE(MP1_Public |
239 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
240 break;
241 default:
242 mp1_fw_flags = RREG32_PCIE(MP1_Public |
243 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
244 break;
245 }
246
247 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
248 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
249 return 0;
250
251 return -EIO;
252 }
253
smu_v13_0_check_fw_version(struct smu_context * smu)254 int smu_v13_0_check_fw_version(struct smu_context *smu)
255 {
256 struct amdgpu_device *adev = smu->adev;
257 uint32_t if_version = 0xff, smu_version = 0xff;
258 uint8_t smu_program, smu_major, smu_minor, smu_debug;
259 int ret = 0;
260
261 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
262 if (ret)
263 return ret;
264
265 smu_program = (smu_version >> 24) & 0xff;
266 smu_major = (smu_version >> 16) & 0xff;
267 smu_minor = (smu_version >> 8) & 0xff;
268 smu_debug = (smu_version >> 0) & 0xff;
269 if (smu->is_apu)
270 adev->pm.fw_version = smu_version;
271
272 switch (adev->ip_versions[MP1_HWIP][0]) {
273 case IP_VERSION(13, 0, 2):
274 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
275 break;
276 case IP_VERSION(13, 0, 0):
277 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0;
278 break;
279 case IP_VERSION(13, 0, 10):
280 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10;
281 break;
282 case IP_VERSION(13, 0, 7):
283 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
284 break;
285 case IP_VERSION(13, 0, 1):
286 case IP_VERSION(13, 0, 3):
287 case IP_VERSION(13, 0, 8):
288 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
289 break;
290 case IP_VERSION(13, 0, 4):
291 case IP_VERSION(13, 0, 11):
292 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
293 break;
294 case IP_VERSION(13, 0, 5):
295 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
296 break;
297 default:
298 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
299 adev->ip_versions[MP1_HWIP][0]);
300 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
301 break;
302 }
303
304 /* only for dGPU w/ SMU13*/
305 if (adev->pm.fw)
306 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
307 smu_program, smu_version, smu_major, smu_minor, smu_debug);
308
309 /*
310 * 1. if_version mismatch is not critical as our fw is designed
311 * to be backward compatible.
312 * 2. New fw usually brings some optimizations. But that's visible
313 * only on the paired driver.
314 * Considering above, we just leave user a verbal message instead
315 * of halt driver loading.
316 */
317 if (if_version != smu->smc_driver_if_version) {
318 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
319 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
320 smu->smc_driver_if_version, if_version,
321 smu_program, smu_version, smu_major, smu_minor, smu_debug);
322 dev_info(adev->dev, "SMU driver if version not matched\n");
323 }
324
325 return ret;
326 }
327
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)328 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
329 {
330 struct amdgpu_device *adev = smu->adev;
331 uint32_t ppt_offset_bytes;
332 const struct smc_firmware_header_v2_0 *v2;
333
334 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
335
336 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
337 *size = le32_to_cpu(v2->ppt_size_bytes);
338 *table = (uint8_t *)v2 + ppt_offset_bytes;
339
340 return 0;
341 }
342
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)343 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
344 uint32_t *size, uint32_t pptable_id)
345 {
346 struct amdgpu_device *adev = smu->adev;
347 const struct smc_firmware_header_v2_1 *v2_1;
348 struct smc_soft_pptable_entry *entries;
349 uint32_t pptable_count = 0;
350 int i = 0;
351
352 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
353 entries = (struct smc_soft_pptable_entry *)
354 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
355 pptable_count = le32_to_cpu(v2_1->pptable_count);
356 for (i = 0; i < pptable_count; i++) {
357 if (le32_to_cpu(entries[i].id) == pptable_id) {
358 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
359 *size = le32_to_cpu(entries[i].ppt_size_bytes);
360 break;
361 }
362 }
363
364 if (i == pptable_count)
365 return -EINVAL;
366
367 return 0;
368 }
369
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)370 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
371 {
372 struct amdgpu_device *adev = smu->adev;
373 uint16_t atom_table_size;
374 uint8_t frev, crev;
375 int ret, index;
376
377 dev_info(adev->dev, "use vbios provided pptable\n");
378 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
379 powerplayinfo);
380
381 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
382 (uint8_t **)table);
383 if (ret)
384 return ret;
385
386 if (size)
387 *size = atom_table_size;
388
389 return 0;
390 }
391
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)392 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
393 void **table,
394 uint32_t *size,
395 uint32_t pptable_id)
396 {
397 const struct smc_firmware_header_v1_0 *hdr;
398 struct amdgpu_device *adev = smu->adev;
399 uint16_t version_major, version_minor;
400 int ret;
401
402 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
403 if (!hdr)
404 return -EINVAL;
405
406 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
407
408 version_major = le16_to_cpu(hdr->header.header_version_major);
409 version_minor = le16_to_cpu(hdr->header.header_version_minor);
410 if (version_major != 2) {
411 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
412 version_major, version_minor);
413 return -EINVAL;
414 }
415
416 switch (version_minor) {
417 case 0:
418 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
419 break;
420 case 1:
421 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
422 break;
423 default:
424 ret = -EINVAL;
425 break;
426 }
427
428 return ret;
429 }
430
smu_v13_0_setup_pptable(struct smu_context * smu)431 int smu_v13_0_setup_pptable(struct smu_context *smu)
432 {
433 struct amdgpu_device *adev = smu->adev;
434 uint32_t size = 0, pptable_id = 0;
435 void *table;
436 int ret = 0;
437
438 /* override pptable_id from driver parameter */
439 if (amdgpu_smu_pptable_id >= 0) {
440 pptable_id = amdgpu_smu_pptable_id;
441 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
442 } else {
443 pptable_id = smu->smu_table.boot_values.pp_table_id;
444 }
445
446 /* force using vbios pptable in sriov mode */
447 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
448 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
449 else
450 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
451
452 if (ret)
453 return ret;
454
455 if (!smu->smu_table.power_play_table)
456 smu->smu_table.power_play_table = table;
457 if (!smu->smu_table.power_play_table_size)
458 smu->smu_table.power_play_table_size = size;
459
460 return 0;
461 }
462
smu_v13_0_init_smc_tables(struct smu_context * smu)463 int smu_v13_0_init_smc_tables(struct smu_context *smu)
464 {
465 struct smu_table_context *smu_table = &smu->smu_table;
466 struct smu_table *tables = smu_table->tables;
467 int ret = 0;
468
469 smu_table->driver_pptable =
470 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
471 if (!smu_table->driver_pptable) {
472 ret = -ENOMEM;
473 goto err0_out;
474 }
475
476 smu_table->max_sustainable_clocks =
477 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
478 if (!smu_table->max_sustainable_clocks) {
479 ret = -ENOMEM;
480 goto err1_out;
481 }
482
483 /* Aldebaran does not support OVERDRIVE */
484 if (tables[SMU_TABLE_OVERDRIVE].size) {
485 smu_table->overdrive_table =
486 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
487 if (!smu_table->overdrive_table) {
488 ret = -ENOMEM;
489 goto err2_out;
490 }
491
492 smu_table->boot_overdrive_table =
493 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
494 if (!smu_table->boot_overdrive_table) {
495 ret = -ENOMEM;
496 goto err3_out;
497 }
498 }
499
500 smu_table->combo_pptable =
501 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
502 if (!smu_table->combo_pptable) {
503 ret = -ENOMEM;
504 goto err4_out;
505 }
506
507 return 0;
508
509 err4_out:
510 kfree(smu_table->boot_overdrive_table);
511 err3_out:
512 kfree(smu_table->overdrive_table);
513 err2_out:
514 kfree(smu_table->max_sustainable_clocks);
515 err1_out:
516 kfree(smu_table->driver_pptable);
517 err0_out:
518 return ret;
519 }
520
smu_v13_0_fini_smc_tables(struct smu_context * smu)521 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
522 {
523 struct smu_table_context *smu_table = &smu->smu_table;
524 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
525
526 kfree(smu_table->gpu_metrics_table);
527 kfree(smu_table->combo_pptable);
528 kfree(smu_table->boot_overdrive_table);
529 kfree(smu_table->overdrive_table);
530 kfree(smu_table->max_sustainable_clocks);
531 kfree(smu_table->driver_pptable);
532 smu_table->gpu_metrics_table = NULL;
533 smu_table->combo_pptable = NULL;
534 smu_table->boot_overdrive_table = NULL;
535 smu_table->overdrive_table = NULL;
536 smu_table->max_sustainable_clocks = NULL;
537 smu_table->driver_pptable = NULL;
538 kfree(smu_table->hardcode_pptable);
539 smu_table->hardcode_pptable = NULL;
540
541 kfree(smu_table->ecc_table);
542 kfree(smu_table->metrics_table);
543 kfree(smu_table->watermarks_table);
544 smu_table->ecc_table = NULL;
545 smu_table->metrics_table = NULL;
546 smu_table->watermarks_table = NULL;
547 smu_table->metrics_time = 0;
548
549 kfree(smu_dpm->dpm_context);
550 kfree(smu_dpm->golden_dpm_context);
551 kfree(smu_dpm->dpm_current_power_state);
552 kfree(smu_dpm->dpm_request_power_state);
553 smu_dpm->dpm_context = NULL;
554 smu_dpm->golden_dpm_context = NULL;
555 smu_dpm->dpm_context_size = 0;
556 smu_dpm->dpm_current_power_state = NULL;
557 smu_dpm->dpm_request_power_state = NULL;
558
559 return 0;
560 }
561
smu_v13_0_init_power(struct smu_context * smu)562 int smu_v13_0_init_power(struct smu_context *smu)
563 {
564 struct smu_power_context *smu_power = &smu->smu_power;
565
566 if (smu_power->power_context || smu_power->power_context_size != 0)
567 return -EINVAL;
568
569 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
570 GFP_KERNEL);
571 if (!smu_power->power_context)
572 return -ENOMEM;
573 smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
574
575 return 0;
576 }
577
smu_v13_0_fini_power(struct smu_context * smu)578 int smu_v13_0_fini_power(struct smu_context *smu)
579 {
580 struct smu_power_context *smu_power = &smu->smu_power;
581
582 if (!smu_power->power_context || smu_power->power_context_size == 0)
583 return -EINVAL;
584
585 kfree(smu_power->power_context);
586 smu_power->power_context = NULL;
587 smu_power->power_context_size = 0;
588
589 return 0;
590 }
591
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)592 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
593 {
594 int ret, index;
595 uint16_t size;
596 uint8_t frev, crev;
597 struct atom_common_table_header *header;
598 struct atom_firmware_info_v3_4 *v_3_4;
599 struct atom_firmware_info_v3_3 *v_3_3;
600 struct atom_firmware_info_v3_1 *v_3_1;
601 struct atom_smu_info_v3_6 *smu_info_v3_6;
602 struct atom_smu_info_v4_0 *smu_info_v4_0;
603
604 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
605 firmwareinfo);
606
607 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
608 (uint8_t **)&header);
609 if (ret)
610 return ret;
611
612 if (header->format_revision != 3) {
613 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
614 return -EINVAL;
615 }
616
617 switch (header->content_revision) {
618 case 0:
619 case 1:
620 case 2:
621 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
622 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
623 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
624 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
625 smu->smu_table.boot_values.socclk = 0;
626 smu->smu_table.boot_values.dcefclk = 0;
627 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
628 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
629 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
630 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
631 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
632 smu->smu_table.boot_values.pp_table_id = 0;
633 break;
634 case 3:
635 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
636 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
637 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
638 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
639 smu->smu_table.boot_values.socclk = 0;
640 smu->smu_table.boot_values.dcefclk = 0;
641 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
642 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
643 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
644 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
645 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
646 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
647 break;
648 case 4:
649 default:
650 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
651 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
652 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
653 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
654 smu->smu_table.boot_values.socclk = 0;
655 smu->smu_table.boot_values.dcefclk = 0;
656 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
657 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
658 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
659 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
660 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
661 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
662 break;
663 }
664
665 smu->smu_table.boot_values.format_revision = header->format_revision;
666 smu->smu_table.boot_values.content_revision = header->content_revision;
667
668 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
669 smu_info);
670 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
671 (uint8_t **)&header)) {
672
673 if ((frev == 3) && (crev == 6)) {
674 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
675
676 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
677 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
678 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
679 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
680 } else if ((frev == 3) && (crev == 1)) {
681 return 0;
682 } else if ((frev == 4) && (crev == 0)) {
683 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
684
685 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
686 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
687 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
688 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
689 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
690 } else {
691 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
692 (uint32_t)frev, (uint32_t)crev);
693 }
694 }
695
696 return 0;
697 }
698
699
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)700 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
701 {
702 struct smu_table_context *smu_table = &smu->smu_table;
703 struct smu_table *memory_pool = &smu_table->memory_pool;
704 int ret = 0;
705 uint64_t address;
706 uint32_t address_low, address_high;
707
708 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
709 return ret;
710
711 address = memory_pool->mc_address;
712 address_high = (uint32_t)upper_32_bits(address);
713 address_low = (uint32_t)lower_32_bits(address);
714
715 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
716 address_high, NULL);
717 if (ret)
718 return ret;
719 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
720 address_low, NULL);
721 if (ret)
722 return ret;
723 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
724 (uint32_t)memory_pool->size, NULL);
725 if (ret)
726 return ret;
727
728 return ret;
729 }
730
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)731 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
732 {
733 int ret;
734
735 ret = smu_cmn_send_smc_msg_with_param(smu,
736 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
737 if (ret)
738 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
739
740 return ret;
741 }
742
smu_v13_0_set_driver_table_location(struct smu_context * smu)743 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
744 {
745 struct smu_table *driver_table = &smu->smu_table.driver_table;
746 int ret = 0;
747
748 if (driver_table->mc_address) {
749 ret = smu_cmn_send_smc_msg_with_param(smu,
750 SMU_MSG_SetDriverDramAddrHigh,
751 upper_32_bits(driver_table->mc_address),
752 NULL);
753 if (!ret)
754 ret = smu_cmn_send_smc_msg_with_param(smu,
755 SMU_MSG_SetDriverDramAddrLow,
756 lower_32_bits(driver_table->mc_address),
757 NULL);
758 }
759
760 return ret;
761 }
762
smu_v13_0_set_tool_table_location(struct smu_context * smu)763 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
764 {
765 int ret = 0;
766 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
767
768 if (tool_table->mc_address) {
769 ret = smu_cmn_send_smc_msg_with_param(smu,
770 SMU_MSG_SetToolsDramAddrHigh,
771 upper_32_bits(tool_table->mc_address),
772 NULL);
773 if (!ret)
774 ret = smu_cmn_send_smc_msg_with_param(smu,
775 SMU_MSG_SetToolsDramAddrLow,
776 lower_32_bits(tool_table->mc_address),
777 NULL);
778 }
779
780 return ret;
781 }
782
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)783 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
784 {
785 int ret = 0;
786
787 if (!smu->pm_enabled)
788 return ret;
789
790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
791
792 return ret;
793 }
794
smu_v13_0_set_allowed_mask(struct smu_context * smu)795 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
796 {
797 struct smu_feature *feature = &smu->smu_feature;
798 int ret = 0;
799 uint32_t feature_mask[2];
800
801 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
802 feature->feature_num < 64)
803 return -EINVAL;
804
805 bitmap_to_arr32(feature_mask, feature->allowed, 64);
806
807 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
808 feature_mask[1], NULL);
809 if (ret)
810 return ret;
811
812 return smu_cmn_send_smc_msg_with_param(smu,
813 SMU_MSG_SetAllowedFeaturesMaskLow,
814 feature_mask[0],
815 NULL);
816 }
817
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)818 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
819 {
820 int ret = 0;
821 struct amdgpu_device *adev = smu->adev;
822
823 switch (adev->ip_versions[MP1_HWIP][0]) {
824 case IP_VERSION(13, 0, 0):
825 case IP_VERSION(13, 0, 1):
826 case IP_VERSION(13, 0, 3):
827 case IP_VERSION(13, 0, 4):
828 case IP_VERSION(13, 0, 5):
829 case IP_VERSION(13, 0, 7):
830 case IP_VERSION(13, 0, 8):
831 case IP_VERSION(13, 0, 10):
832 case IP_VERSION(13, 0, 11):
833 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
834 return 0;
835 if (enable)
836 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
837 else
838 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
839 break;
840 default:
841 break;
842 }
843
844 return ret;
845 }
846
smu_v13_0_system_features_control(struct smu_context * smu,bool en)847 int smu_v13_0_system_features_control(struct smu_context *smu,
848 bool en)
849 {
850 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
851 SMU_MSG_DisableAllSmuFeatures), NULL);
852 }
853
smu_v13_0_notify_display_change(struct smu_context * smu)854 int smu_v13_0_notify_display_change(struct smu_context *smu)
855 {
856 int ret = 0;
857
858 if (!smu->pm_enabled)
859 return ret;
860
861 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
862 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
863 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
864
865 return ret;
866 }
867
868 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)869 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
870 enum smu_clk_type clock_select)
871 {
872 int ret = 0;
873 int clk_id;
874
875 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
876 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
877 return 0;
878
879 clk_id = smu_cmn_to_asic_specific_index(smu,
880 CMN2ASIC_MAPPING_CLK,
881 clock_select);
882 if (clk_id < 0)
883 return -EINVAL;
884
885 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
886 clk_id << 16, clock);
887 if (ret) {
888 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
889 return ret;
890 }
891
892 if (*clock != 0)
893 return 0;
894
895 /* if DC limit is zero, return AC limit */
896 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
897 clk_id << 16, clock);
898 if (ret) {
899 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
900 return ret;
901 }
902
903 return 0;
904 }
905
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)906 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
907 {
908 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
909 smu->smu_table.max_sustainable_clocks;
910 int ret = 0;
911
912 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
913 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
914 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
915 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
916 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
917 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
918
919 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
920 ret = smu_v13_0_get_max_sustainable_clock(smu,
921 &(max_sustainable_clocks->uclock),
922 SMU_UCLK);
923 if (ret) {
924 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
925 __func__);
926 return ret;
927 }
928 }
929
930 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
931 ret = smu_v13_0_get_max_sustainable_clock(smu,
932 &(max_sustainable_clocks->soc_clock),
933 SMU_SOCCLK);
934 if (ret) {
935 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
936 __func__);
937 return ret;
938 }
939 }
940
941 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
942 ret = smu_v13_0_get_max_sustainable_clock(smu,
943 &(max_sustainable_clocks->dcef_clock),
944 SMU_DCEFCLK);
945 if (ret) {
946 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
947 __func__);
948 return ret;
949 }
950
951 ret = smu_v13_0_get_max_sustainable_clock(smu,
952 &(max_sustainable_clocks->display_clock),
953 SMU_DISPCLK);
954 if (ret) {
955 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
956 __func__);
957 return ret;
958 }
959 ret = smu_v13_0_get_max_sustainable_clock(smu,
960 &(max_sustainable_clocks->phy_clock),
961 SMU_PHYCLK);
962 if (ret) {
963 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
964 __func__);
965 return ret;
966 }
967 ret = smu_v13_0_get_max_sustainable_clock(smu,
968 &(max_sustainable_clocks->pixel_clock),
969 SMU_PIXCLK);
970 if (ret) {
971 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
972 __func__);
973 return ret;
974 }
975 }
976
977 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
978 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
979
980 return 0;
981 }
982
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)983 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
984 uint32_t *power_limit)
985 {
986 int power_src;
987 int ret = 0;
988
989 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
990 return -EINVAL;
991
992 power_src = smu_cmn_to_asic_specific_index(smu,
993 CMN2ASIC_MAPPING_PWR,
994 smu->adev->pm.ac_power ?
995 SMU_POWER_SOURCE_AC :
996 SMU_POWER_SOURCE_DC);
997 if (power_src < 0)
998 return -EINVAL;
999
1000 ret = smu_cmn_send_smc_msg_with_param(smu,
1001 SMU_MSG_GetPptLimit,
1002 power_src << 16,
1003 power_limit);
1004 if (ret)
1005 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1006
1007 return ret;
1008 }
1009
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1010 int smu_v13_0_set_power_limit(struct smu_context *smu,
1011 enum smu_ppt_limit_type limit_type,
1012 uint32_t limit)
1013 {
1014 int ret = 0;
1015
1016 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1017 return -EINVAL;
1018
1019 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1020 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1021 return -EOPNOTSUPP;
1022 }
1023
1024 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1025 if (ret) {
1026 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1027 return ret;
1028 }
1029
1030 smu->current_power_limit = limit;
1031
1032 return 0;
1033 }
1034
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)1035 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1036 {
1037 return smu_cmn_send_smc_msg(smu,
1038 SMU_MSG_AllowIHHostInterrupt,
1039 NULL);
1040 }
1041
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1042 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1043 {
1044 int ret = 0;
1045
1046 if (smu->dc_controlled_by_gpio &&
1047 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1048 ret = smu_v13_0_allow_ih_interrupt(smu);
1049
1050 return ret;
1051 }
1052
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1053 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1054 {
1055 int ret = 0;
1056
1057 if (!smu->irq_source.num_types)
1058 return 0;
1059
1060 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1061 if (ret)
1062 return ret;
1063
1064 return smu_v13_0_process_pending_interrupt(smu);
1065 }
1066
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1067 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1068 {
1069 if (!smu->irq_source.num_types)
1070 return 0;
1071
1072 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1073 }
1074
convert_to_vddc(uint8_t vid)1075 static uint16_t convert_to_vddc(uint8_t vid)
1076 {
1077 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1078 }
1079
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1080 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1081 {
1082 struct amdgpu_device *adev = smu->adev;
1083 uint32_t vdd = 0, val_vid = 0;
1084
1085 if (!value)
1086 return -EINVAL;
1087 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1088 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1089 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1090
1091 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1092
1093 *value = vdd;
1094
1095 return 0;
1096
1097 }
1098
1099 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1100 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1101 struct pp_display_clock_request
1102 *clock_req)
1103 {
1104 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1105 int ret = 0;
1106 enum smu_clk_type clk_select = 0;
1107 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1108
1109 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1110 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1111 switch (clk_type) {
1112 case amd_pp_dcef_clock:
1113 clk_select = SMU_DCEFCLK;
1114 break;
1115 case amd_pp_disp_clock:
1116 clk_select = SMU_DISPCLK;
1117 break;
1118 case amd_pp_pixel_clock:
1119 clk_select = SMU_PIXCLK;
1120 break;
1121 case amd_pp_phy_clock:
1122 clk_select = SMU_PHYCLK;
1123 break;
1124 case amd_pp_mem_clock:
1125 clk_select = SMU_UCLK;
1126 break;
1127 default:
1128 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1129 ret = -EINVAL;
1130 break;
1131 }
1132
1133 if (ret)
1134 goto failed;
1135
1136 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1137 return 0;
1138
1139 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1140
1141 if(clk_select == SMU_UCLK)
1142 smu->hard_min_uclk_req_from_dal = clk_freq;
1143 }
1144
1145 failed:
1146 return ret;
1147 }
1148
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1149 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1150 {
1151 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1152 return AMD_FAN_CTRL_MANUAL;
1153 else
1154 return AMD_FAN_CTRL_AUTO;
1155 }
1156
1157 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1158 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1159 {
1160 int ret = 0;
1161
1162 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1163 return 0;
1164
1165 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1166 if (ret)
1167 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1168 __func__, (auto_fan_control ? "Start" : "Stop"));
1169
1170 return ret;
1171 }
1172
1173 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1174 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1175 {
1176 struct amdgpu_device *adev = smu->adev;
1177
1178 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1179 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1180 CG_FDO_CTRL2, TMIN, 0));
1181 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1182 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1183 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1184
1185 return 0;
1186 }
1187
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1188 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1189 uint32_t speed)
1190 {
1191 struct amdgpu_device *adev = smu->adev;
1192 uint32_t duty100, duty;
1193 uint64_t tmp64;
1194
1195 speed = MIN(speed, 255);
1196
1197 if (smu_v13_0_auto_fan_control(smu, 0))
1198 return -EINVAL;
1199
1200 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1201 CG_FDO_CTRL1, FMAX_DUTY100);
1202 if (!duty100)
1203 return -EINVAL;
1204
1205 tmp64 = (uint64_t)speed * duty100;
1206 do_div(tmp64, 255);
1207 duty = (uint32_t)tmp64;
1208
1209 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1210 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1211 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1212
1213 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1214 }
1215
1216 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1217 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1218 uint32_t mode)
1219 {
1220 int ret = 0;
1221
1222 switch (mode) {
1223 case AMD_FAN_CTRL_NONE:
1224 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1225 break;
1226 case AMD_FAN_CTRL_MANUAL:
1227 ret = smu_v13_0_auto_fan_control(smu, 0);
1228 break;
1229 case AMD_FAN_CTRL_AUTO:
1230 ret = smu_v13_0_auto_fan_control(smu, 1);
1231 break;
1232 default:
1233 break;
1234 }
1235
1236 if (ret) {
1237 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1238 return -EINVAL;
1239 }
1240
1241 return ret;
1242 }
1243
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1244 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1245 uint32_t speed)
1246 {
1247 struct amdgpu_device *adev = smu->adev;
1248 uint32_t crystal_clock_freq = 2500;
1249 uint32_t tach_period;
1250 int ret;
1251
1252 if (!speed)
1253 return -EINVAL;
1254
1255 ret = smu_v13_0_auto_fan_control(smu, 0);
1256 if (ret)
1257 return ret;
1258
1259 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1260 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1261 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1262 CG_TACH_CTRL, TARGET_PERIOD,
1263 tach_period));
1264
1265 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1266 }
1267
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1268 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1269 uint32_t pstate)
1270 {
1271 int ret = 0;
1272 ret = smu_cmn_send_smc_msg_with_param(smu,
1273 SMU_MSG_SetXgmiMode,
1274 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1275 NULL);
1276 return ret;
1277 }
1278
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1279 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1280 struct amdgpu_irq_src *source,
1281 unsigned tyep,
1282 enum amdgpu_interrupt_state state)
1283 {
1284 struct smu_context *smu = adev->powerplay.pp_handle;
1285 uint32_t low, high;
1286 uint32_t val = 0;
1287
1288 switch (state) {
1289 case AMDGPU_IRQ_STATE_DISABLE:
1290 /* For THM irqs */
1291 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1292 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1293 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1294 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1295
1296 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1297
1298 /* For MP1 SW irqs */
1299 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1300 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1301 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1302
1303 break;
1304 case AMDGPU_IRQ_STATE_ENABLE:
1305 /* For THM irqs */
1306 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1307 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1308 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1309 smu->thermal_range.software_shutdown_temp);
1310
1311 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1312 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1313 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1314 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1315 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1316 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1317 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1318 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1319 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1320
1321 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1322 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1323 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1324 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1325
1326 /* For MP1 SW irqs */
1327 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1328 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1329 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1330 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1331
1332 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1333 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1334 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1335
1336 break;
1337 default:
1338 break;
1339 }
1340
1341 return 0;
1342 }
1343
smu_v13_0_ack_ac_dc_interrupt(struct smu_context * smu)1344 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1345 {
1346 return smu_cmn_send_smc_msg(smu,
1347 SMU_MSG_ReenableAcDcInterrupt,
1348 NULL);
1349 }
1350
1351 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1352 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1353 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1354
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1355 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1356 struct amdgpu_irq_src *source,
1357 struct amdgpu_iv_entry *entry)
1358 {
1359 struct smu_context *smu = adev->powerplay.pp_handle;
1360 uint32_t client_id = entry->client_id;
1361 uint32_t src_id = entry->src_id;
1362 /*
1363 * ctxid is used to distinguish different
1364 * events for SMCToHost interrupt.
1365 */
1366 uint32_t ctxid = entry->src_data[0];
1367 uint32_t data;
1368 uint32_t high;
1369
1370 if (client_id == SOC15_IH_CLIENTID_THM) {
1371 switch (src_id) {
1372 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1373 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1374 /*
1375 * SW CTF just occurred.
1376 * Try to do a graceful shutdown to prevent further damage.
1377 */
1378 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1379 orderly_poweroff(true);
1380 break;
1381 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1382 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1383 break;
1384 default:
1385 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1386 src_id);
1387 break;
1388 }
1389 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1390 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1391 /*
1392 * HW CTF just occurred. Shutdown to prevent further damage.
1393 */
1394 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1395 orderly_poweroff(true);
1396 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1397 if (src_id == 0xfe) {
1398 /* ACK SMUToHost interrupt */
1399 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1400 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1401 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1402
1403 switch (ctxid) {
1404 case 0x3:
1405 dev_dbg(adev->dev, "Switched to AC mode!\n");
1406 smu_v13_0_ack_ac_dc_interrupt(smu);
1407 break;
1408 case 0x4:
1409 dev_dbg(adev->dev, "Switched to DC mode!\n");
1410 smu_v13_0_ack_ac_dc_interrupt(smu);
1411 break;
1412 case 0x7:
1413 /*
1414 * Increment the throttle interrupt counter
1415 */
1416 atomic64_inc(&smu->throttle_int_counter);
1417
1418 if (!atomic_read(&adev->throttling_logging_enabled))
1419 return 0;
1420
1421 if (__ratelimit(&adev->throttling_logging_rs))
1422 schedule_work(&smu->throttling_logging_work);
1423
1424 break;
1425 case 0x8:
1426 high = smu->thermal_range.software_shutdown_temp +
1427 smu->thermal_range.software_shutdown_temp_offset;
1428 high = min_t(typeof(high),
1429 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1430 high);
1431 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1432 high,
1433 smu->thermal_range.software_shutdown_temp_offset);
1434
1435 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1436 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1437 DIG_THERM_INTH,
1438 (high & 0xff));
1439 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1440 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1441 break;
1442 case 0x9:
1443 high = min_t(typeof(high),
1444 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1445 smu->thermal_range.software_shutdown_temp);
1446 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1447
1448 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1449 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1450 DIG_THERM_INTH,
1451 (high & 0xff));
1452 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1453 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1454 break;
1455 }
1456 }
1457 }
1458
1459 return 0;
1460 }
1461
1462 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1463 {
1464 .set = smu_v13_0_set_irq_state,
1465 .process = smu_v13_0_irq_process,
1466 };
1467
smu_v13_0_register_irq_handler(struct smu_context * smu)1468 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1469 {
1470 struct amdgpu_device *adev = smu->adev;
1471 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1472 int ret = 0;
1473
1474 if (amdgpu_sriov_vf(adev))
1475 return 0;
1476
1477 irq_src->num_types = 1;
1478 irq_src->funcs = &smu_v13_0_irq_funcs;
1479
1480 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1481 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1482 irq_src);
1483 if (ret)
1484 return ret;
1485
1486 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1487 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1488 irq_src);
1489 if (ret)
1490 return ret;
1491
1492 /* Register CTF(GPIO_19) interrupt */
1493 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1494 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1495 irq_src);
1496 if (ret)
1497 return ret;
1498
1499 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1500 0xfe,
1501 irq_src);
1502 if (ret)
1503 return ret;
1504
1505 return ret;
1506 }
1507
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1508 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1509 struct pp_smu_nv_clock_table *max_clocks)
1510 {
1511 struct smu_table_context *table_context = &smu->smu_table;
1512 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1513
1514 if (!max_clocks || !table_context->max_sustainable_clocks)
1515 return -EINVAL;
1516
1517 sustainable_clocks = table_context->max_sustainable_clocks;
1518
1519 max_clocks->dcfClockInKhz =
1520 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1521 max_clocks->displayClockInKhz =
1522 (unsigned int) sustainable_clocks->display_clock * 1000;
1523 max_clocks->phyClockInKhz =
1524 (unsigned int) sustainable_clocks->phy_clock * 1000;
1525 max_clocks->pixelClockInKhz =
1526 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1527 max_clocks->uClockInKhz =
1528 (unsigned int) sustainable_clocks->uclock * 1000;
1529 max_clocks->socClockInKhz =
1530 (unsigned int) sustainable_clocks->soc_clock * 1000;
1531 max_clocks->dscClockInKhz = 0;
1532 max_clocks->dppClockInKhz = 0;
1533 max_clocks->fabricClockInKhz = 0;
1534
1535 return 0;
1536 }
1537
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1538 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1539 {
1540 int ret = 0;
1541
1542 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1543
1544 return ret;
1545 }
1546
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1547 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1548 uint64_t event_arg)
1549 {
1550 int ret = 0;
1551
1552 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1553 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1554
1555 return ret;
1556 }
1557
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1558 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1559 uint64_t event_arg)
1560 {
1561 int ret = -EINVAL;
1562
1563 switch (event) {
1564 case SMU_EVENT_RESET_COMPLETE:
1565 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1566 break;
1567 default:
1568 break;
1569 }
1570
1571 return ret;
1572 }
1573
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1574 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1575 uint32_t *min, uint32_t *max)
1576 {
1577 int ret = 0, clk_id = 0;
1578 uint32_t param = 0;
1579 uint32_t clock_limit;
1580
1581 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1582 switch (clk_type) {
1583 case SMU_MCLK:
1584 case SMU_UCLK:
1585 clock_limit = smu->smu_table.boot_values.uclk;
1586 break;
1587 case SMU_GFXCLK:
1588 case SMU_SCLK:
1589 clock_limit = smu->smu_table.boot_values.gfxclk;
1590 break;
1591 case SMU_SOCCLK:
1592 clock_limit = smu->smu_table.boot_values.socclk;
1593 break;
1594 default:
1595 clock_limit = 0;
1596 break;
1597 }
1598
1599 /* clock in Mhz unit */
1600 if (min)
1601 *min = clock_limit / 100;
1602 if (max)
1603 *max = clock_limit / 100;
1604
1605 return 0;
1606 }
1607
1608 clk_id = smu_cmn_to_asic_specific_index(smu,
1609 CMN2ASIC_MAPPING_CLK,
1610 clk_type);
1611 if (clk_id < 0) {
1612 ret = -EINVAL;
1613 goto failed;
1614 }
1615 param = (clk_id & 0xffff) << 16;
1616
1617 if (max) {
1618 if (smu->adev->pm.ac_power)
1619 ret = smu_cmn_send_smc_msg_with_param(smu,
1620 SMU_MSG_GetMaxDpmFreq,
1621 param,
1622 max);
1623 else
1624 ret = smu_cmn_send_smc_msg_with_param(smu,
1625 SMU_MSG_GetDcModeMaxDpmFreq,
1626 param,
1627 max);
1628 if (ret)
1629 goto failed;
1630 }
1631
1632 if (min) {
1633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1634 if (ret)
1635 goto failed;
1636 }
1637
1638 failed:
1639 return ret;
1640 }
1641
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1642 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1643 enum smu_clk_type clk_type,
1644 uint32_t min,
1645 uint32_t max)
1646 {
1647 int ret = 0, clk_id = 0;
1648 uint32_t param;
1649
1650 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1651 return 0;
1652
1653 clk_id = smu_cmn_to_asic_specific_index(smu,
1654 CMN2ASIC_MAPPING_CLK,
1655 clk_type);
1656 if (clk_id < 0)
1657 return clk_id;
1658
1659 if (max > 0) {
1660 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1661 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1662 param, NULL);
1663 if (ret)
1664 goto out;
1665 }
1666
1667 if (min > 0) {
1668 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1669 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1670 param, NULL);
1671 if (ret)
1672 goto out;
1673 }
1674
1675 out:
1676 return ret;
1677 }
1678
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1679 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1680 enum smu_clk_type clk_type,
1681 uint32_t min,
1682 uint32_t max)
1683 {
1684 int ret = 0, clk_id = 0;
1685 uint32_t param;
1686
1687 if (min <= 0 && max <= 0)
1688 return -EINVAL;
1689
1690 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1691 return 0;
1692
1693 clk_id = smu_cmn_to_asic_specific_index(smu,
1694 CMN2ASIC_MAPPING_CLK,
1695 clk_type);
1696 if (clk_id < 0)
1697 return clk_id;
1698
1699 if (max > 0) {
1700 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1701 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1702 param, NULL);
1703 if (ret)
1704 return ret;
1705 }
1706
1707 if (min > 0) {
1708 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1709 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1710 param, NULL);
1711 if (ret)
1712 return ret;
1713 }
1714
1715 return ret;
1716 }
1717
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1718 int smu_v13_0_set_performance_level(struct smu_context *smu,
1719 enum amd_dpm_forced_level level)
1720 {
1721 struct smu_13_0_dpm_context *dpm_context =
1722 smu->smu_dpm.dpm_context;
1723 struct smu_13_0_dpm_table *gfx_table =
1724 &dpm_context->dpm_tables.gfx_table;
1725 struct smu_13_0_dpm_table *mem_table =
1726 &dpm_context->dpm_tables.uclk_table;
1727 struct smu_13_0_dpm_table *soc_table =
1728 &dpm_context->dpm_tables.soc_table;
1729 struct smu_13_0_dpm_table *vclk_table =
1730 &dpm_context->dpm_tables.vclk_table;
1731 struct smu_13_0_dpm_table *dclk_table =
1732 &dpm_context->dpm_tables.dclk_table;
1733 struct smu_13_0_dpm_table *fclk_table =
1734 &dpm_context->dpm_tables.fclk_table;
1735 struct smu_umd_pstate_table *pstate_table =
1736 &smu->pstate_table;
1737 struct amdgpu_device *adev = smu->adev;
1738 uint32_t sclk_min = 0, sclk_max = 0;
1739 uint32_t mclk_min = 0, mclk_max = 0;
1740 uint32_t socclk_min = 0, socclk_max = 0;
1741 uint32_t vclk_min = 0, vclk_max = 0;
1742 uint32_t dclk_min = 0, dclk_max = 0;
1743 uint32_t fclk_min = 0, fclk_max = 0;
1744 int ret = 0, i;
1745
1746 switch (level) {
1747 case AMD_DPM_FORCED_LEVEL_HIGH:
1748 sclk_min = sclk_max = gfx_table->max;
1749 mclk_min = mclk_max = mem_table->max;
1750 socclk_min = socclk_max = soc_table->max;
1751 vclk_min = vclk_max = vclk_table->max;
1752 dclk_min = dclk_max = dclk_table->max;
1753 fclk_min = fclk_max = fclk_table->max;
1754 break;
1755 case AMD_DPM_FORCED_LEVEL_LOW:
1756 sclk_min = sclk_max = gfx_table->min;
1757 mclk_min = mclk_max = mem_table->min;
1758 socclk_min = socclk_max = soc_table->min;
1759 vclk_min = vclk_max = vclk_table->min;
1760 dclk_min = dclk_max = dclk_table->min;
1761 fclk_min = fclk_max = fclk_table->min;
1762 break;
1763 case AMD_DPM_FORCED_LEVEL_AUTO:
1764 sclk_min = gfx_table->min;
1765 sclk_max = gfx_table->max;
1766 mclk_min = mem_table->min;
1767 mclk_max = mem_table->max;
1768 socclk_min = soc_table->min;
1769 socclk_max = soc_table->max;
1770 vclk_min = vclk_table->min;
1771 vclk_max = vclk_table->max;
1772 dclk_min = dclk_table->min;
1773 dclk_max = dclk_table->max;
1774 fclk_min = fclk_table->min;
1775 fclk_max = fclk_table->max;
1776 break;
1777 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1778 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1779 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1780 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1781 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1782 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1783 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1784 break;
1785 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1786 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1787 break;
1788 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1789 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1790 break;
1791 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1792 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1793 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1794 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1795 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1796 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1797 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1798 break;
1799 case AMD_DPM_FORCED_LEVEL_MANUAL:
1800 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1801 return 0;
1802 default:
1803 dev_err(adev->dev, "Invalid performance level %d\n", level);
1804 return -EINVAL;
1805 }
1806
1807 /*
1808 * Unset those settings for SMU 13.0.2. As soft limits settings
1809 * for those clock domains are not supported.
1810 */
1811 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1812 mclk_min = mclk_max = 0;
1813 socclk_min = socclk_max = 0;
1814 vclk_min = vclk_max = 0;
1815 dclk_min = dclk_max = 0;
1816 fclk_min = fclk_max = 0;
1817 }
1818
1819 if (sclk_min && sclk_max) {
1820 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1821 SMU_GFXCLK,
1822 sclk_min,
1823 sclk_max);
1824 if (ret)
1825 return ret;
1826
1827 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1828 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1829 }
1830
1831 if (mclk_min && mclk_max) {
1832 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1833 SMU_MCLK,
1834 mclk_min,
1835 mclk_max);
1836 if (ret)
1837 return ret;
1838
1839 pstate_table->uclk_pstate.curr.min = mclk_min;
1840 pstate_table->uclk_pstate.curr.max = mclk_max;
1841 }
1842
1843 if (socclk_min && socclk_max) {
1844 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1845 SMU_SOCCLK,
1846 socclk_min,
1847 socclk_max);
1848 if (ret)
1849 return ret;
1850
1851 pstate_table->socclk_pstate.curr.min = socclk_min;
1852 pstate_table->socclk_pstate.curr.max = socclk_max;
1853 }
1854
1855 if (vclk_min && vclk_max) {
1856 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1857 if (adev->vcn.harvest_config & (1 << i))
1858 continue;
1859 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1860 i ? SMU_VCLK1 : SMU_VCLK,
1861 vclk_min,
1862 vclk_max);
1863 if (ret)
1864 return ret;
1865 }
1866 pstate_table->vclk_pstate.curr.min = vclk_min;
1867 pstate_table->vclk_pstate.curr.max = vclk_max;
1868 }
1869
1870 if (dclk_min && dclk_max) {
1871 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1872 if (adev->vcn.harvest_config & (1 << i))
1873 continue;
1874 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1875 i ? SMU_DCLK1 : SMU_DCLK,
1876 dclk_min,
1877 dclk_max);
1878 if (ret)
1879 return ret;
1880 }
1881 pstate_table->dclk_pstate.curr.min = dclk_min;
1882 pstate_table->dclk_pstate.curr.max = dclk_max;
1883 }
1884
1885 if (fclk_min && fclk_max) {
1886 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1887 SMU_FCLK,
1888 fclk_min,
1889 fclk_max);
1890 if (ret)
1891 return ret;
1892
1893 pstate_table->fclk_pstate.curr.min = fclk_min;
1894 pstate_table->fclk_pstate.curr.max = fclk_max;
1895 }
1896
1897 return ret;
1898 }
1899
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1900 int smu_v13_0_set_power_source(struct smu_context *smu,
1901 enum smu_power_src_type power_src)
1902 {
1903 int pwr_source;
1904
1905 pwr_source = smu_cmn_to_asic_specific_index(smu,
1906 CMN2ASIC_MAPPING_PWR,
1907 (uint32_t)power_src);
1908 if (pwr_source < 0)
1909 return -EINVAL;
1910
1911 return smu_cmn_send_smc_msg_with_param(smu,
1912 SMU_MSG_NotifyPowerSource,
1913 pwr_source,
1914 NULL);
1915 }
1916
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1917 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1918 enum smu_clk_type clk_type,
1919 uint16_t level,
1920 uint32_t *value)
1921 {
1922 int ret = 0, clk_id = 0;
1923 uint32_t param;
1924
1925 if (!value)
1926 return -EINVAL;
1927
1928 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1929 return 0;
1930
1931 clk_id = smu_cmn_to_asic_specific_index(smu,
1932 CMN2ASIC_MAPPING_CLK,
1933 clk_type);
1934 if (clk_id < 0)
1935 return clk_id;
1936
1937 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1938
1939 ret = smu_cmn_send_smc_msg_with_param(smu,
1940 SMU_MSG_GetDpmFreqByIndex,
1941 param,
1942 value);
1943 if (ret)
1944 return ret;
1945
1946 *value = *value & 0x7fffffff;
1947
1948 return ret;
1949 }
1950
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1951 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1952 enum smu_clk_type clk_type,
1953 uint32_t *value)
1954 {
1955 int ret;
1956
1957 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1958 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1959 if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1960 ++(*value);
1961
1962 return ret;
1963 }
1964
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1965 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1966 enum smu_clk_type clk_type,
1967 bool *is_fine_grained_dpm)
1968 {
1969 int ret = 0, clk_id = 0;
1970 uint32_t param;
1971 uint32_t value;
1972
1973 if (!is_fine_grained_dpm)
1974 return -EINVAL;
1975
1976 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1977 return 0;
1978
1979 clk_id = smu_cmn_to_asic_specific_index(smu,
1980 CMN2ASIC_MAPPING_CLK,
1981 clk_type);
1982 if (clk_id < 0)
1983 return clk_id;
1984
1985 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1986
1987 ret = smu_cmn_send_smc_msg_with_param(smu,
1988 SMU_MSG_GetDpmFreqByIndex,
1989 param,
1990 &value);
1991 if (ret)
1992 return ret;
1993
1994 /*
1995 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1996 * now, we un-support it
1997 */
1998 *is_fine_grained_dpm = value & 0x80000000;
1999
2000 return 0;
2001 }
2002
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)2003 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2004 enum smu_clk_type clk_type,
2005 struct smu_13_0_dpm_table *single_dpm_table)
2006 {
2007 int ret = 0;
2008 uint32_t clk;
2009 int i;
2010
2011 ret = smu_v13_0_get_dpm_level_count(smu,
2012 clk_type,
2013 &single_dpm_table->count);
2014 if (ret) {
2015 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2016 return ret;
2017 }
2018
2019 if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
2020 ret = smu_v13_0_get_fine_grained_status(smu,
2021 clk_type,
2022 &single_dpm_table->is_fine_grained);
2023 if (ret) {
2024 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2025 return ret;
2026 }
2027 }
2028
2029 for (i = 0; i < single_dpm_table->count; i++) {
2030 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2031 clk_type,
2032 i,
2033 &clk);
2034 if (ret) {
2035 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2036 return ret;
2037 }
2038
2039 single_dpm_table->dpm_levels[i].value = clk;
2040 single_dpm_table->dpm_levels[i].enabled = true;
2041
2042 if (i == 0)
2043 single_dpm_table->min = clk;
2044 else if (i == single_dpm_table->count - 1)
2045 single_dpm_table->max = clk;
2046 }
2047
2048 return 0;
2049 }
2050
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)2051 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2052 {
2053 struct amdgpu_device *adev = smu->adev;
2054
2055 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2056 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2057 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2058 }
2059
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)2060 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2061 {
2062 uint32_t width_level;
2063
2064 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2065 if (width_level > LINK_WIDTH_MAX)
2066 width_level = 0;
2067
2068 return link_width[width_level];
2069 }
2070
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)2071 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2072 {
2073 struct amdgpu_device *adev = smu->adev;
2074
2075 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2076 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2077 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2078 }
2079
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)2080 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2081 {
2082 uint32_t speed_level;
2083
2084 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2085 if (speed_level > LINK_SPEED_MAX)
2086 speed_level = 0;
2087
2088 return link_speed[speed_level];
2089 }
2090
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable)2091 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2092 bool enable)
2093 {
2094 struct amdgpu_device *adev = smu->adev;
2095 int i, ret = 0;
2096
2097 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2098 if (adev->vcn.harvest_config & (1 << i))
2099 continue;
2100
2101 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2102 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2103 i << 16U, NULL);
2104 if (ret)
2105 return ret;
2106 }
2107
2108 return ret;
2109 }
2110
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2111 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2112 bool enable)
2113 {
2114 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2115 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2116 0, NULL);
2117 }
2118
smu_v13_0_run_btc(struct smu_context * smu)2119 int smu_v13_0_run_btc(struct smu_context *smu)
2120 {
2121 int res;
2122
2123 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2124 if (res)
2125 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2126
2127 return res;
2128 }
2129
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2130 int smu_v13_0_gpo_control(struct smu_context *smu,
2131 bool enablement)
2132 {
2133 int res;
2134
2135 res = smu_cmn_send_smc_msg_with_param(smu,
2136 SMU_MSG_AllowGpo,
2137 enablement ? 1 : 0,
2138 NULL);
2139 if (res)
2140 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2141
2142 return res;
2143 }
2144
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2145 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2146 bool enablement)
2147 {
2148 struct amdgpu_device *adev = smu->adev;
2149 int ret = 0;
2150
2151 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2152 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2153 if (ret) {
2154 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2155 return ret;
2156 }
2157 }
2158
2159 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2160 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2161 if (ret) {
2162 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2163 return ret;
2164 }
2165 }
2166
2167 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2168 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2169 if (ret) {
2170 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2171 return ret;
2172 }
2173 }
2174
2175 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2176 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2177 if (ret) {
2178 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2179 return ret;
2180 }
2181 }
2182
2183 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2184 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2185 if (ret) {
2186 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2187 return ret;
2188 }
2189 }
2190
2191 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2192 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2193 if (ret) {
2194 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2195 return ret;
2196 }
2197 }
2198
2199 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2200 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2201 if (ret) {
2202 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2203 return ret;
2204 }
2205 }
2206
2207 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2208 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2209 if (ret) {
2210 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2211 return ret;
2212 }
2213 }
2214
2215 return ret;
2216 }
2217
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2218 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2219 bool enablement)
2220 {
2221 int ret = 0;
2222
2223 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2224 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2225
2226 return ret;
2227 }
2228
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2229 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2230 enum smu_baco_seq baco_seq)
2231 {
2232 struct smu_baco_context *smu_baco = &smu->smu_baco;
2233 int ret;
2234
2235 ret = smu_cmn_send_smc_msg_with_param(smu,
2236 SMU_MSG_ArmD3,
2237 baco_seq,
2238 NULL);
2239 if (ret)
2240 return ret;
2241
2242 if (baco_seq == BACO_SEQ_BAMACO ||
2243 baco_seq == BACO_SEQ_BACO)
2244 smu_baco->state = SMU_BACO_STATE_ENTER;
2245 else
2246 smu_baco->state = SMU_BACO_STATE_EXIT;
2247
2248 return 0;
2249 }
2250
smu_v13_0_baco_is_support(struct smu_context * smu)2251 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2252 {
2253 struct smu_baco_context *smu_baco = &smu->smu_baco;
2254
2255 if (amdgpu_sriov_vf(smu->adev) ||
2256 !smu_baco->platform_support)
2257 return false;
2258
2259 /* return true if ASIC is in BACO state already */
2260 if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2261 return true;
2262
2263 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2264 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2265 return false;
2266
2267 return true;
2268 }
2269
smu_v13_0_baco_get_state(struct smu_context * smu)2270 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2271 {
2272 struct smu_baco_context *smu_baco = &smu->smu_baco;
2273
2274 return smu_baco->state;
2275 }
2276
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2277 int smu_v13_0_baco_set_state(struct smu_context *smu,
2278 enum smu_baco_state state)
2279 {
2280 struct smu_baco_context *smu_baco = &smu->smu_baco;
2281 struct amdgpu_device *adev = smu->adev;
2282 int ret = 0;
2283
2284 if (smu_v13_0_baco_get_state(smu) == state)
2285 return 0;
2286
2287 if (state == SMU_BACO_STATE_ENTER) {
2288 ret = smu_cmn_send_smc_msg_with_param(smu,
2289 SMU_MSG_EnterBaco,
2290 smu_baco->maco_support ?
2291 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2292 NULL);
2293 } else {
2294 ret = smu_cmn_send_smc_msg(smu,
2295 SMU_MSG_ExitBaco,
2296 NULL);
2297 if (ret)
2298 return ret;
2299
2300 /* clear vbios scratch 6 and 7 for coming asic reinit */
2301 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2302 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2303 }
2304
2305 if (!ret)
2306 smu_baco->state = state;
2307
2308 return ret;
2309 }
2310
smu_v13_0_baco_enter(struct smu_context * smu)2311 int smu_v13_0_baco_enter(struct smu_context *smu)
2312 {
2313 int ret = 0;
2314
2315 ret = smu_v13_0_baco_set_state(smu,
2316 SMU_BACO_STATE_ENTER);
2317 if (ret)
2318 return ret;
2319
2320 msleep(10);
2321
2322 return ret;
2323 }
2324
smu_v13_0_baco_exit(struct smu_context * smu)2325 int smu_v13_0_baco_exit(struct smu_context *smu)
2326 {
2327 return smu_v13_0_baco_set_state(smu,
2328 SMU_BACO_STATE_EXIT);
2329 }
2330
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2331 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2332 {
2333 uint16_t index;
2334
2335 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2336 SMU_MSG_EnableGfxImu);
2337 /* Param 1 to tell PMFW to enable GFXOFF feature */
2338 return smu_cmn_send_msg_without_waiting(smu, index, 1);
2339 }
2340
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2341 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2342 enum PP_OD_DPM_TABLE_COMMAND type,
2343 long input[], uint32_t size)
2344 {
2345 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2346 int ret = 0;
2347
2348 /* Only allowed in manual mode */
2349 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2350 return -EINVAL;
2351
2352 switch (type) {
2353 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2354 if (size != 2) {
2355 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2356 return -EINVAL;
2357 }
2358
2359 if (input[0] == 0) {
2360 if (input[1] < smu->gfx_default_hard_min_freq) {
2361 dev_warn(smu->adev->dev,
2362 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2363 input[1], smu->gfx_default_hard_min_freq);
2364 return -EINVAL;
2365 }
2366 smu->gfx_actual_hard_min_freq = input[1];
2367 } else if (input[0] == 1) {
2368 if (input[1] > smu->gfx_default_soft_max_freq) {
2369 dev_warn(smu->adev->dev,
2370 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2371 input[1], smu->gfx_default_soft_max_freq);
2372 return -EINVAL;
2373 }
2374 smu->gfx_actual_soft_max_freq = input[1];
2375 } else {
2376 return -EINVAL;
2377 }
2378 break;
2379 case PP_OD_RESTORE_DEFAULT_TABLE:
2380 if (size != 0) {
2381 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2382 return -EINVAL;
2383 }
2384 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2385 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2386 break;
2387 case PP_OD_COMMIT_DPM_TABLE:
2388 if (size != 0) {
2389 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2390 return -EINVAL;
2391 }
2392 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2393 dev_err(smu->adev->dev,
2394 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2395 smu->gfx_actual_hard_min_freq,
2396 smu->gfx_actual_soft_max_freq);
2397 return -EINVAL;
2398 }
2399
2400 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2401 smu->gfx_actual_hard_min_freq,
2402 NULL);
2403 if (ret) {
2404 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2405 return ret;
2406 }
2407
2408 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2409 smu->gfx_actual_soft_max_freq,
2410 NULL);
2411 if (ret) {
2412 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2413 return ret;
2414 }
2415 break;
2416 default:
2417 return -ENOSYS;
2418 }
2419
2420 return ret;
2421 }
2422
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2423 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2424 {
2425 struct smu_table_context *smu_table = &smu->smu_table;
2426
2427 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2428 smu_table->clocks_table, false);
2429 }
2430
smu_v13_0_set_smu_mailbox_registers(struct smu_context * smu)2431 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2432 {
2433 struct amdgpu_device *adev = smu->adev;
2434
2435 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2436 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2437 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2438 }
2439
smu_v13_0_mode1_reset(struct smu_context * smu)2440 int smu_v13_0_mode1_reset(struct smu_context *smu)
2441 {
2442 int ret = 0;
2443
2444 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2445 if (!ret)
2446 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2447
2448 return ret;
2449 }
2450