1 /*
2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch.h>
8 #include <arch_helpers.h>
9 #include <platform_def.h>
10 #include <plat/common/platform.h>
11 
12 #include "socfpga_private.h"
13 
14 
plat_get_syscnt_freq2(void)15 unsigned int plat_get_syscnt_freq2(void)
16 {
17 	return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
18 }
19 
socfpga_get_ns_image_entrypoint(void)20 unsigned long socfpga_get_ns_image_entrypoint(void)
21 {
22 	return PLAT_NS_IMAGE_OFFSET;
23 }
24 
25 /******************************************************************************
26  * Gets SPSR for BL32 entry
27  *****************************************************************************/
socfpga_get_spsr_for_bl32_entry(void)28 uint32_t socfpga_get_spsr_for_bl32_entry(void)
29 {
30 	/*
31 	 * The Secure Payload Dispatcher service is responsible for
32 	 * setting the SPSR prior to entry into the BL32 image.
33 	 */
34 	return 0;
35 }
36 
37 /******************************************************************************
38  * Gets SPSR for BL33 entry
39  *****************************************************************************/
socfpga_get_spsr_for_bl33_entry(void)40 uint32_t socfpga_get_spsr_for_bl33_entry(void)
41 {
42 	unsigned long el_status;
43 	unsigned int mode;
44 	uint32_t spsr;
45 
46 	/* Figure out what mode we enter the non-secure world in */
47 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
48 	el_status &= ID_AA64PFR0_ELX_MASK;
49 
50 	mode = (el_status) ? MODE_EL2 : MODE_EL1;
51 
52 	/*
53 	 * TODO: Consider the possibility of specifying the SPSR in
54 	 * the FIP ToC and allowing the platform to have a say as
55 	 * well.
56 	 */
57 	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
58 	return spsr;
59 }
60 
61