1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 */
6
7 #ifndef __SPARX5_MAIN_H__
8 #define __SPARX5_MAIN_H__
9
10 #include <linux/types.h>
11 #include <linux/phy/phy.h>
12 #include <linux/netdevice.h>
13 #include <linux/phy.h>
14 #include <linux/if_vlan.h>
15 #include <linux/bitmap.h>
16 #include <linux/phylink.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/ptp_clock_kernel.h>
19 #include <linux/hrtimer.h>
20 #include <linux/debugfs.h>
21
22 #include "sparx5_main_regs.h"
23
24 /* Target chip type */
25 enum spx5_target_chiptype {
26 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
27 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
28 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
29 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
30 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
31 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
32 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
33 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
34 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */
35 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */
36 };
37
38 enum sparx5_port_max_tags {
39 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */
40 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */
41 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */
42 };
43
44 enum sparx5_vlan_port_type {
45 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */
46 SPX5_VLAN_PORT_TYPE_C, /* C-port */
47 SPX5_VLAN_PORT_TYPE_S, /* S-port */
48 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */
49 };
50
51 #define SPX5_PORTS 65
52 #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */
53 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */
54 #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */
55 #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */
56 #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */
57 #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/
58 #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */
59
60 #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */
61 #define PGID_UC_FLOOD (PGID_BASE + 0)
62 #define PGID_MC_FLOOD (PGID_BASE + 1)
63 #define PGID_IPV4_MC_DATA (PGID_BASE + 2)
64 #define PGID_IPV4_MC_CTRL (PGID_BASE + 3)
65 #define PGID_IPV6_MC_DATA (PGID_BASE + 4)
66 #define PGID_IPV6_MC_CTRL (PGID_BASE + 5)
67 #define PGID_BCAST (PGID_BASE + 6)
68 #define PGID_CPU (PGID_BASE + 7)
69 #define PGID_MCAST_START (PGID_BASE + 8)
70
71 #define PGID_TABLE_SIZE 3290
72
73 #define IFH_LEN 9 /* 36 bytes */
74 #define NULL_VID 0
75 #define SPX5_MACT_PULL_DELAY (2 * HZ)
76 #define SPX5_STATS_CHECK_DELAY (1 * HZ)
77 #define SPX5_PRIOS 8 /* Number of priority queues */
78 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */
79 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */
80
81 #define XTR_QUEUE 0
82 #define INJ_QUEUE 0
83
84 #define FDMA_DCB_MAX 64
85 #define FDMA_RX_DCB_MAX_DBS 15
86 #define FDMA_TX_DCB_MAX_DBS 1
87
88 #define SPARX5_PHC_COUNT 3
89 #define SPARX5_PHC_PORT 0
90
91 #define IFH_REW_OP_NOOP 0x0
92 #define IFH_REW_OP_ONE_STEP_PTP 0x3
93 #define IFH_REW_OP_TWO_STEP_PTP 0x4
94
95 #define IFH_PDU_TYPE_NONE 0x0
96 #define IFH_PDU_TYPE_PTP 0x5
97 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6
98 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7
99
100 struct sparx5;
101
102 struct sparx5_db_hw {
103 u64 dataptr;
104 u64 status;
105 };
106
107 struct sparx5_rx_dcb_hw {
108 u64 nextptr;
109 u64 info;
110 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS];
111 };
112
113 struct sparx5_tx_dcb_hw {
114 u64 nextptr;
115 u64 info;
116 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS];
117 };
118
119 /* Frame DMA receive state:
120 * For each DB, there is a SKB, and the skb data pointer is mapped in
121 * the DB. Once a frame is received the skb is given to the upper layers
122 * and a new skb is added to the dcb.
123 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused.
124 */
125 struct sparx5_rx {
126 struct sparx5_rx_dcb_hw *dcb_entries;
127 struct sparx5_rx_dcb_hw *last_entry;
128 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS];
129 int db_index;
130 int dcb_index;
131 dma_addr_t dma;
132 struct napi_struct napi;
133 u32 channel_id;
134 struct net_device *ndev;
135 u64 packets;
136 };
137
138 /* Frame DMA transmit state:
139 * DCBs are chained using the DCBs nextptr field.
140 */
141 struct sparx5_tx {
142 struct sparx5_tx_dcb_hw *curr_entry;
143 struct sparx5_tx_dcb_hw *first_entry;
144 struct list_head db_list;
145 dma_addr_t dma;
146 u32 channel_id;
147 u64 packets;
148 u64 dropped;
149 };
150
151 struct sparx5_port_config {
152 phy_interface_t portmode;
153 u32 bandwidth;
154 int speed;
155 int duplex;
156 enum phy_media media;
157 bool inband;
158 bool power_down;
159 bool autoneg;
160 bool serdes_reset;
161 u32 pause;
162 u32 pause_adv;
163 phy_interface_t phy_mode;
164 u32 sd_sgpio;
165 };
166
167 struct sparx5_port {
168 struct net_device *ndev;
169 struct sparx5 *sparx5;
170 struct device_node *of_node;
171 struct phy *serdes;
172 struct sparx5_port_config conf;
173 struct phylink_config phylink_config;
174 struct phylink *phylink;
175 struct phylink_pcs phylink_pcs;
176 u16 portno;
177 /* Ingress default VLAN (pvid) */
178 u16 pvid;
179 /* Egress default VLAN (vid) */
180 u16 vid;
181 bool signd_internal;
182 bool signd_active_high;
183 bool signd_enable;
184 bool flow_control;
185 enum sparx5_port_max_tags max_vlan_tags;
186 enum sparx5_vlan_port_type vlan_type;
187 u32 custom_etype;
188 bool vlan_aware;
189 struct hrtimer inj_timer;
190 /* ptp */
191 u8 ptp_cmd;
192 u16 ts_id;
193 struct sk_buff_head tx_skbs;
194 bool is_mrouter;
195 };
196
197 enum sparx5_core_clockfreq {
198 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */
199 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */
200 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */
201 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */
202 };
203
204 struct sparx5_phc {
205 struct ptp_clock *clock;
206 struct ptp_clock_info info;
207 struct hwtstamp_config hwtstamp_config;
208 struct sparx5 *sparx5;
209 u8 index;
210 };
211
212 struct sparx5_skb_cb {
213 u8 rew_op;
214 u8 pdu_type;
215 u8 pdu_w16_offset;
216 u16 ts_id;
217 unsigned long jiffies;
218 };
219
220 struct sparx5_mdb_entry {
221 struct list_head list;
222 DECLARE_BITMAP(port_mask, SPX5_PORTS);
223 unsigned char addr[ETH_ALEN];
224 bool cpu_copy;
225 u16 vid;
226 u16 pgid_idx;
227 };
228
229 #define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10)
230 #define SPARX5_SKB_CB(skb) \
231 ((struct sparx5_skb_cb *)((skb)->cb))
232
233 struct sparx5 {
234 struct platform_device *pdev;
235 struct device *dev;
236 u32 chip_id;
237 enum spx5_target_chiptype target_ct;
238 void __iomem *regs[NUM_TARGETS];
239 int port_count;
240 struct mutex lock; /* MAC reg lock */
241 /* port structures are in net device */
242 struct sparx5_port *ports[SPX5_PORTS];
243 enum sparx5_core_clockfreq coreclock;
244 /* Statistics */
245 u32 num_stats;
246 u32 num_ethtool_stats;
247 const char * const *stats_layout;
248 u64 *stats;
249 /* Workqueue for reading stats */
250 struct mutex queue_stats_lock;
251 struct delayed_work stats_work;
252 struct workqueue_struct *stats_queue;
253 /* Notifiers */
254 struct notifier_block netdevice_nb;
255 struct notifier_block switchdev_nb;
256 struct notifier_block switchdev_blocking_nb;
257 /* Switch state */
258 u8 base_mac[ETH_ALEN];
259 /* Associated bridge device (when bridged) */
260 struct net_device *hw_bridge_dev;
261 /* Bridged interfaces */
262 DECLARE_BITMAP(bridge_mask, SPX5_PORTS);
263 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
264 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
265 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
266 /* SW MAC table */
267 struct list_head mact_entries;
268 /* mac table list (mact_entries) mutex */
269 struct mutex mact_lock;
270 /* SW MDB table */
271 struct list_head mdb_entries;
272 /* mdb list mutex */
273 struct mutex mdb_lock;
274 struct delayed_work mact_work;
275 struct workqueue_struct *mact_queue;
276 /* Board specifics */
277 bool sd_sgpio_remapping;
278 /* Register based inj/xtr */
279 int xtr_irq;
280 /* Frame DMA */
281 int fdma_irq;
282 struct sparx5_rx rx;
283 struct sparx5_tx tx;
284 /* PTP */
285 bool ptp;
286 struct sparx5_phc phc[SPARX5_PHC_COUNT];
287 spinlock_t ptp_clock_lock; /* lock for phc */
288 spinlock_t ptp_ts_id_lock; /* lock for ts_id */
289 struct mutex ptp_lock; /* lock for ptp interface state */
290 u16 ptp_skbs;
291 int ptp_irq;
292 /* VCAP */
293 struct vcap_control *vcap_ctrl;
294 /* PGID allocation map */
295 u8 pgid_map[PGID_TABLE_SIZE];
296 /* Common root for debugfs */
297 struct dentry *debugfs_root;
298 };
299
300 /* sparx5_switchdev.c */
301 int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
302 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
303
304 /* sparx5_packet.c */
305 struct frame_info {
306 int src_port;
307 u32 timestamp;
308 };
309
310 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
311 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info);
312 irqreturn_t sparx5_xtr_handler(int irq, void *_priv);
313 netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev);
314 int sparx5_manual_injection_mode(struct sparx5 *sparx5);
315 void sparx5_port_inj_timer_setup(struct sparx5_port *port);
316
317 /* sparx5_fdma.c */
318 int sparx5_fdma_start(struct sparx5 *sparx5);
319 int sparx5_fdma_stop(struct sparx5 *sparx5);
320 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb);
321 irqreturn_t sparx5_fdma_handler(int irq, void *args);
322
323 /* sparx5_mactable.c */
324 void sparx5_mact_pull_work(struct work_struct *work);
325 int sparx5_mact_learn(struct sparx5 *sparx5, int port,
326 const unsigned char mac[ETH_ALEN], u16 vid);
327 bool sparx5_mact_getnext(struct sparx5 *sparx5,
328 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2);
329 int sparx5_mact_find(struct sparx5 *sparx5,
330 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2);
331 int sparx5_mact_forget(struct sparx5 *sparx5,
332 const unsigned char mac[ETH_ALEN], u16 vid);
333 int sparx5_add_mact_entry(struct sparx5 *sparx5,
334 struct net_device *dev,
335 u16 portno,
336 const unsigned char *addr, u16 vid);
337 int sparx5_del_mact_entry(struct sparx5 *sparx5,
338 const unsigned char *addr,
339 u16 vid);
340 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr);
341 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr);
342 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs);
343 void sparx5_mact_init(struct sparx5 *sparx5);
344
345 /* sparx5_vlan.c */
346 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable);
347 void sparx5_pgid_clear(struct sparx5 *spx5, int pgid);
348 void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]);
349 void sparx5_update_fwd(struct sparx5 *sparx5);
350 void sparx5_vlan_init(struct sparx5 *sparx5);
351 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno);
352 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
353 bool untagged);
354 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid);
355 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port);
356
357 /* sparx5_calendar.c */
358 int sparx5_config_auto_calendar(struct sparx5 *sparx5);
359 int sparx5_config_dsm_calendar(struct sparx5 *sparx5);
360
361 /* sparx5_ethtool.c */
362 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
363 int sparx_stats_init(struct sparx5 *sparx5);
364
365 /* sparx5_dcb.c */
366 #ifdef CONFIG_SPARX5_DCB
367 int sparx5_dcb_init(struct sparx5 *sparx5);
368 #else
sparx5_dcb_init(struct sparx5 * sparx5)369 static inline int sparx5_dcb_init(struct sparx5 *sparx5)
370 {
371 return 0;
372 }
373 #endif
374
375 /* sparx5_netdev.c */
376 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp);
377 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op);
378 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type);
379 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset);
380 void sparx5_set_port_ifh(void *ifh_hdr, u16 portno);
381 bool sparx5_netdevice_check(const struct net_device *dev);
382 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
383 int sparx5_register_netdevs(struct sparx5 *sparx5);
384 void sparx5_destroy_netdevs(struct sparx5 *sparx5);
385 void sparx5_unregister_netdevs(struct sparx5 *sparx5);
386
387 /* sparx5_ptp.c */
388 int sparx5_ptp_init(struct sparx5 *sparx5);
389 void sparx5_ptp_deinit(struct sparx5 *sparx5);
390 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr);
391 int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr);
392 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb,
393 u64 timestamp);
394 int sparx5_ptp_txtstamp_request(struct sparx5_port *port,
395 struct sk_buff *skb);
396 void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
397 struct sk_buff *skb);
398 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args);
399 int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
400
401 /* sparx5_vcap_impl.c */
402 int sparx5_vcap_init(struct sparx5 *sparx5);
403 void sparx5_vcap_destroy(struct sparx5 *sparx5);
404
405 /* sparx5_pgid.c */
406 enum sparx5_pgid_type {
407 SPX5_PGID_FREE,
408 SPX5_PGID_RESERVED,
409 SPX5_PGID_MULTICAST,
410 };
411
412 void sparx5_pgid_init(struct sparx5 *spx5);
413 int sparx5_pgid_alloc_glag(struct sparx5 *spx5, u16 *idx);
414 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx);
415 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx);
416
417 /* sparx5_pool.c */
418 struct sparx5_pool_entry {
419 u16 ref_cnt;
420 u32 idx; /* tc index */
421 };
422
423 u32 sparx5_pool_idx_to_id(u32 idx);
424 int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id);
425 int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id);
426 int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx,
427 u32 *id);
428
429 /* sparx5_sdlb.c */
430 #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF
431 #define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1)
432 #define SPX5_SDLB_GROUP_RATE_MAX 25000000000ULL
433 #define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET 13
434 #define SPX5_SDLB_CNT 4096
435 #define SPX5_SDLB_GROUP_CNT 10
436 #define SPX5_CLK_PER_100PS_DEFAULT 16
437
438 struct sparx5_sdlb_group {
439 u64 max_rate;
440 u32 min_burst;
441 u32 frame_size;
442 u32 pup_interval;
443 u32 nsets;
444 };
445
446 extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT];
447 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval,
448 u64 rate);
449
450 int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5);
451 int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst);
452 int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group);
453
454 int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx);
455 int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx);
456
457 void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst,
458 u32 frame_size, u32 idx);
459
460 /* sparx5_police.c */
461 enum {
462 /* More policer types will be added later */
463 SPX5_POL_SERVICE
464 };
465
466 struct sparx5_policer {
467 u32 type;
468 u32 idx;
469 u64 rate;
470 u32 burst;
471 u32 group;
472 u8 event_mask;
473 };
474
475 int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol);
476
477 /* sparx5_psfp.c */
478 #define SPX5_PSFP_GCE_CNT 4
479 #define SPX5_PSFP_SG_CNT 1024
480 #define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS (1 * NSEC_PER_USEC)
481 #define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS ((1 * NSEC_PER_SEC) - 1)
482 #define SPX5_PSFP_SG_MAX_IPV (SPX5_PRIOS - 1)
483 #define SPX5_PSFP_SG_OPEN (SPX5_PSFP_SG_CNT - 1)
484 #define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT 1000000
485 #define SPX5_PSFP_SF_MAX_SDU 16383
486
487 struct sparx5_psfp_fm {
488 struct sparx5_policer pol;
489 };
490
491 struct sparx5_psfp_gce {
492 bool gate_state; /* StreamGateState */
493 u32 interval; /* TimeInterval */
494 u32 ipv; /* InternalPriorityValue */
495 u32 maxoctets; /* IntervalOctetMax */
496 };
497
498 struct sparx5_psfp_sg {
499 bool gate_state; /* PSFPAdminGateStates */
500 bool gate_enabled; /* PSFPGateEnabled */
501 u32 ipv; /* PSFPAdminIPV */
502 struct timespec64 basetime; /* PSFPAdminBaseTime */
503 u32 cycletime; /* PSFPAdminCycleTime */
504 u32 cycletimeext; /* PSFPAdminCycleTimeExtension */
505 u32 num_entries; /* PSFPAdminControlListLength */
506 struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT];
507 };
508
509 struct sparx5_psfp_sf {
510 bool sblock_osize_ena;
511 bool sblock_osize;
512 u32 max_sdu;
513 u32 sgid; /* Gate id */
514 u32 fmid; /* Flow meter id */
515 };
516
517 int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx,
518 struct sparx5_psfp_fm *fm, u32 *id);
519 int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id);
520
521 int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx,
522 struct sparx5_psfp_sg *sg, u32 *id);
523 int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id);
524
525 int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf,
526 u32 *id);
527 int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id);
528
529 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx);
530 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx);
531 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid);
532 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid);
533
534 void sparx5_psfp_init(struct sparx5 *sparx5);
535
536 /* sparx5_qos.c */
537 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time,
538 const ktime_t org_base_time, ktime_t *new_base_time);
539
540 /* Clock period in picoseconds */
sparx5_clk_period(enum sparx5_core_clockfreq cclock)541 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
542 {
543 switch (cclock) {
544 case SPX5_CORE_CLOCK_250MHZ:
545 return 4000;
546 case SPX5_CORE_CLOCK_500MHZ:
547 return 2000;
548 case SPX5_CORE_CLOCK_625MHZ:
549 default:
550 return 1600;
551 }
552 }
553
sparx5_is_baser(phy_interface_t interface)554 static inline bool sparx5_is_baser(phy_interface_t interface)
555 {
556 return interface == PHY_INTERFACE_MODE_5GBASER ||
557 interface == PHY_INTERFACE_MODE_10GBASER ||
558 interface == PHY_INTERFACE_MODE_25GBASER;
559 }
560
561 extern const struct phylink_mac_ops sparx5_phylink_mac_ops;
562 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops;
563 extern const struct ethtool_ops sparx5_ethtool_ops;
564 extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops;
565
566 /* Calculate raw offset */
spx5_offset(int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)567 static inline __pure int spx5_offset(int id, int tinst, int tcnt,
568 int gbase, int ginst,
569 int gcnt, int gwidth,
570 int raddr, int rinst,
571 int rcnt, int rwidth)
572 {
573 WARN_ON((tinst) >= tcnt);
574 WARN_ON((ginst) >= gcnt);
575 WARN_ON((rinst) >= rcnt);
576 return gbase + ((ginst) * gwidth) +
577 raddr + ((rinst) * rwidth);
578 }
579
580 /* Read, Write and modify registers content.
581 * The register definition macros start at the id
582 */
spx5_addr(void __iomem * base[],int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)583 static inline void __iomem *spx5_addr(void __iomem *base[],
584 int id, int tinst, int tcnt,
585 int gbase, int ginst,
586 int gcnt, int gwidth,
587 int raddr, int rinst,
588 int rcnt, int rwidth)
589 {
590 WARN_ON((tinst) >= tcnt);
591 WARN_ON((ginst) >= gcnt);
592 WARN_ON((rinst) >= rcnt);
593 return base[id + (tinst)] +
594 gbase + ((ginst) * gwidth) +
595 raddr + ((rinst) * rwidth);
596 }
597
spx5_inst_addr(void __iomem * base,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)598 static inline void __iomem *spx5_inst_addr(void __iomem *base,
599 int gbase, int ginst,
600 int gcnt, int gwidth,
601 int raddr, int rinst,
602 int rcnt, int rwidth)
603 {
604 WARN_ON((ginst) >= gcnt);
605 WARN_ON((rinst) >= rcnt);
606 return base +
607 gbase + ((ginst) * gwidth) +
608 raddr + ((rinst) * rwidth);
609 }
610
spx5_rd(struct sparx5 * sparx5,int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)611 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt,
612 int gbase, int ginst, int gcnt, int gwidth,
613 int raddr, int rinst, int rcnt, int rwidth)
614 {
615 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
616 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
617 }
618
spx5_inst_rd(void __iomem * iomem,int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)619 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt,
620 int gbase, int ginst, int gcnt, int gwidth,
621 int raddr, int rinst, int rcnt, int rwidth)
622 {
623 return readl(spx5_inst_addr(iomem, gbase, ginst,
624 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
625 }
626
spx5_wr(u32 val,struct sparx5 * sparx5,int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)627 static inline void spx5_wr(u32 val, struct sparx5 *sparx5,
628 int id, int tinst, int tcnt,
629 int gbase, int ginst, int gcnt, int gwidth,
630 int raddr, int rinst, int rcnt, int rwidth)
631 {
632 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt,
633 gbase, ginst, gcnt, gwidth,
634 raddr, rinst, rcnt, rwidth));
635 }
636
spx5_inst_wr(u32 val,void __iomem * iomem,int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)637 static inline void spx5_inst_wr(u32 val, void __iomem *iomem,
638 int id, int tinst, int tcnt,
639 int gbase, int ginst, int gcnt, int gwidth,
640 int raddr, int rinst, int rcnt, int rwidth)
641 {
642 writel(val, spx5_inst_addr(iomem,
643 gbase, ginst, gcnt, gwidth,
644 raddr, rinst, rcnt, rwidth));
645 }
646
spx5_rmw(u32 val,u32 mask,struct sparx5 * sparx5,int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)647 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5,
648 int id, int tinst, int tcnt,
649 int gbase, int ginst, int gcnt, int gwidth,
650 int raddr, int rinst, int rcnt, int rwidth)
651 {
652 u32 nval;
653
654 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
655 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
656 nval = (nval & ~mask) | (val & mask);
657 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
658 gcnt, gwidth, raddr, rinst, rcnt, rwidth));
659 }
660
spx5_inst_rmw(u32 val,u32 mask,void __iomem * iomem,int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)661 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
662 int id, int tinst, int tcnt,
663 int gbase, int ginst, int gcnt, int gwidth,
664 int raddr, int rinst, int rcnt, int rwidth)
665 {
666 u32 nval;
667
668 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
669 rinst, rcnt, rwidth));
670 nval = (nval & ~mask) | (val & mask);
671 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
672 rinst, rcnt, rwidth));
673 }
674
spx5_inst_get(struct sparx5 * sparx5,int id,int tinst)675 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst)
676 {
677 return sparx5->regs[id + tinst];
678 }
679
spx5_reg_get(struct sparx5 * sparx5,int id,int tinst,int tcnt,int gbase,int ginst,int gcnt,int gwidth,int raddr,int rinst,int rcnt,int rwidth)680 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5,
681 int id, int tinst, int tcnt,
682 int gbase, int ginst, int gcnt, int gwidth,
683 int raddr, int rinst, int rcnt, int rwidth)
684 {
685 return spx5_addr(sparx5->regs, id, tinst, tcnt,
686 gbase, ginst, gcnt, gwidth,
687 raddr, rinst, rcnt, rwidth);
688 }
689
690 #endif /* __SPARX5_MAIN_H__ */
691