1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * STMicroelectronics st_lsm6dsx sensor driver
4 *
5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer
6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial
7 * interface standard output.
8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale
9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of
10 * +-125/+-245/+-500/+-1000/+-2000 dps
11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer
12 * allowing dynamic batching of sensor data.
13 * LSM9DSx series is similar but includes an additional magnetometer, handled
14 * by a different driver.
15 *
16 * Supported sensors:
17 * - LSM6DS3:
18 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416
19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
21 * - FIFO size: 8KB
22 *
23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C:
24 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416
25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
27 * - FIFO size: 4KB
28 *
29 * - LSM6DSO/LSM6DSOX/ASM330LHH/ASM330LHHX/LSM6DSR/ISM330DHCX/LSM6DST/LSM6DSOP/
30 * LSM6DSTX/LSM6DSO16IS/ISM330IS:
31 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416,
32 * 833
33 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
34 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
35 * - FIFO size: 3KB
36 *
37 * - LSM6DSV/LSM6DSV16X:
38 * - Accelerometer/Gyroscope supported ODR [Hz]: 7.5, 15, 30, 60, 120, 240,
39 * 480, 960
40 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
41 * - Gyroscope supported full-scale [dps]: +-125/+-250/+-500/+-1000/+-2000
42 * - FIFO size: 3KB
43 *
44 * - LSM9DS1/LSM6DS0:
45 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952
46 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
47 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952
48 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000
49 * - FIFO size: 32
50 *
51 * Copyright 2016 STMicroelectronics Inc.
52 *
53 * Lorenzo Bianconi <lorenzo.bianconi@st.com>
54 * Denis Ciocca <denis.ciocca@st.com>
55 */
56
57 #include <linux/kernel.h>
58 #include <linux/module.h>
59 #include <linux/delay.h>
60 #include <linux/iio/events.h>
61 #include <linux/iio/iio.h>
62 #include <linux/iio/sysfs.h>
63 #include <linux/iio/triggered_buffer.h>
64 #include <linux/iio/trigger_consumer.h>
65 #include <linux/interrupt.h>
66 #include <linux/irq.h>
67 #include <linux/minmax.h>
68 #include <linux/pm.h>
69 #include <linux/property.h>
70 #include <linux/regmap.h>
71 #include <linux/bitfield.h>
72
73 #include <linux/platform_data/st_sensors_pdata.h>
74
75 #include "st_lsm6dsx.h"
76
77 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
78
79 #define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */
80
81 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = {
82 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0),
83 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1),
84 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2),
85 IIO_CHAN_SOFT_TIMESTAMP(3),
86 };
87
88 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = {
89 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0),
90 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1),
91 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2),
92 IIO_CHAN_SOFT_TIMESTAMP(3),
93 };
94
95 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = {
96 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0),
97 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1),
98 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2),
99 IIO_CHAN_SOFT_TIMESTAMP(3),
100 };
101
102 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
103 {
104 .reset = {
105 .addr = 0x22,
106 .mask = BIT(0),
107 },
108 .boot = {
109 .addr = 0x22,
110 .mask = BIT(7),
111 },
112 .bdu = {
113 .addr = 0x22,
114 .mask = BIT(6),
115 },
116 .id = {
117 {
118 .hw_id = ST_LSM9DS1_ID,
119 .name = ST_LSM9DS1_DEV_NAME,
120 .wai = 0x68,
121 }, {
122 .hw_id = ST_LSM6DS0_ID,
123 .name = ST_LSM6DS0_DEV_NAME,
124 .wai = 0x68,
125 },
126 },
127 .channels = {
128 [ST_LSM6DSX_ID_ACC] = {
129 .chan = st_lsm6dsx_acc_channels,
130 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
131 },
132 [ST_LSM6DSX_ID_GYRO] = {
133 .chan = st_lsm6ds0_gyro_channels,
134 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels),
135 },
136 },
137 .odr_table = {
138 [ST_LSM6DSX_ID_ACC] = {
139 .reg = {
140 .addr = 0x20,
141 .mask = GENMASK(7, 5),
142 },
143 .odr_avl[0] = { 10000, 0x01 },
144 .odr_avl[1] = { 50000, 0x02 },
145 .odr_avl[2] = { 119000, 0x03 },
146 .odr_avl[3] = { 238000, 0x04 },
147 .odr_avl[4] = { 476000, 0x05 },
148 .odr_avl[5] = { 952000, 0x06 },
149 .odr_len = 6,
150 },
151 [ST_LSM6DSX_ID_GYRO] = {
152 .reg = {
153 .addr = 0x10,
154 .mask = GENMASK(7, 5),
155 },
156 .odr_avl[0] = { 14900, 0x01 },
157 .odr_avl[1] = { 59500, 0x02 },
158 .odr_avl[2] = { 119000, 0x03 },
159 .odr_avl[3] = { 238000, 0x04 },
160 .odr_avl[4] = { 476000, 0x05 },
161 .odr_avl[5] = { 952000, 0x06 },
162 .odr_len = 6,
163 },
164 },
165 .fs_table = {
166 [ST_LSM6DSX_ID_ACC] = {
167 .reg = {
168 .addr = 0x20,
169 .mask = GENMASK(4, 3),
170 },
171 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
172 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
173 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
174 .fs_avl[3] = { IIO_G_TO_M_S_2(732000), 0x1 },
175 .fs_len = 4,
176 },
177 [ST_LSM6DSX_ID_GYRO] = {
178 .reg = {
179 .addr = 0x10,
180 .mask = GENMASK(4, 3),
181 },
182
183 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
184 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
185 .fs_avl[2] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
186 .fs_len = 3,
187 },
188 },
189 .irq_config = {
190 .irq1 = {
191 .addr = 0x0c,
192 .mask = BIT(3),
193 },
194 .irq2 = {
195 .addr = 0x0d,
196 .mask = BIT(3),
197 },
198 .hla = {
199 .addr = 0x22,
200 .mask = BIT(5),
201 },
202 .od = {
203 .addr = 0x22,
204 .mask = BIT(4),
205 },
206 },
207 .fifo_ops = {
208 .max_size = 32,
209 },
210 },
211 {
212 .reset = {
213 .addr = 0x12,
214 .mask = BIT(0),
215 },
216 .boot = {
217 .addr = 0x12,
218 .mask = BIT(7),
219 },
220 .bdu = {
221 .addr = 0x12,
222 .mask = BIT(6),
223 },
224 .id = {
225 {
226 .hw_id = ST_LSM6DS3_ID,
227 .name = ST_LSM6DS3_DEV_NAME,
228 .wai = 0x69,
229 },
230 },
231 .channels = {
232 [ST_LSM6DSX_ID_ACC] = {
233 .chan = st_lsm6dsx_acc_channels,
234 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
235 },
236 [ST_LSM6DSX_ID_GYRO] = {
237 .chan = st_lsm6dsx_gyro_channels,
238 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
239 },
240 },
241 .odr_table = {
242 [ST_LSM6DSX_ID_ACC] = {
243 .reg = {
244 .addr = 0x10,
245 .mask = GENMASK(7, 4),
246 },
247 .odr_avl[0] = { 12500, 0x01 },
248 .odr_avl[1] = { 26000, 0x02 },
249 .odr_avl[2] = { 52000, 0x03 },
250 .odr_avl[3] = { 104000, 0x04 },
251 .odr_avl[4] = { 208000, 0x05 },
252 .odr_avl[5] = { 416000, 0x06 },
253 .odr_len = 6,
254 },
255 [ST_LSM6DSX_ID_GYRO] = {
256 .reg = {
257 .addr = 0x11,
258 .mask = GENMASK(7, 4),
259 },
260 .odr_avl[0] = { 12500, 0x01 },
261 .odr_avl[1] = { 26000, 0x02 },
262 .odr_avl[2] = { 52000, 0x03 },
263 .odr_avl[3] = { 104000, 0x04 },
264 .odr_avl[4] = { 208000, 0x05 },
265 .odr_avl[5] = { 416000, 0x06 },
266 .odr_len = 6,
267 },
268 },
269 .fs_table = {
270 [ST_LSM6DSX_ID_ACC] = {
271 .reg = {
272 .addr = 0x10,
273 .mask = GENMASK(3, 2),
274 },
275 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
276 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
277 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
278 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
279 .fs_len = 4,
280 },
281 [ST_LSM6DSX_ID_GYRO] = {
282 .reg = {
283 .addr = 0x11,
284 .mask = GENMASK(3, 2),
285 },
286 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
287 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
288 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
289 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
290 .fs_len = 4,
291 },
292 },
293 .irq_config = {
294 .irq1 = {
295 .addr = 0x0d,
296 .mask = BIT(3),
297 },
298 .irq2 = {
299 .addr = 0x0e,
300 .mask = BIT(3),
301 },
302 .lir = {
303 .addr = 0x58,
304 .mask = BIT(0),
305 },
306 .irq1_func = {
307 .addr = 0x5e,
308 .mask = BIT(5),
309 },
310 .irq2_func = {
311 .addr = 0x5f,
312 .mask = BIT(5),
313 },
314 .hla = {
315 .addr = 0x12,
316 .mask = BIT(5),
317 },
318 .od = {
319 .addr = 0x12,
320 .mask = BIT(4),
321 },
322 },
323 .decimator = {
324 [ST_LSM6DSX_ID_ACC] = {
325 .addr = 0x08,
326 .mask = GENMASK(2, 0),
327 },
328 [ST_LSM6DSX_ID_GYRO] = {
329 .addr = 0x08,
330 .mask = GENMASK(5, 3),
331 },
332 },
333 .fifo_ops = {
334 .update_fifo = st_lsm6dsx_update_fifo,
335 .read_fifo = st_lsm6dsx_read_fifo,
336 .fifo_th = {
337 .addr = 0x06,
338 .mask = GENMASK(11, 0),
339 },
340 .fifo_diff = {
341 .addr = 0x3a,
342 .mask = GENMASK(11, 0),
343 },
344 .max_size = 1365,
345 .th_wl = 3, /* 1LSB = 2B */
346 },
347 .ts_settings = {
348 .timer_en = {
349 .addr = 0x58,
350 .mask = BIT(7),
351 },
352 .hr_timer = {
353 .addr = 0x5c,
354 .mask = BIT(4),
355 },
356 .fifo_en = {
357 .addr = 0x07,
358 .mask = BIT(7),
359 },
360 .decimator = {
361 .addr = 0x09,
362 .mask = GENMASK(5, 3),
363 },
364 },
365 .event_settings = {
366 .wakeup_reg = {
367 .addr = 0x5B,
368 .mask = GENMASK(5, 0),
369 },
370 .wakeup_src_reg = 0x1b,
371 .wakeup_src_status_mask = BIT(3),
372 .wakeup_src_z_mask = BIT(0),
373 .wakeup_src_y_mask = BIT(1),
374 .wakeup_src_x_mask = BIT(2),
375 },
376 },
377 {
378 .reset = {
379 .addr = 0x12,
380 .mask = BIT(0),
381 },
382 .boot = {
383 .addr = 0x12,
384 .mask = BIT(7),
385 },
386 .bdu = {
387 .addr = 0x12,
388 .mask = BIT(6),
389 },
390 .id = {
391 {
392 .hw_id = ST_LSM6DS3H_ID,
393 .name = ST_LSM6DS3H_DEV_NAME,
394 .wai = 0x69,
395 },
396 },
397 .channels = {
398 [ST_LSM6DSX_ID_ACC] = {
399 .chan = st_lsm6dsx_acc_channels,
400 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
401 },
402 [ST_LSM6DSX_ID_GYRO] = {
403 .chan = st_lsm6dsx_gyro_channels,
404 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
405 },
406 },
407 .odr_table = {
408 [ST_LSM6DSX_ID_ACC] = {
409 .reg = {
410 .addr = 0x10,
411 .mask = GENMASK(7, 4),
412 },
413 .odr_avl[0] = { 12500, 0x01 },
414 .odr_avl[1] = { 26000, 0x02 },
415 .odr_avl[2] = { 52000, 0x03 },
416 .odr_avl[3] = { 104000, 0x04 },
417 .odr_avl[4] = { 208000, 0x05 },
418 .odr_avl[5] = { 416000, 0x06 },
419 .odr_len = 6,
420 },
421 [ST_LSM6DSX_ID_GYRO] = {
422 .reg = {
423 .addr = 0x11,
424 .mask = GENMASK(7, 4),
425 },
426 .odr_avl[0] = { 12500, 0x01 },
427 .odr_avl[1] = { 26000, 0x02 },
428 .odr_avl[2] = { 52000, 0x03 },
429 .odr_avl[3] = { 104000, 0x04 },
430 .odr_avl[4] = { 208000, 0x05 },
431 .odr_avl[5] = { 416000, 0x06 },
432 .odr_len = 6,
433 },
434 },
435 .fs_table = {
436 [ST_LSM6DSX_ID_ACC] = {
437 .reg = {
438 .addr = 0x10,
439 .mask = GENMASK(3, 2),
440 },
441 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
442 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
443 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
444 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
445 .fs_len = 4,
446 },
447 [ST_LSM6DSX_ID_GYRO] = {
448 .reg = {
449 .addr = 0x11,
450 .mask = GENMASK(3, 2),
451 },
452 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
453 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
454 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
455 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
456 .fs_len = 4,
457 },
458 },
459 .irq_config = {
460 .irq1 = {
461 .addr = 0x0d,
462 .mask = BIT(3),
463 },
464 .irq2 = {
465 .addr = 0x0e,
466 .mask = BIT(3),
467 },
468 .lir = {
469 .addr = 0x58,
470 .mask = BIT(0),
471 },
472 .irq1_func = {
473 .addr = 0x5e,
474 .mask = BIT(5),
475 },
476 .irq2_func = {
477 .addr = 0x5f,
478 .mask = BIT(5),
479 },
480 .hla = {
481 .addr = 0x12,
482 .mask = BIT(5),
483 },
484 .od = {
485 .addr = 0x12,
486 .mask = BIT(4),
487 },
488 },
489 .decimator = {
490 [ST_LSM6DSX_ID_ACC] = {
491 .addr = 0x08,
492 .mask = GENMASK(2, 0),
493 },
494 [ST_LSM6DSX_ID_GYRO] = {
495 .addr = 0x08,
496 .mask = GENMASK(5, 3),
497 },
498 },
499 .fifo_ops = {
500 .update_fifo = st_lsm6dsx_update_fifo,
501 .read_fifo = st_lsm6dsx_read_fifo,
502 .fifo_th = {
503 .addr = 0x06,
504 .mask = GENMASK(11, 0),
505 },
506 .fifo_diff = {
507 .addr = 0x3a,
508 .mask = GENMASK(11, 0),
509 },
510 .max_size = 682,
511 .th_wl = 3, /* 1LSB = 2B */
512 },
513 .ts_settings = {
514 .timer_en = {
515 .addr = 0x58,
516 .mask = BIT(7),
517 },
518 .hr_timer = {
519 .addr = 0x5c,
520 .mask = BIT(4),
521 },
522 .fifo_en = {
523 .addr = 0x07,
524 .mask = BIT(7),
525 },
526 .decimator = {
527 .addr = 0x09,
528 .mask = GENMASK(5, 3),
529 },
530 },
531 .event_settings = {
532 .wakeup_reg = {
533 .addr = 0x5B,
534 .mask = GENMASK(5, 0),
535 },
536 .wakeup_src_reg = 0x1b,
537 .wakeup_src_status_mask = BIT(3),
538 .wakeup_src_z_mask = BIT(0),
539 .wakeup_src_y_mask = BIT(1),
540 .wakeup_src_x_mask = BIT(2),
541 },
542 },
543 {
544 .reset = {
545 .addr = 0x12,
546 .mask = BIT(0),
547 },
548 .boot = {
549 .addr = 0x12,
550 .mask = BIT(7),
551 },
552 .bdu = {
553 .addr = 0x12,
554 .mask = BIT(6),
555 },
556 .id = {
557 {
558 .hw_id = ST_LSM6DSL_ID,
559 .name = ST_LSM6DSL_DEV_NAME,
560 .wai = 0x6a,
561 }, {
562 .hw_id = ST_LSM6DSM_ID,
563 .name = ST_LSM6DSM_DEV_NAME,
564 .wai = 0x6a,
565 }, {
566 .hw_id = ST_ISM330DLC_ID,
567 .name = ST_ISM330DLC_DEV_NAME,
568 .wai = 0x6a,
569 }, {
570 .hw_id = ST_LSM6DS3TRC_ID,
571 .name = ST_LSM6DS3TRC_DEV_NAME,
572 .wai = 0x6a,
573 },
574 },
575 .channels = {
576 [ST_LSM6DSX_ID_ACC] = {
577 .chan = st_lsm6dsx_acc_channels,
578 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
579 },
580 [ST_LSM6DSX_ID_GYRO] = {
581 .chan = st_lsm6dsx_gyro_channels,
582 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
583 },
584 },
585 .odr_table = {
586 [ST_LSM6DSX_ID_ACC] = {
587 .reg = {
588 .addr = 0x10,
589 .mask = GENMASK(7, 4),
590 },
591 .odr_avl[0] = { 12500, 0x01 },
592 .odr_avl[1] = { 26000, 0x02 },
593 .odr_avl[2] = { 52000, 0x03 },
594 .odr_avl[3] = { 104000, 0x04 },
595 .odr_avl[4] = { 208000, 0x05 },
596 .odr_avl[5] = { 416000, 0x06 },
597 .odr_len = 6,
598 },
599 [ST_LSM6DSX_ID_GYRO] = {
600 .reg = {
601 .addr = 0x11,
602 .mask = GENMASK(7, 4),
603 },
604 .odr_avl[0] = { 12500, 0x01 },
605 .odr_avl[1] = { 26000, 0x02 },
606 .odr_avl[2] = { 52000, 0x03 },
607 .odr_avl[3] = { 104000, 0x04 },
608 .odr_avl[4] = { 208000, 0x05 },
609 .odr_avl[5] = { 416000, 0x06 },
610 .odr_len = 6,
611 },
612 },
613 .fs_table = {
614 [ST_LSM6DSX_ID_ACC] = {
615 .reg = {
616 .addr = 0x10,
617 .mask = GENMASK(3, 2),
618 },
619 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
620 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
621 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
622 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
623 .fs_len = 4,
624 },
625 [ST_LSM6DSX_ID_GYRO] = {
626 .reg = {
627 .addr = 0x11,
628 .mask = GENMASK(3, 2),
629 },
630 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
631 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
632 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
633 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
634 .fs_len = 4,
635 },
636 },
637 .irq_config = {
638 .irq1 = {
639 .addr = 0x0d,
640 .mask = BIT(3),
641 },
642 .irq2 = {
643 .addr = 0x0e,
644 .mask = BIT(3),
645 },
646 .lir = {
647 .addr = 0x58,
648 .mask = BIT(0),
649 },
650 .irq1_func = {
651 .addr = 0x5e,
652 .mask = BIT(5),
653 },
654 .irq2_func = {
655 .addr = 0x5f,
656 .mask = BIT(5),
657 },
658 .hla = {
659 .addr = 0x12,
660 .mask = BIT(5),
661 },
662 .od = {
663 .addr = 0x12,
664 .mask = BIT(4),
665 },
666 },
667 .decimator = {
668 [ST_LSM6DSX_ID_ACC] = {
669 .addr = 0x08,
670 .mask = GENMASK(2, 0),
671 },
672 [ST_LSM6DSX_ID_GYRO] = {
673 .addr = 0x08,
674 .mask = GENMASK(5, 3),
675 },
676 [ST_LSM6DSX_ID_EXT0] = {
677 .addr = 0x09,
678 .mask = GENMASK(2, 0),
679 },
680 },
681 .fifo_ops = {
682 .update_fifo = st_lsm6dsx_update_fifo,
683 .read_fifo = st_lsm6dsx_read_fifo,
684 .fifo_th = {
685 .addr = 0x06,
686 .mask = GENMASK(10, 0),
687 },
688 .fifo_diff = {
689 .addr = 0x3a,
690 .mask = GENMASK(10, 0),
691 },
692 .max_size = 682,
693 .th_wl = 3, /* 1LSB = 2B */
694 },
695 .ts_settings = {
696 .timer_en = {
697 .addr = 0x19,
698 .mask = BIT(5),
699 },
700 .hr_timer = {
701 .addr = 0x5c,
702 .mask = BIT(4),
703 },
704 .fifo_en = {
705 .addr = 0x07,
706 .mask = BIT(7),
707 },
708 .decimator = {
709 .addr = 0x09,
710 .mask = GENMASK(5, 3),
711 },
712 },
713 .shub_settings = {
714 .page_mux = {
715 .addr = 0x01,
716 .mask = BIT(7),
717 },
718 .master_en = {
719 .addr = 0x1a,
720 .mask = BIT(0),
721 },
722 .pullup_en = {
723 .addr = 0x1a,
724 .mask = BIT(3),
725 },
726 .aux_sens = {
727 .addr = 0x04,
728 .mask = GENMASK(5, 4),
729 },
730 .wr_once = {
731 .addr = 0x07,
732 .mask = BIT(5),
733 },
734 .emb_func = {
735 .addr = 0x19,
736 .mask = BIT(2),
737 },
738 .num_ext_dev = 1,
739 .shub_out = {
740 .addr = 0x2e,
741 },
742 .slv0_addr = 0x02,
743 .dw_slv0_addr = 0x0e,
744 .pause = 0x7,
745 },
746 .event_settings = {
747 .enable_reg = {
748 .addr = 0x58,
749 .mask = BIT(7),
750 },
751 .wakeup_reg = {
752 .addr = 0x5B,
753 .mask = GENMASK(5, 0),
754 },
755 .wakeup_src_reg = 0x1b,
756 .wakeup_src_status_mask = BIT(3),
757 .wakeup_src_z_mask = BIT(0),
758 .wakeup_src_y_mask = BIT(1),
759 .wakeup_src_x_mask = BIT(2),
760 },
761 },
762 {
763 .reset = {
764 .addr = 0x12,
765 .mask = BIT(0),
766 },
767 .boot = {
768 .addr = 0x12,
769 .mask = BIT(7),
770 },
771 .bdu = {
772 .addr = 0x12,
773 .mask = BIT(6),
774 },
775 .id = {
776 {
777 .hw_id = ST_LSM6DSR_ID,
778 .name = ST_LSM6DSR_DEV_NAME,
779 .wai = 0x6b,
780 }, {
781 .hw_id = ST_ISM330DHCX_ID,
782 .name = ST_ISM330DHCX_DEV_NAME,
783 .wai = 0x6b,
784 }, {
785 .hw_id = ST_LSM6DSRX_ID,
786 .name = ST_LSM6DSRX_DEV_NAME,
787 .wai = 0x6b,
788 }, {
789 .hw_id = ST_LSM6DSO_ID,
790 .name = ST_LSM6DSO_DEV_NAME,
791 .wai = 0x6c,
792 }, {
793 .hw_id = ST_LSM6DSOX_ID,
794 .name = ST_LSM6DSOX_DEV_NAME,
795 .wai = 0x6c,
796 }, {
797 .hw_id = ST_LSM6DST_ID,
798 .name = ST_LSM6DST_DEV_NAME,
799 .wai = 0x6d,
800 }, {
801 .hw_id = ST_ASM330LHHX_ID,
802 .name = ST_ASM330LHHX_DEV_NAME,
803 .wai = 0x6b,
804 }, {
805 .hw_id = ST_LSM6DSTX_ID,
806 .name = ST_LSM6DSTX_DEV_NAME,
807 .wai = 0x6d,
808 },
809 },
810 .channels = {
811 [ST_LSM6DSX_ID_ACC] = {
812 .chan = st_lsm6dsx_acc_channels,
813 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
814 },
815 [ST_LSM6DSX_ID_GYRO] = {
816 .chan = st_lsm6dsx_gyro_channels,
817 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
818 },
819 },
820 .drdy_mask = {
821 .addr = 0x13,
822 .mask = BIT(3),
823 },
824 .odr_table = {
825 [ST_LSM6DSX_ID_ACC] = {
826 .reg = {
827 .addr = 0x10,
828 .mask = GENMASK(7, 4),
829 },
830 .odr_avl[0] = { 12500, 0x01 },
831 .odr_avl[1] = { 26000, 0x02 },
832 .odr_avl[2] = { 52000, 0x03 },
833 .odr_avl[3] = { 104000, 0x04 },
834 .odr_avl[4] = { 208000, 0x05 },
835 .odr_avl[5] = { 416000, 0x06 },
836 .odr_avl[6] = { 833000, 0x07 },
837 .odr_len = 7,
838 },
839 [ST_LSM6DSX_ID_GYRO] = {
840 .reg = {
841 .addr = 0x11,
842 .mask = GENMASK(7, 4),
843 },
844 .odr_avl[0] = { 12500, 0x01 },
845 .odr_avl[1] = { 26000, 0x02 },
846 .odr_avl[2] = { 52000, 0x03 },
847 .odr_avl[3] = { 104000, 0x04 },
848 .odr_avl[4] = { 208000, 0x05 },
849 .odr_avl[5] = { 416000, 0x06 },
850 .odr_avl[6] = { 833000, 0x07 },
851 .odr_len = 7,
852 },
853 },
854 .fs_table = {
855 [ST_LSM6DSX_ID_ACC] = {
856 .reg = {
857 .addr = 0x10,
858 .mask = GENMASK(3, 2),
859 },
860 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
861 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
862 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
863 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
864 .fs_len = 4,
865 },
866 [ST_LSM6DSX_ID_GYRO] = {
867 .reg = {
868 .addr = 0x11,
869 .mask = GENMASK(3, 2),
870 },
871 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
872 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
873 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
874 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
875 .fs_len = 4,
876 },
877 },
878 .irq_config = {
879 .irq1 = {
880 .addr = 0x0d,
881 .mask = BIT(3),
882 },
883 .irq2 = {
884 .addr = 0x0e,
885 .mask = BIT(3),
886 },
887 .lir = {
888 .addr = 0x56,
889 .mask = BIT(0),
890 },
891 .clear_on_read = {
892 .addr = 0x56,
893 .mask = BIT(6),
894 },
895 .irq1_func = {
896 .addr = 0x5e,
897 .mask = BIT(5),
898 },
899 .irq2_func = {
900 .addr = 0x5f,
901 .mask = BIT(5),
902 },
903 .hla = {
904 .addr = 0x12,
905 .mask = BIT(5),
906 },
907 .od = {
908 .addr = 0x12,
909 .mask = BIT(4),
910 },
911 },
912 .batch = {
913 [ST_LSM6DSX_ID_ACC] = {
914 .addr = 0x09,
915 .mask = GENMASK(3, 0),
916 },
917 [ST_LSM6DSX_ID_GYRO] = {
918 .addr = 0x09,
919 .mask = GENMASK(7, 4),
920 },
921 },
922 .fifo_ops = {
923 .update_fifo = st_lsm6dsx_update_fifo,
924 .read_fifo = st_lsm6dsx_read_tagged_fifo,
925 .fifo_th = {
926 .addr = 0x07,
927 .mask = GENMASK(8, 0),
928 },
929 .fifo_diff = {
930 .addr = 0x3a,
931 .mask = GENMASK(9, 0),
932 },
933 .max_size = 512,
934 .th_wl = 1,
935 },
936 .ts_settings = {
937 .timer_en = {
938 .addr = 0x19,
939 .mask = BIT(5),
940 },
941 .decimator = {
942 .addr = 0x0a,
943 .mask = GENMASK(7, 6),
944 },
945 .freq_fine = 0x63,
946 },
947 .shub_settings = {
948 .page_mux = {
949 .addr = 0x01,
950 .mask = BIT(6),
951 },
952 .master_en = {
953 .sec_page = true,
954 .addr = 0x14,
955 .mask = BIT(2),
956 },
957 .pullup_en = {
958 .sec_page = true,
959 .addr = 0x14,
960 .mask = BIT(3),
961 },
962 .aux_sens = {
963 .addr = 0x14,
964 .mask = GENMASK(1, 0),
965 },
966 .wr_once = {
967 .addr = 0x14,
968 .mask = BIT(6),
969 },
970 .num_ext_dev = 3,
971 .shub_out = {
972 .sec_page = true,
973 .addr = 0x02,
974 },
975 .slv0_addr = 0x15,
976 .dw_slv0_addr = 0x21,
977 .batch_en = BIT(3),
978 },
979 .event_settings = {
980 .enable_reg = {
981 .addr = 0x58,
982 .mask = BIT(7),
983 },
984 .wakeup_reg = {
985 .addr = 0x5b,
986 .mask = GENMASK(5, 0),
987 },
988 .wakeup_src_reg = 0x1b,
989 .wakeup_src_status_mask = BIT(3),
990 .wakeup_src_z_mask = BIT(0),
991 .wakeup_src_y_mask = BIT(1),
992 .wakeup_src_x_mask = BIT(2),
993 },
994 },
995 {
996 .reset = {
997 .addr = 0x12,
998 .mask = BIT(0),
999 },
1000 .boot = {
1001 .addr = 0x12,
1002 .mask = BIT(7),
1003 },
1004 .bdu = {
1005 .addr = 0x12,
1006 .mask = BIT(6),
1007 },
1008 .id = {
1009 {
1010 .hw_id = ST_ASM330LHH_ID,
1011 .name = ST_ASM330LHH_DEV_NAME,
1012 .wai = 0x6b,
1013 }, {
1014 .hw_id = ST_LSM6DSOP_ID,
1015 .name = ST_LSM6DSOP_DEV_NAME,
1016 .wai = 0x6c,
1017 },
1018 },
1019 .channels = {
1020 [ST_LSM6DSX_ID_ACC] = {
1021 .chan = st_lsm6dsx_acc_channels,
1022 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
1023 },
1024 [ST_LSM6DSX_ID_GYRO] = {
1025 .chan = st_lsm6dsx_gyro_channels,
1026 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
1027 },
1028 },
1029 .drdy_mask = {
1030 .addr = 0x13,
1031 .mask = BIT(3),
1032 },
1033 .odr_table = {
1034 [ST_LSM6DSX_ID_ACC] = {
1035 .reg = {
1036 .addr = 0x10,
1037 .mask = GENMASK(7, 4),
1038 },
1039 .odr_avl[0] = { 12500, 0x01 },
1040 .odr_avl[1] = { 26000, 0x02 },
1041 .odr_avl[2] = { 52000, 0x03 },
1042 .odr_avl[3] = { 104000, 0x04 },
1043 .odr_avl[4] = { 208000, 0x05 },
1044 .odr_avl[5] = { 416000, 0x06 },
1045 .odr_avl[6] = { 833000, 0x07 },
1046 .odr_len = 7,
1047 },
1048 [ST_LSM6DSX_ID_GYRO] = {
1049 .reg = {
1050 .addr = 0x11,
1051 .mask = GENMASK(7, 4),
1052 },
1053 .odr_avl[0] = { 12500, 0x01 },
1054 .odr_avl[1] = { 26000, 0x02 },
1055 .odr_avl[2] = { 52000, 0x03 },
1056 .odr_avl[3] = { 104000, 0x04 },
1057 .odr_avl[4] = { 208000, 0x05 },
1058 .odr_avl[5] = { 416000, 0x06 },
1059 .odr_avl[6] = { 833000, 0x07 },
1060 .odr_len = 7,
1061 },
1062 },
1063 .fs_table = {
1064 [ST_LSM6DSX_ID_ACC] = {
1065 .reg = {
1066 .addr = 0x10,
1067 .mask = GENMASK(3, 2),
1068 },
1069 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
1070 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
1071 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
1072 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
1073 .fs_len = 4,
1074 },
1075 [ST_LSM6DSX_ID_GYRO] = {
1076 .reg = {
1077 .addr = 0x11,
1078 .mask = GENMASK(3, 2),
1079 },
1080 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
1081 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
1082 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
1083 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
1084 .fs_len = 4,
1085 },
1086 },
1087 .irq_config = {
1088 .irq1 = {
1089 .addr = 0x0d,
1090 .mask = BIT(3),
1091 },
1092 .irq2 = {
1093 .addr = 0x0e,
1094 .mask = BIT(3),
1095 },
1096 .lir = {
1097 .addr = 0x56,
1098 .mask = BIT(0),
1099 },
1100 .clear_on_read = {
1101 .addr = 0x56,
1102 .mask = BIT(6),
1103 },
1104 .irq1_func = {
1105 .addr = 0x5e,
1106 .mask = BIT(5),
1107 },
1108 .irq2_func = {
1109 .addr = 0x5f,
1110 .mask = BIT(5),
1111 },
1112 .hla = {
1113 .addr = 0x12,
1114 .mask = BIT(5),
1115 },
1116 .od = {
1117 .addr = 0x12,
1118 .mask = BIT(4),
1119 },
1120 },
1121 .batch = {
1122 [ST_LSM6DSX_ID_ACC] = {
1123 .addr = 0x09,
1124 .mask = GENMASK(3, 0),
1125 },
1126 [ST_LSM6DSX_ID_GYRO] = {
1127 .addr = 0x09,
1128 .mask = GENMASK(7, 4),
1129 },
1130 },
1131 .fifo_ops = {
1132 .update_fifo = st_lsm6dsx_update_fifo,
1133 .read_fifo = st_lsm6dsx_read_tagged_fifo,
1134 .fifo_th = {
1135 .addr = 0x07,
1136 .mask = GENMASK(8, 0),
1137 },
1138 .fifo_diff = {
1139 .addr = 0x3a,
1140 .mask = GENMASK(9, 0),
1141 },
1142 .max_size = 512,
1143 .th_wl = 1,
1144 },
1145 .ts_settings = {
1146 .timer_en = {
1147 .addr = 0x19,
1148 .mask = BIT(5),
1149 },
1150 .decimator = {
1151 .addr = 0x0a,
1152 .mask = GENMASK(7, 6),
1153 },
1154 .freq_fine = 0x63,
1155 },
1156 .event_settings = {
1157 .enable_reg = {
1158 .addr = 0x58,
1159 .mask = BIT(7),
1160 },
1161 .wakeup_reg = {
1162 .addr = 0x5B,
1163 .mask = GENMASK(5, 0),
1164 },
1165 .wakeup_src_reg = 0x1b,
1166 .wakeup_src_status_mask = BIT(3),
1167 .wakeup_src_z_mask = BIT(0),
1168 .wakeup_src_y_mask = BIT(1),
1169 .wakeup_src_x_mask = BIT(2),
1170 },
1171 },
1172 {
1173 .reset = {
1174 .addr = 0x12,
1175 .mask = BIT(0),
1176 },
1177 .boot = {
1178 .addr = 0x12,
1179 .mask = BIT(7),
1180 },
1181 .bdu = {
1182 .addr = 0x12,
1183 .mask = BIT(6),
1184 },
1185 .id = {
1186 {
1187 .hw_id = ST_LSM6DSV_ID,
1188 .name = ST_LSM6DSV_DEV_NAME,
1189 .wai = 0x70,
1190 }, {
1191 .hw_id = ST_LSM6DSV16X_ID,
1192 .name = ST_LSM6DSV16X_DEV_NAME,
1193 .wai = 0x70,
1194 },
1195 },
1196 .channels = {
1197 [ST_LSM6DSX_ID_ACC] = {
1198 .chan = st_lsm6dsx_acc_channels,
1199 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
1200 },
1201 [ST_LSM6DSX_ID_GYRO] = {
1202 .chan = st_lsm6dsx_gyro_channels,
1203 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
1204 },
1205 },
1206 .drdy_mask = {
1207 .addr = 0x13,
1208 .mask = BIT(3),
1209 },
1210 .odr_table = {
1211 [ST_LSM6DSX_ID_ACC] = {
1212 .reg = {
1213 .addr = 0x10,
1214 .mask = GENMASK(3, 0),
1215 },
1216 .odr_avl[0] = { 7500, 0x02 },
1217 .odr_avl[1] = { 15000, 0x03 },
1218 .odr_avl[2] = { 30000, 0x04 },
1219 .odr_avl[3] = { 60000, 0x05 },
1220 .odr_avl[4] = { 120000, 0x06 },
1221 .odr_avl[5] = { 240000, 0x07 },
1222 .odr_avl[6] = { 480000, 0x08 },
1223 .odr_avl[7] = { 960000, 0x09 },
1224 .odr_len = 8,
1225 },
1226 [ST_LSM6DSX_ID_GYRO] = {
1227 .reg = {
1228 .addr = 0x11,
1229 .mask = GENMASK(3, 0),
1230 },
1231 .odr_avl[0] = { 7500, 0x02 },
1232 .odr_avl[1] = { 15000, 0x03 },
1233 .odr_avl[2] = { 30000, 0x04 },
1234 .odr_avl[3] = { 60000, 0x05 },
1235 .odr_avl[4] = { 120000, 0x06 },
1236 .odr_avl[5] = { 240000, 0x07 },
1237 .odr_avl[6] = { 480000, 0x08 },
1238 .odr_avl[7] = { 960000, 0x09 },
1239 .odr_len = 8,
1240 },
1241 },
1242 .fs_table = {
1243 [ST_LSM6DSX_ID_ACC] = {
1244 .reg = {
1245 .addr = 0x17,
1246 .mask = GENMASK(1, 0),
1247 },
1248 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
1249 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x1 },
1250 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x2 },
1251 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x3 },
1252 .fs_len = 4,
1253 },
1254 [ST_LSM6DSX_ID_GYRO] = {
1255 .reg = {
1256 .addr = 0x15,
1257 .mask = GENMASK(3, 0),
1258 },
1259 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x1 },
1260 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x2 },
1261 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x3 },
1262 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x4 },
1263 .fs_len = 4,
1264 },
1265 },
1266 .irq_config = {
1267 .irq1 = {
1268 .addr = 0x0d,
1269 .mask = BIT(3),
1270 },
1271 .irq2 = {
1272 .addr = 0x0e,
1273 .mask = BIT(3),
1274 },
1275 .lir = {
1276 .addr = 0x56,
1277 .mask = BIT(0),
1278 },
1279 .irq1_func = {
1280 .addr = 0x5e,
1281 .mask = BIT(5),
1282 },
1283 .irq2_func = {
1284 .addr = 0x5f,
1285 .mask = BIT(5),
1286 },
1287 .hla = {
1288 .addr = 0x03,
1289 .mask = BIT(4),
1290 },
1291 .od = {
1292 .addr = 0x03,
1293 .mask = BIT(3),
1294 },
1295 },
1296 .batch = {
1297 [ST_LSM6DSX_ID_ACC] = {
1298 .addr = 0x09,
1299 .mask = GENMASK(3, 0),
1300 },
1301 [ST_LSM6DSX_ID_GYRO] = {
1302 .addr = 0x09,
1303 .mask = GENMASK(7, 4),
1304 },
1305 },
1306 .fifo_ops = {
1307 .update_fifo = st_lsm6dsx_update_fifo,
1308 .read_fifo = st_lsm6dsx_read_tagged_fifo,
1309 .fifo_th = {
1310 .addr = 0x07,
1311 .mask = GENMASK(7, 0),
1312 },
1313 .fifo_diff = {
1314 .addr = 0x1b,
1315 .mask = GENMASK(8, 0),
1316 },
1317 .max_size = 512,
1318 .th_wl = 1,
1319 },
1320 .ts_settings = {
1321 .timer_en = {
1322 .addr = 0x50,
1323 .mask = BIT(6),
1324 },
1325 .decimator = {
1326 .addr = 0x0a,
1327 .mask = GENMASK(7, 6),
1328 },
1329 .freq_fine = 0x4f,
1330 },
1331 .shub_settings = {
1332 .page_mux = {
1333 .addr = 0x01,
1334 .mask = BIT(6),
1335 },
1336 .master_en = {
1337 .sec_page = true,
1338 .addr = 0x14,
1339 .mask = BIT(2),
1340 },
1341 .pullup_en = {
1342 .addr = 0x03,
1343 .mask = BIT(6),
1344 },
1345 .aux_sens = {
1346 .addr = 0x14,
1347 .mask = GENMASK(1, 0),
1348 },
1349 .wr_once = {
1350 .addr = 0x14,
1351 .mask = BIT(6),
1352 },
1353 .num_ext_dev = 3,
1354 .shub_out = {
1355 .sec_page = true,
1356 .addr = 0x02,
1357 },
1358 .slv0_addr = 0x15,
1359 .dw_slv0_addr = 0x21,
1360 .batch_en = BIT(3),
1361 },
1362 .event_settings = {
1363 .enable_reg = {
1364 .addr = 0x50,
1365 .mask = BIT(7),
1366 },
1367 .wakeup_reg = {
1368 .addr = 0x5b,
1369 .mask = GENMASK(5, 0),
1370 },
1371 .wakeup_src_reg = 0x45,
1372 .wakeup_src_status_mask = BIT(3),
1373 .wakeup_src_z_mask = BIT(0),
1374 .wakeup_src_y_mask = BIT(1),
1375 .wakeup_src_x_mask = BIT(2),
1376 },
1377 },
1378 {
1379 .reset = {
1380 .addr = 0x12,
1381 .mask = BIT(0),
1382 },
1383 .boot = {
1384 .addr = 0x12,
1385 .mask = BIT(7),
1386 },
1387 .bdu = {
1388 .addr = 0x12,
1389 .mask = BIT(6),
1390 },
1391 .id = {
1392 {
1393 .hw_id = ST_LSM6DSO16IS_ID,
1394 .name = ST_LSM6DSO16IS_DEV_NAME,
1395 .wai = 0x22,
1396 }, {
1397 .hw_id = ST_ISM330IS_ID,
1398 .name = ST_ISM330IS_DEV_NAME,
1399 .wai = 0x22,
1400 }
1401 },
1402 .channels = {
1403 [ST_LSM6DSX_ID_ACC] = {
1404 .chan = st_lsm6dsx_acc_channels,
1405 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
1406 },
1407 [ST_LSM6DSX_ID_GYRO] = {
1408 .chan = st_lsm6dsx_gyro_channels,
1409 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
1410 },
1411 },
1412 .odr_table = {
1413 [ST_LSM6DSX_ID_ACC] = {
1414 .reg = {
1415 .addr = 0x10,
1416 .mask = GENMASK(7, 4),
1417 },
1418 .odr_avl[0] = { 12500, 0x01 },
1419 .odr_avl[1] = { 26000, 0x02 },
1420 .odr_avl[2] = { 52000, 0x03 },
1421 .odr_avl[3] = { 104000, 0x04 },
1422 .odr_avl[4] = { 208000, 0x05 },
1423 .odr_avl[5] = { 416000, 0x06 },
1424 .odr_avl[6] = { 833000, 0x07 },
1425 .odr_len = 7,
1426 },
1427 [ST_LSM6DSX_ID_GYRO] = {
1428 .reg = {
1429 .addr = 0x11,
1430 .mask = GENMASK(7, 4),
1431 },
1432 .odr_avl[0] = { 12500, 0x01 },
1433 .odr_avl[1] = { 26000, 0x02 },
1434 .odr_avl[2] = { 52000, 0x03 },
1435 .odr_avl[3] = { 104000, 0x04 },
1436 .odr_avl[4] = { 208000, 0x05 },
1437 .odr_avl[5] = { 416000, 0x06 },
1438 .odr_avl[6] = { 833000, 0x07 },
1439 .odr_len = 7,
1440 },
1441 },
1442 .fs_table = {
1443 [ST_LSM6DSX_ID_ACC] = {
1444 .reg = {
1445 .addr = 0x10,
1446 .mask = GENMASK(3, 2),
1447 },
1448 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
1449 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
1450 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
1451 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
1452 .fs_len = 4,
1453 },
1454 [ST_LSM6DSX_ID_GYRO] = {
1455 .reg = {
1456 .addr = 0x11,
1457 .mask = GENMASK(3, 2),
1458 },
1459 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
1460 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
1461 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
1462 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
1463 .fs_len = 4,
1464 },
1465 },
1466 .irq_config = {
1467 .hla = {
1468 .addr = 0x12,
1469 .mask = BIT(5),
1470 },
1471 .od = {
1472 .addr = 0x12,
1473 .mask = BIT(4),
1474 },
1475 },
1476 .shub_settings = {
1477 .page_mux = {
1478 .addr = 0x01,
1479 .mask = BIT(6),
1480 },
1481 .master_en = {
1482 .sec_page = true,
1483 .addr = 0x14,
1484 .mask = BIT(2),
1485 },
1486 .pullup_en = {
1487 .sec_page = true,
1488 .addr = 0x14,
1489 .mask = BIT(3),
1490 },
1491 .aux_sens = {
1492 .addr = 0x14,
1493 .mask = GENMASK(1, 0),
1494 },
1495 .wr_once = {
1496 .addr = 0x14,
1497 .mask = BIT(6),
1498 },
1499 .num_ext_dev = 3,
1500 .shub_out = {
1501 .sec_page = true,
1502 .addr = 0x02,
1503 },
1504 .slv0_addr = 0x15,
1505 .dw_slv0_addr = 0x21,
1506 },
1507 },
1508 };
1509
st_lsm6dsx_set_page(struct st_lsm6dsx_hw * hw,bool enable)1510 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable)
1511 {
1512 const struct st_lsm6dsx_shub_settings *hub_settings;
1513 unsigned int data;
1514 int err;
1515
1516 hub_settings = &hw->settings->shub_settings;
1517 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask);
1518 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr,
1519 hub_settings->page_mux.mask, data);
1520 usleep_range(100, 150);
1521
1522 return err;
1523 }
1524
st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw * hw,int id,const char ** name)1525 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id,
1526 const char **name)
1527 {
1528 int err, i, j, data;
1529
1530 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) {
1531 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) {
1532 if (st_lsm6dsx_sensor_settings[i].id[j].name &&
1533 id == st_lsm6dsx_sensor_settings[i].id[j].hw_id)
1534 break;
1535 }
1536 if (j < ST_LSM6DSX_MAX_ID)
1537 break;
1538 }
1539
1540 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) {
1541 dev_err(hw->dev, "unsupported hw id [%02x]\n", id);
1542 return -ENODEV;
1543 }
1544
1545 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data);
1546 if (err < 0) {
1547 dev_err(hw->dev, "failed to read whoami register\n");
1548 return err;
1549 }
1550
1551 if (data != st_lsm6dsx_sensor_settings[i].id[j].wai) {
1552 dev_err(hw->dev, "unsupported whoami [%02x]\n", data);
1553 return -ENODEV;
1554 }
1555
1556 *name = st_lsm6dsx_sensor_settings[i].id[j].name;
1557 hw->settings = &st_lsm6dsx_sensor_settings[i];
1558
1559 return 0;
1560 }
1561
st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor * sensor,u32 gain)1562 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor,
1563 u32 gain)
1564 {
1565 const struct st_lsm6dsx_fs_table_entry *fs_table;
1566 unsigned int data;
1567 int i, err;
1568
1569 fs_table = &sensor->hw->settings->fs_table[sensor->id];
1570 for (i = 0; i < fs_table->fs_len; i++) {
1571 if (fs_table->fs_avl[i].gain == gain)
1572 break;
1573 }
1574
1575 if (i == fs_table->fs_len)
1576 return -EINVAL;
1577
1578 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val,
1579 fs_table->reg.mask);
1580 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr,
1581 fs_table->reg.mask, data);
1582 if (err < 0)
1583 return err;
1584
1585 sensor->gain = gain;
1586
1587 return 0;
1588 }
1589
st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor * sensor,u32 odr,u8 * val)1590 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u32 odr, u8 *val)
1591 {
1592 const struct st_lsm6dsx_odr_table_entry *odr_table;
1593 int i;
1594
1595 odr_table = &sensor->hw->settings->odr_table[sensor->id];
1596 for (i = 0; i < odr_table->odr_len; i++) {
1597 /*
1598 * ext devices can run at different odr respect to
1599 * accel sensor
1600 */
1601 if (odr_table->odr_avl[i].milli_hz >= odr)
1602 break;
1603 }
1604
1605 if (i == odr_table->odr_len)
1606 return -EINVAL;
1607
1608 *val = odr_table->odr_avl[i].val;
1609 return odr_table->odr_avl[i].milli_hz;
1610 }
1611
1612 static int
st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw * hw,u32 odr,enum st_lsm6dsx_sensor_id id)1613 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u32 odr,
1614 enum st_lsm6dsx_sensor_id id)
1615 {
1616 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]);
1617
1618 if (odr > 0) {
1619 if (hw->enable_mask & BIT(id))
1620 return max_t(u32, ref->odr, odr);
1621 else
1622 return odr;
1623 } else {
1624 return (hw->enable_mask & BIT(id)) ? ref->odr : 0;
1625 }
1626 }
1627
1628 static int
st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor * sensor,u32 req_odr)1629 st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u32 req_odr)
1630 {
1631 struct st_lsm6dsx_sensor *ref_sensor = sensor;
1632 struct st_lsm6dsx_hw *hw = sensor->hw;
1633 const struct st_lsm6dsx_reg *reg;
1634 unsigned int data;
1635 u8 val = 0;
1636 int err;
1637
1638 switch (sensor->id) {
1639 case ST_LSM6DSX_ID_GYRO:
1640 break;
1641 case ST_LSM6DSX_ID_EXT0:
1642 case ST_LSM6DSX_ID_EXT1:
1643 case ST_LSM6DSX_ID_EXT2:
1644 case ST_LSM6DSX_ID_ACC: {
1645 u32 odr;
1646 int i;
1647
1648 /*
1649 * i2c embedded controller relies on the accelerometer sensor as
1650 * bus read/write trigger so we need to enable accel device
1651 * at odr = max(accel_odr, ext_odr) in order to properly
1652 * communicate with i2c slave devices
1653 */
1654 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
1655 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) {
1656 if (!hw->iio_devs[i] || i == sensor->id)
1657 continue;
1658
1659 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i);
1660 if (odr != req_odr)
1661 /* device already configured */
1662 return 0;
1663 }
1664 break;
1665 }
1666 default: /* should never occur */
1667 return -EINVAL;
1668 }
1669
1670 if (req_odr > 0) {
1671 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val);
1672 if (err < 0)
1673 return err;
1674 }
1675
1676 reg = &hw->settings->odr_table[ref_sensor->id].reg;
1677 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask);
1678 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data);
1679 }
1680
1681 static int
__st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor * sensor,bool enable)1682 __st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
1683 bool enable)
1684 {
1685 struct st_lsm6dsx_hw *hw = sensor->hw;
1686 u32 odr = enable ? sensor->odr : 0;
1687 int err;
1688
1689 err = st_lsm6dsx_set_odr(sensor, odr);
1690 if (err < 0)
1691 return err;
1692
1693 if (enable)
1694 hw->enable_mask |= BIT(sensor->id);
1695 else
1696 hw->enable_mask &= ~BIT(sensor->id);
1697
1698 return 0;
1699 }
1700
1701 static int
st_lsm6dsx_check_events(struct st_lsm6dsx_sensor * sensor,bool enable)1702 st_lsm6dsx_check_events(struct st_lsm6dsx_sensor *sensor, bool enable)
1703 {
1704 struct st_lsm6dsx_hw *hw = sensor->hw;
1705
1706 if (sensor->id == ST_LSM6DSX_ID_GYRO || enable)
1707 return 0;
1708
1709 return hw->enable_event;
1710 }
1711
st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor * sensor,bool enable)1712 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
1713 bool enable)
1714 {
1715 if (st_lsm6dsx_check_events(sensor, enable))
1716 return 0;
1717
1718 return __st_lsm6dsx_sensor_set_enable(sensor, enable);
1719 }
1720
st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor * sensor,u8 addr,int * val)1721 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor,
1722 u8 addr, int *val)
1723 {
1724 struct st_lsm6dsx_hw *hw = sensor->hw;
1725 int err, delay;
1726 __le16 data;
1727
1728 err = st_lsm6dsx_sensor_set_enable(sensor, true);
1729 if (err < 0)
1730 return err;
1731
1732 /*
1733 * we need to wait for sensor settling time before
1734 * reading data in order to avoid corrupted samples
1735 */
1736 delay = 1000000000 / sensor->odr;
1737 usleep_range(3 * delay, 4 * delay);
1738
1739 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data));
1740 if (err < 0)
1741 return err;
1742
1743 if (!hw->enable_event) {
1744 err = st_lsm6dsx_sensor_set_enable(sensor, false);
1745 if (err < 0)
1746 return err;
1747 }
1748
1749 *val = (s16)le16_to_cpu(data);
1750
1751 return IIO_VAL_INT;
1752 }
1753
st_lsm6dsx_read_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * ch,int * val,int * val2,long mask)1754 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev,
1755 struct iio_chan_spec const *ch,
1756 int *val, int *val2, long mask)
1757 {
1758 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1759 int ret;
1760
1761 switch (mask) {
1762 case IIO_CHAN_INFO_RAW:
1763 ret = iio_device_claim_direct_mode(iio_dev);
1764 if (ret)
1765 break;
1766
1767 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val);
1768 iio_device_release_direct_mode(iio_dev);
1769 break;
1770 case IIO_CHAN_INFO_SAMP_FREQ:
1771 *val = sensor->odr / 1000;
1772 *val2 = (sensor->odr % 1000) * 1000;
1773 ret = IIO_VAL_INT_PLUS_MICRO;
1774 break;
1775 case IIO_CHAN_INFO_SCALE:
1776 *val = 0;
1777 *val2 = sensor->gain;
1778 ret = IIO_VAL_INT_PLUS_NANO;
1779 break;
1780 default:
1781 ret = -EINVAL;
1782 break;
1783 }
1784
1785 return ret;
1786 }
1787
st_lsm6dsx_write_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1788 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev,
1789 struct iio_chan_spec const *chan,
1790 int val, int val2, long mask)
1791 {
1792 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1793 int err;
1794
1795 err = iio_device_claim_direct_mode(iio_dev);
1796 if (err)
1797 return err;
1798
1799 switch (mask) {
1800 case IIO_CHAN_INFO_SCALE:
1801 err = st_lsm6dsx_set_full_scale(sensor, val2);
1802 break;
1803 case IIO_CHAN_INFO_SAMP_FREQ: {
1804 u8 data;
1805
1806 val = val * 1000 + val2 / 1000;
1807 val = st_lsm6dsx_check_odr(sensor, val, &data);
1808 if (val < 0)
1809 err = val;
1810 else
1811 sensor->odr = val;
1812 break;
1813 }
1814 default:
1815 err = -EINVAL;
1816 break;
1817 }
1818
1819 iio_device_release_direct_mode(iio_dev);
1820
1821 return err;
1822 }
1823
st_lsm6dsx_event_setup(struct st_lsm6dsx_hw * hw,int state)1824 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state)
1825 {
1826 const struct st_lsm6dsx_reg *reg;
1827 unsigned int data;
1828 int err;
1829
1830 if (!hw->settings->irq_config.irq1_func.addr)
1831 return -ENOTSUPP;
1832
1833 reg = &hw->settings->event_settings.enable_reg;
1834 if (reg->addr) {
1835 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask);
1836 err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
1837 reg->mask, data);
1838 if (err < 0)
1839 return err;
1840 }
1841
1842 /* Enable wakeup interrupt */
1843 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask);
1844 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr,
1845 hw->irq_routing->mask, data);
1846 }
1847
st_lsm6dsx_read_event(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1848 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev,
1849 const struct iio_chan_spec *chan,
1850 enum iio_event_type type,
1851 enum iio_event_direction dir,
1852 enum iio_event_info info,
1853 int *val, int *val2)
1854 {
1855 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1856 struct st_lsm6dsx_hw *hw = sensor->hw;
1857
1858 if (type != IIO_EV_TYPE_THRESH)
1859 return -EINVAL;
1860
1861 *val2 = 0;
1862 *val = hw->event_threshold;
1863
1864 return IIO_VAL_INT;
1865 }
1866
1867 static int
st_lsm6dsx_write_event(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1868 st_lsm6dsx_write_event(struct iio_dev *iio_dev,
1869 const struct iio_chan_spec *chan,
1870 enum iio_event_type type,
1871 enum iio_event_direction dir,
1872 enum iio_event_info info,
1873 int val, int val2)
1874 {
1875 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1876 struct st_lsm6dsx_hw *hw = sensor->hw;
1877 const struct st_lsm6dsx_reg *reg;
1878 unsigned int data;
1879 int err;
1880
1881 if (type != IIO_EV_TYPE_THRESH)
1882 return -EINVAL;
1883
1884 if (val < 0 || val > 31)
1885 return -EINVAL;
1886
1887 reg = &hw->settings->event_settings.wakeup_reg;
1888 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask);
1889 err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
1890 reg->mask, data);
1891 if (err < 0)
1892 return -EINVAL;
1893
1894 hw->event_threshold = val;
1895
1896 return 0;
1897 }
1898
1899 static int
st_lsm6dsx_read_event_config(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1900 st_lsm6dsx_read_event_config(struct iio_dev *iio_dev,
1901 const struct iio_chan_spec *chan,
1902 enum iio_event_type type,
1903 enum iio_event_direction dir)
1904 {
1905 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1906 struct st_lsm6dsx_hw *hw = sensor->hw;
1907
1908 if (type != IIO_EV_TYPE_THRESH)
1909 return -EINVAL;
1910
1911 return !!(hw->enable_event & BIT(chan->channel2));
1912 }
1913
1914 static int
st_lsm6dsx_write_event_config(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)1915 st_lsm6dsx_write_event_config(struct iio_dev *iio_dev,
1916 const struct iio_chan_spec *chan,
1917 enum iio_event_type type,
1918 enum iio_event_direction dir, int state)
1919 {
1920 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1921 struct st_lsm6dsx_hw *hw = sensor->hw;
1922 u8 enable_event;
1923 int err;
1924
1925 if (type != IIO_EV_TYPE_THRESH)
1926 return -EINVAL;
1927
1928 if (state) {
1929 enable_event = hw->enable_event | BIT(chan->channel2);
1930
1931 /* do not enable events if they are already enabled */
1932 if (hw->enable_event)
1933 goto out;
1934 } else {
1935 enable_event = hw->enable_event & ~BIT(chan->channel2);
1936
1937 /* only turn off sensor if no events is enabled */
1938 if (enable_event)
1939 goto out;
1940 }
1941
1942 /* stop here if no changes have been made */
1943 if (hw->enable_event == enable_event)
1944 return 0;
1945
1946 err = st_lsm6dsx_event_setup(hw, state);
1947 if (err < 0)
1948 return err;
1949
1950 mutex_lock(&hw->conf_lock);
1951 if (enable_event || !(hw->fifo_mask & BIT(sensor->id)))
1952 err = __st_lsm6dsx_sensor_set_enable(sensor, state);
1953 mutex_unlock(&hw->conf_lock);
1954 if (err < 0)
1955 return err;
1956
1957 out:
1958 hw->enable_event = enable_event;
1959
1960 return 0;
1961 }
1962
st_lsm6dsx_set_watermark(struct iio_dev * iio_dev,unsigned int val)1963 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val)
1964 {
1965 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1966 struct st_lsm6dsx_hw *hw = sensor->hw;
1967 int err;
1968
1969 val = clamp_val(val, 1, hw->settings->fifo_ops.max_size);
1970
1971 mutex_lock(&hw->conf_lock);
1972
1973 err = st_lsm6dsx_update_watermark(sensor, val);
1974
1975 mutex_unlock(&hw->conf_lock);
1976
1977 if (err < 0)
1978 return err;
1979
1980 sensor->watermark = val;
1981
1982 return 0;
1983 }
1984
1985 static ssize_t
st_lsm6dsx_sysfs_sampling_frequency_avail(struct device * dev,struct device_attribute * attr,char * buf)1986 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev,
1987 struct device_attribute *attr,
1988 char *buf)
1989 {
1990 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_to_iio_dev(dev));
1991 const struct st_lsm6dsx_odr_table_entry *odr_table;
1992 int i, len = 0;
1993
1994 odr_table = &sensor->hw->settings->odr_table[sensor->id];
1995 for (i = 0; i < odr_table->odr_len; i++)
1996 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%03d ",
1997 odr_table->odr_avl[i].milli_hz / 1000,
1998 odr_table->odr_avl[i].milli_hz % 1000);
1999 buf[len - 1] = '\n';
2000
2001 return len;
2002 }
2003
st_lsm6dsx_sysfs_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)2004 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev,
2005 struct device_attribute *attr,
2006 char *buf)
2007 {
2008 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_to_iio_dev(dev));
2009 const struct st_lsm6dsx_fs_table_entry *fs_table;
2010 struct st_lsm6dsx_hw *hw = sensor->hw;
2011 int i, len = 0;
2012
2013 fs_table = &hw->settings->fs_table[sensor->id];
2014 for (i = 0; i < fs_table->fs_len; i++)
2015 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09u ",
2016 fs_table->fs_avl[i].gain);
2017 buf[len - 1] = '\n';
2018
2019 return len;
2020 }
2021
st_lsm6dsx_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)2022 static int st_lsm6dsx_write_raw_get_fmt(struct iio_dev *indio_dev,
2023 struct iio_chan_spec const *chan,
2024 long mask)
2025 {
2026 switch (mask) {
2027 case IIO_CHAN_INFO_SCALE:
2028 switch (chan->type) {
2029 case IIO_ANGL_VEL:
2030 case IIO_ACCEL:
2031 return IIO_VAL_INT_PLUS_NANO;
2032 default:
2033 return IIO_VAL_INT_PLUS_MICRO;
2034 }
2035 default:
2036 return IIO_VAL_INT_PLUS_MICRO;
2037 }
2038 }
2039
2040 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail);
2041 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
2042 st_lsm6dsx_sysfs_scale_avail, NULL, 0);
2043 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444,
2044 st_lsm6dsx_sysfs_scale_avail, NULL, 0);
2045
2046 static struct attribute *st_lsm6dsx_acc_attributes[] = {
2047 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
2048 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
2049 NULL,
2050 };
2051
2052 static const struct attribute_group st_lsm6dsx_acc_attribute_group = {
2053 .attrs = st_lsm6dsx_acc_attributes,
2054 };
2055
2056 static const struct iio_info st_lsm6dsx_acc_info = {
2057 .attrs = &st_lsm6dsx_acc_attribute_group,
2058 .read_raw = st_lsm6dsx_read_raw,
2059 .write_raw = st_lsm6dsx_write_raw,
2060 .read_event_value = st_lsm6dsx_read_event,
2061 .write_event_value = st_lsm6dsx_write_event,
2062 .read_event_config = st_lsm6dsx_read_event_config,
2063 .write_event_config = st_lsm6dsx_write_event_config,
2064 .hwfifo_set_watermark = st_lsm6dsx_set_watermark,
2065 .write_raw_get_fmt = st_lsm6dsx_write_raw_get_fmt,
2066 };
2067
2068 static struct attribute *st_lsm6dsx_gyro_attributes[] = {
2069 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
2070 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr,
2071 NULL,
2072 };
2073
2074 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = {
2075 .attrs = st_lsm6dsx_gyro_attributes,
2076 };
2077
2078 static const struct iio_info st_lsm6dsx_gyro_info = {
2079 .attrs = &st_lsm6dsx_gyro_attribute_group,
2080 .read_raw = st_lsm6dsx_read_raw,
2081 .write_raw = st_lsm6dsx_write_raw,
2082 .hwfifo_set_watermark = st_lsm6dsx_set_watermark,
2083 .write_raw_get_fmt = st_lsm6dsx_write_raw_get_fmt,
2084 };
2085
st_lsm6dsx_get_drdy_pin(struct st_lsm6dsx_hw * hw,int * drdy_pin)2086 static int st_lsm6dsx_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
2087 {
2088 struct device *dev = hw->dev;
2089
2090 if (!dev_fwnode(dev))
2091 return -EINVAL;
2092
2093 return device_property_read_u32(dev, "st,drdy-int-pin", drdy_pin);
2094 }
2095
2096 static int
st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw * hw,const struct st_lsm6dsx_reg ** drdy_reg)2097 st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw,
2098 const struct st_lsm6dsx_reg **drdy_reg)
2099 {
2100 int err = 0, drdy_pin;
2101
2102 if (st_lsm6dsx_get_drdy_pin(hw, &drdy_pin) < 0) {
2103 struct st_sensors_platform_data *pdata;
2104 struct device *dev = hw->dev;
2105
2106 pdata = (struct st_sensors_platform_data *)dev->platform_data;
2107 drdy_pin = pdata ? pdata->drdy_int_pin : 1;
2108 }
2109
2110 switch (drdy_pin) {
2111 case 1:
2112 hw->irq_routing = &hw->settings->irq_config.irq1_func;
2113 *drdy_reg = &hw->settings->irq_config.irq1;
2114 break;
2115 case 2:
2116 hw->irq_routing = &hw->settings->irq_config.irq2_func;
2117 *drdy_reg = &hw->settings->irq_config.irq2;
2118 break;
2119 default:
2120 dev_err(hw->dev, "unsupported data ready pin\n");
2121 err = -EINVAL;
2122 break;
2123 }
2124
2125 return err;
2126 }
2127
st_lsm6dsx_init_shub(struct st_lsm6dsx_hw * hw)2128 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw)
2129 {
2130 const struct st_lsm6dsx_shub_settings *hub_settings;
2131 struct st_sensors_platform_data *pdata;
2132 struct device *dev = hw->dev;
2133 unsigned int data;
2134 int err = 0;
2135
2136 hub_settings = &hw->settings->shub_settings;
2137
2138 pdata = (struct st_sensors_platform_data *)dev->platform_data;
2139 if ((dev_fwnode(dev) && device_property_read_bool(dev, "st,pullups")) ||
2140 (pdata && pdata->pullups)) {
2141 if (hub_settings->pullup_en.sec_page) {
2142 err = st_lsm6dsx_set_page(hw, true);
2143 if (err < 0)
2144 return err;
2145 }
2146
2147 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask);
2148 err = regmap_update_bits(hw->regmap,
2149 hub_settings->pullup_en.addr,
2150 hub_settings->pullup_en.mask, data);
2151
2152 if (hub_settings->pullup_en.sec_page)
2153 st_lsm6dsx_set_page(hw, false);
2154
2155 if (err < 0)
2156 return err;
2157 }
2158
2159 if (hub_settings->aux_sens.addr) {
2160 /* configure aux sensors */
2161 err = st_lsm6dsx_set_page(hw, true);
2162 if (err < 0)
2163 return err;
2164
2165 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask);
2166 err = regmap_update_bits(hw->regmap,
2167 hub_settings->aux_sens.addr,
2168 hub_settings->aux_sens.mask, data);
2169
2170 st_lsm6dsx_set_page(hw, false);
2171
2172 if (err < 0)
2173 return err;
2174 }
2175
2176 if (hub_settings->emb_func.addr) {
2177 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->emb_func.mask);
2178 err = regmap_update_bits(hw->regmap,
2179 hub_settings->emb_func.addr,
2180 hub_settings->emb_func.mask, data);
2181 }
2182
2183 return err;
2184 }
2185
st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw * hw)2186 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw)
2187 {
2188 const struct st_lsm6dsx_hw_ts_settings *ts_settings;
2189 int err, val;
2190
2191 ts_settings = &hw->settings->ts_settings;
2192 /* enable hw timestamp generation if necessary */
2193 if (ts_settings->timer_en.addr) {
2194 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask);
2195 err = regmap_update_bits(hw->regmap,
2196 ts_settings->timer_en.addr,
2197 ts_settings->timer_en.mask, val);
2198 if (err < 0)
2199 return err;
2200 }
2201
2202 /* enable high resolution for hw ts timer if necessary */
2203 if (ts_settings->hr_timer.addr) {
2204 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask);
2205 err = regmap_update_bits(hw->regmap,
2206 ts_settings->hr_timer.addr,
2207 ts_settings->hr_timer.mask, val);
2208 if (err < 0)
2209 return err;
2210 }
2211
2212 /* enable ts queueing in FIFO if necessary */
2213 if (ts_settings->fifo_en.addr) {
2214 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask);
2215 err = regmap_update_bits(hw->regmap,
2216 ts_settings->fifo_en.addr,
2217 ts_settings->fifo_en.mask, val);
2218 if (err < 0)
2219 return err;
2220 }
2221
2222 /* calibrate timestamp sensitivity */
2223 hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY;
2224 if (ts_settings->freq_fine) {
2225 err = regmap_read(hw->regmap, ts_settings->freq_fine, &val);
2226 if (err < 0)
2227 return err;
2228
2229 /*
2230 * linearize the AN5192 formula:
2231 * 1 / (1 + x) ~= 1 - x (Taylor’s Series)
2232 * ttrim[s] = 1 / (40000 * (1 + 0.0015 * val))
2233 * ttrim[ns] ~= 25000 - 37.5 * val
2234 * ttrim[ns] ~= 25000 - (37500 * val) / 1000
2235 */
2236 hw->ts_gain -= ((s8)val * 37500) / 1000;
2237 }
2238
2239 return 0;
2240 }
2241
st_lsm6dsx_reset_device(struct st_lsm6dsx_hw * hw)2242 static int st_lsm6dsx_reset_device(struct st_lsm6dsx_hw *hw)
2243 {
2244 const struct st_lsm6dsx_reg *reg;
2245 int err;
2246
2247 /*
2248 * flush hw FIFO before device reset in order to avoid
2249 * possible races on interrupt line 1. If the first interrupt
2250 * line is asserted during hw reset the device will work in
2251 * I3C-only mode (if it is supported)
2252 */
2253 err = st_lsm6dsx_flush_fifo(hw);
2254 if (err < 0 && err != -ENOTSUPP)
2255 return err;
2256
2257 /* device sw reset */
2258 reg = &hw->settings->reset;
2259 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2260 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2261 if (err < 0)
2262 return err;
2263
2264 msleep(50);
2265
2266 /* reload trimming parameter */
2267 reg = &hw->settings->boot;
2268 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2269 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2270 if (err < 0)
2271 return err;
2272
2273 msleep(50);
2274
2275 return 0;
2276 }
2277
st_lsm6dsx_init_device(struct st_lsm6dsx_hw * hw)2278 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
2279 {
2280 const struct st_lsm6dsx_reg *reg;
2281 int err;
2282
2283 err = st_lsm6dsx_reset_device(hw);
2284 if (err < 0)
2285 return err;
2286
2287 /* enable Block Data Update */
2288 reg = &hw->settings->bdu;
2289 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2290 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2291 if (err < 0)
2292 return err;
2293
2294 /* enable FIFO watermak interrupt */
2295 err = st_lsm6dsx_get_drdy_reg(hw, ®);
2296 if (err < 0)
2297 return err;
2298
2299 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2300 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2301 if (err < 0)
2302 return err;
2303
2304 /* enable Latched interrupts for device events */
2305 if (hw->settings->irq_config.lir.addr) {
2306 reg = &hw->settings->irq_config.lir;
2307 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2308 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2309 if (err < 0)
2310 return err;
2311
2312 /* enable clear on read for latched interrupts */
2313 if (hw->settings->irq_config.clear_on_read.addr) {
2314 reg = &hw->settings->irq_config.clear_on_read;
2315 err = regmap_update_bits(hw->regmap,
2316 reg->addr, reg->mask,
2317 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2318 if (err < 0)
2319 return err;
2320 }
2321 }
2322
2323 /* enable drdy-mas if available */
2324 if (hw->settings->drdy_mask.addr) {
2325 reg = &hw->settings->drdy_mask;
2326 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2327 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2328 if (err < 0)
2329 return err;
2330 }
2331
2332 err = st_lsm6dsx_init_shub(hw);
2333 if (err < 0)
2334 return err;
2335
2336 return st_lsm6dsx_init_hw_timer(hw);
2337 }
2338
st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw * hw,enum st_lsm6dsx_sensor_id id,const char * name)2339 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw,
2340 enum st_lsm6dsx_sensor_id id,
2341 const char *name)
2342 {
2343 struct st_lsm6dsx_sensor *sensor;
2344 struct iio_dev *iio_dev;
2345
2346 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor));
2347 if (!iio_dev)
2348 return NULL;
2349
2350 iio_dev->modes = INDIO_DIRECT_MODE;
2351 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks;
2352 iio_dev->channels = hw->settings->channels[id].chan;
2353 iio_dev->num_channels = hw->settings->channels[id].len;
2354
2355 sensor = iio_priv(iio_dev);
2356 sensor->id = id;
2357 sensor->hw = hw;
2358 sensor->odr = hw->settings->odr_table[id].odr_avl[0].milli_hz;
2359 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain;
2360 sensor->watermark = 1;
2361
2362 switch (id) {
2363 case ST_LSM6DSX_ID_ACC:
2364 iio_dev->info = &st_lsm6dsx_acc_info;
2365 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel",
2366 name);
2367 break;
2368 case ST_LSM6DSX_ID_GYRO:
2369 iio_dev->info = &st_lsm6dsx_gyro_info;
2370 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro",
2371 name);
2372 break;
2373 default:
2374 return NULL;
2375 }
2376 iio_dev->name = sensor->name;
2377
2378 return iio_dev;
2379 }
2380
2381 static bool
st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw * hw)2382 st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw)
2383 {
2384 const struct st_lsm6dsx_event_settings *event_settings;
2385 int err, data;
2386 s64 timestamp;
2387
2388 if (!hw->enable_event)
2389 return false;
2390
2391 event_settings = &hw->settings->event_settings;
2392 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg,
2393 &data, sizeof(data));
2394 if (err < 0)
2395 return false;
2396
2397 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
2398 if ((data & hw->settings->event_settings.wakeup_src_z_mask) &&
2399 (hw->enable_event & BIT(IIO_MOD_Z)))
2400 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2401 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2402 0,
2403 IIO_MOD_Z,
2404 IIO_EV_TYPE_THRESH,
2405 IIO_EV_DIR_EITHER),
2406 timestamp);
2407
2408 if ((data & hw->settings->event_settings.wakeup_src_y_mask) &&
2409 (hw->enable_event & BIT(IIO_MOD_Y)))
2410 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2411 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2412 0,
2413 IIO_MOD_Y,
2414 IIO_EV_TYPE_THRESH,
2415 IIO_EV_DIR_EITHER),
2416 timestamp);
2417
2418 if ((data & hw->settings->event_settings.wakeup_src_x_mask) &&
2419 (hw->enable_event & BIT(IIO_MOD_X)))
2420 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2421 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2422 0,
2423 IIO_MOD_X,
2424 IIO_EV_TYPE_THRESH,
2425 IIO_EV_DIR_EITHER),
2426 timestamp);
2427
2428 return data & event_settings->wakeup_src_status_mask;
2429 }
2430
st_lsm6dsx_handler_thread(int irq,void * private)2431 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private)
2432 {
2433 struct st_lsm6dsx_hw *hw = private;
2434 int fifo_len = 0, len;
2435 bool event;
2436
2437 event = st_lsm6dsx_report_motion_event(hw);
2438
2439 if (!hw->settings->fifo_ops.read_fifo)
2440 return event ? IRQ_HANDLED : IRQ_NONE;
2441
2442 /*
2443 * If we are using edge IRQs, new samples can arrive while
2444 * processing current interrupt since there are no hw
2445 * guarantees the irq line stays "low" long enough to properly
2446 * detect the new interrupt. In this case the new sample will
2447 * be missed.
2448 * Polling FIFO status register allow us to read new
2449 * samples even if the interrupt arrives while processing
2450 * previous data and the timeslot where the line is "low" is
2451 * too short to be properly detected.
2452 */
2453 do {
2454 mutex_lock(&hw->fifo_lock);
2455 len = hw->settings->fifo_ops.read_fifo(hw);
2456 mutex_unlock(&hw->fifo_lock);
2457
2458 if (len > 0)
2459 fifo_len += len;
2460 } while (len > 0);
2461
2462 return fifo_len || event ? IRQ_HANDLED : IRQ_NONE;
2463 }
2464
st_lsm6dsx_sw_trigger_handler_thread(int irq,void * private)2465 static irqreturn_t st_lsm6dsx_sw_trigger_handler_thread(int irq,
2466 void *private)
2467 {
2468 struct iio_poll_func *pf = private;
2469 struct iio_dev *iio_dev = pf->indio_dev;
2470 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
2471 struct st_lsm6dsx_hw *hw = sensor->hw;
2472
2473 if (sensor->id == ST_LSM6DSX_ID_EXT0 ||
2474 sensor->id == ST_LSM6DSX_ID_EXT1 ||
2475 sensor->id == ST_LSM6DSX_ID_EXT2)
2476 st_lsm6dsx_shub_read_output(hw,
2477 (u8 *)hw->scan[sensor->id].channels,
2478 sizeof(hw->scan[sensor->id].channels));
2479 else
2480 st_lsm6dsx_read_locked(hw, iio_dev->channels[0].address,
2481 hw->scan[sensor->id].channels,
2482 sizeof(hw->scan[sensor->id].channels));
2483
2484 iio_push_to_buffers_with_timestamp(iio_dev, &hw->scan[sensor->id],
2485 iio_get_time_ns(iio_dev));
2486 iio_trigger_notify_done(iio_dev->trig);
2487
2488 return IRQ_HANDLED;
2489 }
2490
st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw * hw)2491 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw)
2492 {
2493 struct st_sensors_platform_data *pdata;
2494 const struct st_lsm6dsx_reg *reg;
2495 struct device *dev = hw->dev;
2496 unsigned long irq_type;
2497 bool irq_active_low;
2498 int err;
2499
2500 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq));
2501
2502 switch (irq_type) {
2503 case IRQF_TRIGGER_HIGH:
2504 case IRQF_TRIGGER_RISING:
2505 irq_active_low = false;
2506 break;
2507 case IRQF_TRIGGER_LOW:
2508 case IRQF_TRIGGER_FALLING:
2509 irq_active_low = true;
2510 break;
2511 default:
2512 dev_info(hw->dev, "mode %lx unsupported\n", irq_type);
2513 return -EINVAL;
2514 }
2515
2516 reg = &hw->settings->irq_config.hla;
2517 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2518 ST_LSM6DSX_SHIFT_VAL(irq_active_low,
2519 reg->mask));
2520 if (err < 0)
2521 return err;
2522
2523 pdata = (struct st_sensors_platform_data *)dev->platform_data;
2524 if ((dev_fwnode(dev) && device_property_read_bool(dev, "drive-open-drain")) ||
2525 (pdata && pdata->open_drain)) {
2526 reg = &hw->settings->irq_config.od;
2527 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2528 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2529 if (err < 0)
2530 return err;
2531
2532 irq_type |= IRQF_SHARED;
2533 }
2534
2535 err = devm_request_threaded_irq(hw->dev, hw->irq,
2536 NULL,
2537 st_lsm6dsx_handler_thread,
2538 irq_type | IRQF_ONESHOT,
2539 "lsm6dsx", hw);
2540 if (err) {
2541 dev_err(hw->dev, "failed to request trigger irq %d\n",
2542 hw->irq);
2543 return err;
2544 }
2545
2546 return 0;
2547 }
2548
st_lsm6dsx_sw_buffer_preenable(struct iio_dev * iio_dev)2549 static int st_lsm6dsx_sw_buffer_preenable(struct iio_dev *iio_dev)
2550 {
2551 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
2552
2553 return st_lsm6dsx_device_set_enable(sensor, true);
2554 }
2555
st_lsm6dsx_sw_buffer_postdisable(struct iio_dev * iio_dev)2556 static int st_lsm6dsx_sw_buffer_postdisable(struct iio_dev *iio_dev)
2557 {
2558 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
2559
2560 return st_lsm6dsx_device_set_enable(sensor, false);
2561 }
2562
2563 static const struct iio_buffer_setup_ops st_lsm6dsx_sw_buffer_ops = {
2564 .preenable = st_lsm6dsx_sw_buffer_preenable,
2565 .postdisable = st_lsm6dsx_sw_buffer_postdisable,
2566 };
2567
st_lsm6dsx_sw_buffers_setup(struct st_lsm6dsx_hw * hw)2568 static int st_lsm6dsx_sw_buffers_setup(struct st_lsm6dsx_hw *hw)
2569 {
2570 int i;
2571
2572 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2573 int err;
2574
2575 if (!hw->iio_devs[i])
2576 continue;
2577
2578 err = devm_iio_triggered_buffer_setup(hw->dev,
2579 hw->iio_devs[i], NULL,
2580 st_lsm6dsx_sw_trigger_handler_thread,
2581 &st_lsm6dsx_sw_buffer_ops);
2582 if (err)
2583 return err;
2584 }
2585
2586 return 0;
2587 }
2588
st_lsm6dsx_init_regulators(struct device * dev)2589 static int st_lsm6dsx_init_regulators(struct device *dev)
2590 {
2591 /* vdd-vddio power regulators */
2592 static const char * const regulators[] = { "vdd", "vddio" };
2593 int err;
2594
2595 err = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators),
2596 regulators);
2597 if (err)
2598 return dev_err_probe(dev, err, "failed to enable regulators\n");
2599
2600 msleep(50);
2601
2602 return 0;
2603 }
2604
st_lsm6dsx_probe(struct device * dev,int irq,int hw_id,struct regmap * regmap)2605 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id,
2606 struct regmap *regmap)
2607 {
2608 struct st_sensors_platform_data *pdata = dev->platform_data;
2609 const struct st_lsm6dsx_shub_settings *hub_settings;
2610 struct st_lsm6dsx_hw *hw;
2611 const char *name = NULL;
2612 int i, err;
2613
2614 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
2615 if (!hw)
2616 return -ENOMEM;
2617
2618 dev_set_drvdata(dev, (void *)hw);
2619
2620 mutex_init(&hw->fifo_lock);
2621 mutex_init(&hw->conf_lock);
2622 mutex_init(&hw->page_lock);
2623
2624 err = st_lsm6dsx_init_regulators(dev);
2625 if (err)
2626 return err;
2627
2628 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL);
2629 if (!hw->buff)
2630 return -ENOMEM;
2631
2632 hw->dev = dev;
2633 hw->irq = irq;
2634 hw->regmap = regmap;
2635
2636 err = st_lsm6dsx_check_whoami(hw, hw_id, &name);
2637 if (err < 0)
2638 return err;
2639
2640 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) {
2641 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name);
2642 if (!hw->iio_devs[i])
2643 return -ENOMEM;
2644 }
2645
2646 err = st_lsm6dsx_init_device(hw);
2647 if (err < 0)
2648 return err;
2649
2650 hub_settings = &hw->settings->shub_settings;
2651 if (hub_settings->master_en.addr &&
2652 (!dev_fwnode(dev) ||
2653 !device_property_read_bool(dev, "st,disable-sensor-hub"))) {
2654 err = st_lsm6dsx_shub_probe(hw, name);
2655 if (err < 0)
2656 return err;
2657 }
2658
2659 if (hw->irq > 0) {
2660 err = st_lsm6dsx_irq_setup(hw);
2661 if (err < 0)
2662 return err;
2663
2664 err = st_lsm6dsx_fifo_setup(hw);
2665 if (err < 0)
2666 return err;
2667 }
2668
2669 if (!hw->irq || !hw->settings->fifo_ops.read_fifo) {
2670 /*
2671 * Rely on sw triggers (e.g. hr-timers) if irq pin is not
2672 * connected of if the device does not support HW FIFO
2673 */
2674 err = st_lsm6dsx_sw_buffers_setup(hw);
2675 if (err)
2676 return err;
2677 }
2678
2679 err = iio_read_mount_matrix(hw->dev, &hw->orientation);
2680 if (err)
2681 return err;
2682
2683 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2684 if (!hw->iio_devs[i])
2685 continue;
2686
2687 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]);
2688 if (err)
2689 return err;
2690 }
2691
2692 if ((dev_fwnode(dev) && device_property_read_bool(dev, "wakeup-source")) ||
2693 (pdata && pdata->wakeup_source))
2694 device_init_wakeup(dev, true);
2695
2696 return 0;
2697 }
2698 EXPORT_SYMBOL_NS(st_lsm6dsx_probe, IIO_LSM6DSX);
2699
st_lsm6dsx_suspend(struct device * dev)2700 static int st_lsm6dsx_suspend(struct device *dev)
2701 {
2702 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev);
2703 struct st_lsm6dsx_sensor *sensor;
2704 int i, err = 0;
2705
2706 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2707 if (!hw->iio_devs[i])
2708 continue;
2709
2710 sensor = iio_priv(hw->iio_devs[i]);
2711 if (!(hw->enable_mask & BIT(sensor->id)))
2712 continue;
2713
2714 if (device_may_wakeup(dev) &&
2715 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) {
2716 /* Enable wake from IRQ */
2717 enable_irq_wake(hw->irq);
2718 continue;
2719 }
2720
2721 err = st_lsm6dsx_device_set_enable(sensor, false);
2722 if (err < 0)
2723 return err;
2724
2725 hw->suspend_mask |= BIT(sensor->id);
2726 }
2727
2728 if (hw->fifo_mask)
2729 err = st_lsm6dsx_flush_fifo(hw);
2730
2731 return err;
2732 }
2733
st_lsm6dsx_resume(struct device * dev)2734 static int st_lsm6dsx_resume(struct device *dev)
2735 {
2736 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev);
2737 struct st_lsm6dsx_sensor *sensor;
2738 int i, err = 0;
2739
2740 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2741 if (!hw->iio_devs[i])
2742 continue;
2743
2744 sensor = iio_priv(hw->iio_devs[i]);
2745 if (device_may_wakeup(dev) &&
2746 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event)
2747 disable_irq_wake(hw->irq);
2748
2749 if (!(hw->suspend_mask & BIT(sensor->id)))
2750 continue;
2751
2752 err = st_lsm6dsx_device_set_enable(sensor, true);
2753 if (err < 0)
2754 return err;
2755
2756 hw->suspend_mask &= ~BIT(sensor->id);
2757 }
2758
2759 if (hw->fifo_mask)
2760 err = st_lsm6dsx_resume_fifo(hw);
2761
2762 return err;
2763 }
2764
2765 EXPORT_NS_SIMPLE_DEV_PM_OPS(st_lsm6dsx_pm_ops, st_lsm6dsx_suspend,
2766 st_lsm6dsx_resume, IIO_LSM6DSX);
2767
2768 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>");
2769 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>");
2770 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver");
2771 MODULE_LICENSE("GPL v2");
2772