1 /*
2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <drivers/clk.h>
10 #include <drivers/st/stm32_gpio.h>
11 #include <drivers/st/stm32_iwdg.h>
12 #include <lib/mmio.h>
13 #include <lib/xlat_tables/xlat_tables_v2.h>
14 #include <libfdt.h>
15
16 #include <plat/common/platform.h>
17 #include <platform_def.h>
18
19 /* Internal layout of the 32bit OTP word board_id */
20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
21 #define BOARD_ID_BOARD_NB_SHIFT 16
22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12)
23 #define BOARD_ID_VARCPN_SHIFT 12
24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8)
25 #define BOARD_ID_REVISION_SHIFT 8
26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4)
27 #define BOARD_ID_VARFG_SHIFT 4
28 #define BOARD_ID_BOM_MASK GENMASK(3, 0)
29
30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
31 BOARD_ID_BOARD_NB_SHIFT)
32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
33 BOARD_ID_VARCPN_SHIFT)
34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
35 BOARD_ID_REVISION_SHIFT)
36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
37 BOARD_ID_VARFG_SHIFT)
38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
39
40 #if STM32MP13
41 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30)
42 #endif
43 #if STM32MP15
44 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20)
45 #endif
46 #define TAMP_BOOT_MODE_ITF_MASK GENMASK(15, 8)
47 #define TAMP_BOOT_MODE_ITF_SHIFT 8
48 #define TAMP_BOOT_MODE_AUTH_MASK GENMASK(23, 16)
49 #define TAMP_BOOT_MODE_AUTH_SHIFT 16
50
51 /*
52 * Backup register to store fwu update information.
53 * It should be writeable only by secure world, but also readable by non secure
54 * (so it should be in Zone 2).
55 */
56 #define TAMP_BOOT_FWU_INFO_REG_ID U(10)
57 #define TAMP_BOOT_FWU_INFO_IDX_MSK GENMASK(3, 0)
58 #define TAMP_BOOT_FWU_INFO_IDX_OFF U(0)
59 #define TAMP_BOOT_FWU_INFO_CNT_MSK GENMASK(7, 4)
60 #define TAMP_BOOT_FWU_INFO_CNT_OFF U(4)
61
62 #if defined(IMAGE_BL2)
63 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
64 STM32MP_SYSRAM_SIZE, \
65 MT_MEMORY | \
66 MT_RW | \
67 MT_SECURE | \
68 MT_EXECUTE_NEVER)
69 #elif defined(IMAGE_BL32)
70 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \
71 STM32MP_SEC_SYSRAM_SIZE, \
72 MT_MEMORY | \
73 MT_RW | \
74 MT_SECURE | \
75 MT_EXECUTE_NEVER)
76
77 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */
78 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \
79 STM32MP_NS_SYSRAM_SIZE, \
80 MT_DEVICE | \
81 MT_RW | \
82 MT_NS | \
83 MT_EXECUTE_NEVER)
84 #endif
85
86 #if STM32MP13
87 #define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \
88 SRAMS_SIZE_2MB_ALIGNED, \
89 MT_MEMORY | \
90 MT_RW | \
91 MT_SECURE | \
92 MT_EXECUTE_NEVER)
93 #endif
94
95 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
96 STM32MP1_DEVICE1_SIZE, \
97 MT_DEVICE | \
98 MT_RW | \
99 MT_SECURE | \
100 MT_EXECUTE_NEVER)
101
102 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
103 STM32MP1_DEVICE2_SIZE, \
104 MT_DEVICE | \
105 MT_RW | \
106 MT_SECURE | \
107 MT_EXECUTE_NEVER)
108
109 #if defined(IMAGE_BL2)
110 static const mmap_region_t stm32mp1_mmap[] = {
111 MAP_SEC_SYSRAM,
112 #if STM32MP13
113 MAP_SRAM_ALL,
114 #endif
115 MAP_DEVICE1,
116 #if STM32MP_RAW_NAND
117 MAP_DEVICE2,
118 #endif
119 {0}
120 };
121 #endif
122 #if defined(IMAGE_BL32)
123 static const mmap_region_t stm32mp1_mmap[] = {
124 MAP_SEC_SYSRAM,
125 MAP_NS_SYSRAM,
126 MAP_DEVICE1,
127 MAP_DEVICE2,
128 {0}
129 };
130 #endif
131
configure_mmu(void)132 void configure_mmu(void)
133 {
134 mmap_add(stm32mp1_mmap);
135 init_xlat_tables();
136
137 enable_mmu_svc_mon(0);
138 }
139
stm32_get_gpio_bank_base(unsigned int bank)140 uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
141 {
142 #if STM32MP13
143 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
144 #endif
145 #if STM32MP15
146 if (bank == GPIO_BANK_Z) {
147 return GPIOZ_BASE;
148 }
149
150 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
151 #endif
152
153 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
154 }
155
stm32_get_gpio_bank_offset(unsigned int bank)156 uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
157 {
158 #if STM32MP13
159 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
160 #endif
161 #if STM32MP15
162 if (bank == GPIO_BANK_Z) {
163 return 0;
164 }
165
166 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
167 #endif
168
169 return bank * GPIO_BANK_OFFSET;
170 }
171
stm32_gpio_is_secure_at_reset(unsigned int bank)172 bool stm32_gpio_is_secure_at_reset(unsigned int bank)
173 {
174 #if STM32MP13
175 return true;
176 #endif
177 #if STM32MP15
178 if (bank == GPIO_BANK_Z) {
179 return true;
180 }
181
182 return false;
183 #endif
184 }
185
stm32_get_gpio_bank_clock(unsigned int bank)186 unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
187 {
188 #if STM32MP13
189 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
190 #endif
191 #if STM32MP15
192 if (bank == GPIO_BANK_Z) {
193 return GPIOZ;
194 }
195
196 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
197 #endif
198
199 return GPIOA + (bank - GPIO_BANK_A);
200 }
201
stm32_get_gpio_bank_pinctrl_node(void * fdt,unsigned int bank)202 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank)
203 {
204 const char *node_compatible = NULL;
205
206 switch (bank) {
207 case GPIO_BANK_A:
208 case GPIO_BANK_B:
209 case GPIO_BANK_C:
210 case GPIO_BANK_D:
211 case GPIO_BANK_E:
212 case GPIO_BANK_F:
213 case GPIO_BANK_G:
214 case GPIO_BANK_H:
215 case GPIO_BANK_I:
216 #if STM32MP13
217 node_compatible = "st,stm32mp135-pinctrl";
218 break;
219 #endif
220 #if STM32MP15
221 case GPIO_BANK_J:
222 case GPIO_BANK_K:
223 node_compatible = "st,stm32mp157-pinctrl";
224 break;
225 case GPIO_BANK_Z:
226 node_compatible = "st,stm32mp157-z-pinctrl";
227 break;
228 #endif
229 default:
230 panic();
231 }
232
233 return fdt_node_offset_by_compatible(fdt, -1, node_compatible);
234 }
235
236 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
237 /*
238 * UART Management
239 */
240 static const uintptr_t stm32mp1_uart_addresses[8] = {
241 USART1_BASE,
242 USART2_BASE,
243 USART3_BASE,
244 UART4_BASE,
245 UART5_BASE,
246 USART6_BASE,
247 UART7_BASE,
248 UART8_BASE,
249 };
250
get_uart_address(uint32_t instance_nb)251 uintptr_t get_uart_address(uint32_t instance_nb)
252 {
253 if ((instance_nb == 0U) ||
254 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) {
255 return 0U;
256 }
257
258 return stm32mp1_uart_addresses[instance_nb - 1U];
259 }
260 #endif
261
262 #if STM32MP_USB_PROGRAMMER
263 struct gpio_bank_pin_list {
264 uint32_t bank;
265 uint32_t pin;
266 };
267
268 static const struct gpio_bank_pin_list gpio_list[] = {
269 { /* USART2_RX: GPIOA3 */
270 .bank = 0U,
271 .pin = 3U,
272 },
273 { /* USART3_RX: GPIOB12 */
274 .bank = 1U,
275 .pin = 12U,
276 },
277 { /* UART4_RX: GPIOB2 */
278 .bank = 1U,
279 .pin = 2U,
280 },
281 { /* UART5_RX: GPIOB4 */
282 .bank = 1U,
283 .pin = 5U,
284 },
285 { /* USART6_RX: GPIOC7 */
286 .bank = 2U,
287 .pin = 7U,
288 },
289 { /* UART7_RX: GPIOF6 */
290 .bank = 5U,
291 .pin = 6U,
292 },
293 { /* UART8_RX: GPIOE0 */
294 .bank = 4U,
295 .pin = 0U,
296 },
297 };
298
stm32mp1_deconfigure_uart_pins(void)299 void stm32mp1_deconfigure_uart_pins(void)
300 {
301 size_t i;
302
303 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) {
304 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin);
305 }
306 }
307 #endif
308
stm32mp_get_chip_version(void)309 uint32_t stm32mp_get_chip_version(void)
310 {
311 #if STM32MP13
312 return stm32mp1_syscfg_get_chip_version();
313 #endif
314 #if STM32MP15
315 uint32_t version = 0U;
316
317 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) {
318 INFO("Cannot get CPU version, debug disabled\n");
319 return 0U;
320 }
321
322 return version;
323 #endif
324 }
325
stm32mp_get_chip_dev_id(void)326 uint32_t stm32mp_get_chip_dev_id(void)
327 {
328 #if STM32MP13
329 return stm32mp1_syscfg_get_chip_dev_id();
330 #endif
331 #if STM32MP15
332 uint32_t dev_id;
333
334 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
335 INFO("Use default chip ID, debug disabled\n");
336 dev_id = STM32MP1_CHIP_ID;
337 }
338
339 return dev_id;
340 #endif
341 }
342
get_part_number(void)343 static uint32_t get_part_number(void)
344 {
345 static uint32_t part_number;
346
347 if (part_number != 0U) {
348 return part_number;
349 }
350
351 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) {
352 panic();
353 }
354
355 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
356 PART_NUMBER_OTP_PART_SHIFT;
357
358 part_number |= stm32mp_get_chip_dev_id() << 16;
359
360 return part_number;
361 }
362
363 #if STM32MP15
get_cpu_package(void)364 static uint32_t get_cpu_package(void)
365 {
366 uint32_t package;
367
368 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) {
369 panic();
370 }
371
372 package = (package & PACKAGE_OTP_PKG_MASK) >>
373 PACKAGE_OTP_PKG_SHIFT;
374
375 return package;
376 }
377 #endif
378
stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])379 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
380 {
381 char *cpu_s, *cpu_r, *pkg;
382
383 /* MPUs Part Numbers */
384 switch (get_part_number()) {
385 #if STM32MP13
386 case STM32MP135F_PART_NB:
387 cpu_s = "135F";
388 break;
389 case STM32MP135D_PART_NB:
390 cpu_s = "135D";
391 break;
392 case STM32MP135C_PART_NB:
393 cpu_s = "135C";
394 break;
395 case STM32MP135A_PART_NB:
396 cpu_s = "135A";
397 break;
398 case STM32MP133F_PART_NB:
399 cpu_s = "133F";
400 break;
401 case STM32MP133D_PART_NB:
402 cpu_s = "133D";
403 break;
404 case STM32MP133C_PART_NB:
405 cpu_s = "133C";
406 break;
407 case STM32MP133A_PART_NB:
408 cpu_s = "133A";
409 break;
410 case STM32MP131F_PART_NB:
411 cpu_s = "131F";
412 break;
413 case STM32MP131D_PART_NB:
414 cpu_s = "131D";
415 break;
416 case STM32MP131C_PART_NB:
417 cpu_s = "131C";
418 break;
419 case STM32MP131A_PART_NB:
420 cpu_s = "131A";
421 break;
422 #endif
423 #if STM32MP15
424 case STM32MP157C_PART_NB:
425 cpu_s = "157C";
426 break;
427 case STM32MP157A_PART_NB:
428 cpu_s = "157A";
429 break;
430 case STM32MP153C_PART_NB:
431 cpu_s = "153C";
432 break;
433 case STM32MP153A_PART_NB:
434 cpu_s = "153A";
435 break;
436 case STM32MP151C_PART_NB:
437 cpu_s = "151C";
438 break;
439 case STM32MP151A_PART_NB:
440 cpu_s = "151A";
441 break;
442 case STM32MP157F_PART_NB:
443 cpu_s = "157F";
444 break;
445 case STM32MP157D_PART_NB:
446 cpu_s = "157D";
447 break;
448 case STM32MP153F_PART_NB:
449 cpu_s = "153F";
450 break;
451 case STM32MP153D_PART_NB:
452 cpu_s = "153D";
453 break;
454 case STM32MP151F_PART_NB:
455 cpu_s = "151F";
456 break;
457 case STM32MP151D_PART_NB:
458 cpu_s = "151D";
459 break;
460 #endif
461 default:
462 cpu_s = "????";
463 break;
464 }
465
466 /* Package */
467 #if STM32MP13
468 /* On STM32MP13, package is not present in OTP */
469 pkg = "";
470 #endif
471 #if STM32MP15
472 switch (get_cpu_package()) {
473 case PKG_AA_LFBGA448:
474 pkg = "AA";
475 break;
476 case PKG_AB_LFBGA354:
477 pkg = "AB";
478 break;
479 case PKG_AC_TFBGA361:
480 pkg = "AC";
481 break;
482 case PKG_AD_TFBGA257:
483 pkg = "AD";
484 break;
485 default:
486 pkg = "??";
487 break;
488 }
489 #endif
490
491 /* REVISION */
492 switch (stm32mp_get_chip_version()) {
493 case STM32MP1_REV_B:
494 cpu_r = "B";
495 break;
496 #if STM32MP13
497 case STM32MP1_REV_Y:
498 cpu_r = "Y";
499 break;
500 #endif
501 case STM32MP1_REV_Z:
502 cpu_r = "Z";
503 break;
504 default:
505 cpu_r = "?";
506 break;
507 }
508
509 snprintf(name, STM32_SOC_NAME_SIZE,
510 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
511 }
512
stm32mp_print_cpuinfo(void)513 void stm32mp_print_cpuinfo(void)
514 {
515 char name[STM32_SOC_NAME_SIZE];
516
517 stm32mp_get_soc_name(name);
518 NOTICE("CPU: %s\n", name);
519 }
520
stm32mp_print_boardinfo(void)521 void stm32mp_print_boardinfo(void)
522 {
523 uint32_t board_id = 0;
524
525 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) {
526 return;
527 }
528
529 if (board_id != 0U) {
530 char rev[2];
531
532 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
533 rev[1] = '\0';
534 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
535 BOARD_ID2NB(board_id),
536 BOARD_ID2VARCPN(board_id),
537 BOARD_ID2VARFG(board_id),
538 rev,
539 BOARD_ID2BOM(board_id));
540 }
541 }
542
543 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
stm32mp_is_single_core(void)544 bool stm32mp_is_single_core(void)
545 {
546 #if STM32MP13
547 return true;
548 #endif
549 #if STM32MP15
550 bool single_core = false;
551
552 switch (get_part_number()) {
553 case STM32MP151A_PART_NB:
554 case STM32MP151C_PART_NB:
555 case STM32MP151D_PART_NB:
556 case STM32MP151F_PART_NB:
557 single_core = true;
558 break;
559 default:
560 break;
561 }
562
563 return single_core;
564 #endif
565 }
566
567 /* Return true when device is in closed state */
stm32mp_is_closed_device(void)568 bool stm32mp_is_closed_device(void)
569 {
570 uint32_t value;
571
572 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) {
573 return true;
574 }
575
576 #if STM32MP13
577 value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT;
578
579 switch (value) {
580 case CFG0_OPEN_DEVICE:
581 return false;
582 case CFG0_CLOSED_DEVICE:
583 case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN:
584 case CFG0_CLOSED_DEVICE_NO_JTAG:
585 return true;
586 default:
587 panic();
588 }
589 #endif
590 #if STM32MP15
591 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE;
592 #endif
593 }
594
595 /* Return true when device supports secure boot */
stm32mp_is_auth_supported(void)596 bool stm32mp_is_auth_supported(void)
597 {
598 bool supported = false;
599
600 switch (get_part_number()) {
601 #if STM32MP13
602 case STM32MP131C_PART_NB:
603 case STM32MP131F_PART_NB:
604 case STM32MP133C_PART_NB:
605 case STM32MP133F_PART_NB:
606 case STM32MP135C_PART_NB:
607 case STM32MP135F_PART_NB:
608 #endif
609 #if STM32MP15
610 case STM32MP151C_PART_NB:
611 case STM32MP151F_PART_NB:
612 case STM32MP153C_PART_NB:
613 case STM32MP153F_PART_NB:
614 case STM32MP157C_PART_NB:
615 case STM32MP157F_PART_NB:
616 #endif
617 supported = true;
618 break;
619 default:
620 break;
621 }
622
623 return supported;
624 }
625
stm32_iwdg_get_instance(uintptr_t base)626 uint32_t stm32_iwdg_get_instance(uintptr_t base)
627 {
628 switch (base) {
629 case IWDG1_BASE:
630 return IWDG1_INST;
631 case IWDG2_BASE:
632 return IWDG2_INST;
633 default:
634 panic();
635 }
636 }
637
stm32_iwdg_get_otp_config(uint32_t iwdg_inst)638 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
639 {
640 uint32_t iwdg_cfg = 0U;
641 uint32_t otp_value;
642
643 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) {
644 panic();
645 }
646
647 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) {
648 iwdg_cfg |= IWDG_HW_ENABLED;
649 }
650
651 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) {
652 iwdg_cfg |= IWDG_DISABLE_ON_STOP;
653 }
654
655 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) {
656 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
657 }
658
659 return iwdg_cfg;
660 }
661
662 #if defined(IMAGE_BL2)
stm32_iwdg_shadow_update(uint32_t iwdg_inst,uint32_t flags)663 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
664 {
665 uint32_t otp_value;
666 uint32_t otp;
667 uint32_t result;
668
669 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) {
670 panic();
671 }
672
673 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) {
674 panic();
675 }
676
677 if ((flags & IWDG_DISABLE_ON_STOP) != 0) {
678 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS);
679 }
680
681 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) {
682 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS);
683 }
684
685 result = bsec_write_otp(otp_value, otp);
686 if (result != BSEC_OK) {
687 return result;
688 }
689
690 /* Sticky lock OTP_IWDG (read and write) */
691 if ((bsec_set_sr_lock(otp) != BSEC_OK) ||
692 (bsec_set_sw_lock(otp) != BSEC_OK)) {
693 return BSEC_LOCK_FAIL;
694 }
695
696 return BSEC_OK;
697 }
698 #endif
699
stm32_save_boot_interface(uint32_t interface,uint32_t instance)700 void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
701 {
702 uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
703
704 clk_enable(RTCAPB);
705
706 mmio_clrsetbits_32(bkpr_itf_idx,
707 TAMP_BOOT_MODE_ITF_MASK,
708 ((interface << 4) | (instance & 0xFU)) <<
709 TAMP_BOOT_MODE_ITF_SHIFT);
710
711 clk_disable(RTCAPB);
712 }
713
stm32_get_boot_interface(uint32_t * interface,uint32_t * instance)714 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
715 {
716 static uint32_t itf;
717
718 if (itf == 0U) {
719 uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
720
721 clk_enable(RTCAPB);
722
723 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >>
724 TAMP_BOOT_MODE_ITF_SHIFT;
725
726 clk_disable(RTCAPB);
727 }
728
729 *interface = itf >> 4;
730 *instance = itf & 0xFU;
731 }
732
stm32_save_boot_auth(uint32_t auth_status,uint32_t boot_partition)733 void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition)
734 {
735 uint32_t boot_status = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
736
737 clk_enable(RTCAPB);
738
739 mmio_clrsetbits_32(boot_status,
740 TAMP_BOOT_MODE_AUTH_MASK,
741 ((auth_status << 4) | (boot_partition & 0xFU)) <<
742 TAMP_BOOT_MODE_AUTH_SHIFT);
743
744 clk_disable(RTCAPB);
745 }
746
747 #if PSA_FWU_SUPPORT
stm32mp1_fwu_set_boot_idx(void)748 void stm32mp1_fwu_set_boot_idx(void)
749 {
750 clk_enable(RTCAPB);
751 mmio_clrsetbits_32(tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID),
752 TAMP_BOOT_FWU_INFO_IDX_MSK,
753 (plat_fwu_get_boot_idx() << TAMP_BOOT_FWU_INFO_IDX_OFF) &
754 TAMP_BOOT_FWU_INFO_IDX_MSK);
755 clk_disable(RTCAPB);
756 }
757
stm32_get_and_dec_fwu_trial_boot_cnt(void)758 uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void)
759 {
760 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
761 uint32_t try_cnt;
762
763 clk_enable(RTCAPB);
764 try_cnt = (mmio_read_32(bkpr_fwu_cnt) & TAMP_BOOT_FWU_INFO_CNT_MSK) >>
765 TAMP_BOOT_FWU_INFO_CNT_OFF;
766
767 assert(try_cnt <= FWU_MAX_TRIAL_REBOOT);
768
769 if (try_cnt != 0U) {
770 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK,
771 (try_cnt - 1U) << TAMP_BOOT_FWU_INFO_CNT_OFF);
772 }
773 clk_disable(RTCAPB);
774
775 return try_cnt;
776 }
777
stm32_set_max_fwu_trial_boot_cnt(void)778 void stm32_set_max_fwu_trial_boot_cnt(void)
779 {
780 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
781
782 clk_enable(RTCAPB);
783 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK,
784 (FWU_MAX_TRIAL_REBOOT << TAMP_BOOT_FWU_INFO_CNT_OFF) &
785 TAMP_BOOT_FWU_INFO_CNT_MSK);
786 clk_disable(RTCAPB);
787 }
788 #endif /* PSA_FWU_SUPPORT */
789