1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2018-2019, STMicroelectronics
4 */
5
6 #include <drivers/stm32mp1_pwr.h>
7 #include <io.h>
8 #include <kernel/delay.h>
9 #include <kernel/panic.h>
10 #include <mm/core_memprot.h>
11 #include <platform_config.h>
12
13 #define PWR_CR3_USB33_EN BIT(24)
14 #define PWR_CR3_USB33_RDY BIT(26)
15 #define PWR_CR3_REG18_EN BIT(28)
16 #define PWR_CR3_REG18_RDY BIT(29)
17 #define PWR_CR3_REG11_EN BIT(30)
18 #define PWR_CR3_REG11_RDY BIT(31)
19
20 struct pwr_regu_desc {
21 unsigned int level_mv;
22 uint32_t cr3_enable_mask;
23 uint32_t cr3_ready_mask;
24 };
25
26 static const struct pwr_regu_desc pwr_regulators[PWR_REGU_COUNT] = {
27 [PWR_REG11] = {
28 .level_mv = 1100,
29 .cr3_enable_mask = PWR_CR3_REG11_EN,
30 .cr3_ready_mask = PWR_CR3_REG11_RDY,
31 },
32 [PWR_REG18] = {
33 .level_mv = 1800,
34 .cr3_enable_mask = PWR_CR3_REG18_EN,
35 .cr3_ready_mask = PWR_CR3_REG18_RDY,
36 },
37 [PWR_USB33] = {
38 .level_mv = 3300,
39 .cr3_enable_mask = PWR_CR3_USB33_EN,
40 .cr3_ready_mask = PWR_CR3_USB33_RDY,
41 },
42 };
43
stm32_pwr_base(void)44 vaddr_t stm32_pwr_base(void)
45 {
46 static struct io_pa_va base = { .pa = PWR_BASE };
47
48 return io_pa_or_va_secure(&base, 1);
49 }
50
stm32mp1_pwr_regulator_mv(enum pwr_regulator id)51 unsigned int stm32mp1_pwr_regulator_mv(enum pwr_regulator id)
52 {
53 assert(id < PWR_REGU_COUNT);
54
55 return pwr_regulators[id].level_mv;
56 }
57
stm32mp1_pwr_regulator_set_state(enum pwr_regulator id,bool enable)58 void stm32mp1_pwr_regulator_set_state(enum pwr_regulator id, bool enable)
59 {
60 uintptr_t cr3 = stm32_pwr_base() + PWR_CR3_OFF;
61 uint32_t enable_mask = pwr_regulators[id].cr3_enable_mask;
62
63 assert(id < PWR_REGU_COUNT);
64
65 if (enable) {
66 uint64_t to = timeout_init_us(10 * 1000);
67 uint32_t ready_mask = pwr_regulators[id].cr3_ready_mask;
68
69 io_setbits32(cr3, enable_mask);
70
71 while (!timeout_elapsed(to))
72 if (io_read32(cr3) & ready_mask)
73 break;
74
75 if (!(io_read32(cr3) & ready_mask))
76 panic();
77 } else {
78 io_clrbits32(cr3, enable_mask);
79 }
80 }
81
stm32mp1_pwr_regulator_is_enabled(enum pwr_regulator id)82 bool stm32mp1_pwr_regulator_is_enabled(enum pwr_regulator id)
83 {
84 assert(id < PWR_REGU_COUNT);
85
86 return io_read32(stm32_pwr_base() + PWR_CR3_OFF) &
87 pwr_regulators[id].cr3_enable_mask;
88 }
89