1 /*
2  * Renesas SCP/MCP Software
3  * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights
4  * reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef MOD_RCAR_SD_CLOCK_H
10 #define MOD_RCAR_SD_CLOCK_H
11 
12 #include <clock_sd_devices.h>
13 #include <rcar_mmap.h>
14 
15 #include <mod_clock.h>
16 #include <mod_rcar_clock.h>
17 
18 #include <fwk_element.h>
19 
20 #include <stdint.h>
21 
22 /*!
23  * \addtogroup GroupRCARModule RCAR Product Modules
24  * @{
25  */
26 
27 /*!
28  * \defgroup GroupRCARSdClock SD clock
29  * @{
30  */
31 
32 /*!
33  * \brief Rate lookup entry.
34  */
35 struct mod_rcar_sd_clock_rate {
36     /*! Divider used to obtain the rate value. */
37     uint32_t divider_num;
38     /*! Value to be set for the divider. */
39     uint32_t divider;
40     /*! Divider maskbit value. */
41     uint32_t divider_mask;
42 };
43 
44 /*!
45  * \brief Subsystem clock device configuration.
46  */
47 struct mod_rcar_sd_clock_dev_config {
48     /*! The type of the clock device. */
49     enum mod_rcar_clock_type type;
50 
51     /*! Pointer to the clock's control register. */
52     volatile uint32_t const control_reg;
53 
54     /*! enable / disable bit position. */
55     volatile bool stop_clk;
56 
57     /*! enable / disable bit position. */
58     volatile uint32_t const stop_clk_bit;
59 
60     /*! Parent clock id. */
61     uint32_t parent;
62 
63     /*! Required initialization Clock divider. */
64     bool need_hardware_init;
65 
66     /*! Fixed Clock divider. */
67     uint32_t div;
68 
69     /*! Fixed Clock divider. */
70     uint32_t multi;
71 
72     /*! The type of rates the clock provides (discrete or continuous) */
73     enum mod_clock_rate_type rate_type;
74 
75     /*! Pointer to the clock's rate lookup table. */
76     const struct mod_rcar_sd_clock_rate *rate_table;
77 
78     /*! The number of rates in the rate lookup table. */
79     uint32_t rate_count;
80 };
81 
82 /*!
83  * @cond
84  */
85 
86 /* Device context */
87 struct rcar_sd_clock_dev_ctx {
88     bool initialized;
89     uint64_t current_rate;
90     uint64_t *rate_table;
91     enum mod_clock_state current_state;
92     const struct mod_rcar_sd_clock_dev_config *config;
93 };
94 
95 /* Module context */
96 struct rcar_sd_clock_ctx {
97     struct rcar_sd_clock_dev_ctx *dev_ctx_table;
98     unsigned int dev_count;
99     uint32_t parent_clk[CLOCK_PARENT_IDX_COUNT];
100 };
101 
102 struct rcar_gen3_cpg_pll_config {
103     char extal_div;
104     char pll1_mult;
105     char pll1_div;
106     char pll3_mult;
107     char pll3_div;
108     char osc_prediv;
109 };
110 
111 /* control register */
112 #define CPG_SD0CKCR (CPG_BASE + 0x0074)
113 #define CPG_SD1CKCR (CPG_BASE + 0x0078)
114 #define CPG_SD2CKCR (CPG_BASE + 0x0268)
115 #define CPG_SD3CKCR (CPG_BASE + 0x026C)
116 #define CPG_SDNCKCR_MASK 0x1F
117 #define CPG_SDNCKCR_SD_64 0x11
118 #define CPG_SDNCKCR_SD_32 0xD
119 #define CPG_SDNCKCR_SD_16 0x9
120 #define CPG_SDNCKCR_SD_8 0x5
121 #define CPG_SDNCKCR_SD_4 0x1
122 #define CPG_SDNCKCR_SD_2 0x0
123 
124 #define CPG_CANFDCKCR (CPG_BASE + 0x0244)
125 #define CPG_CSI0CKCR (CPG_BASE + 0x000C)
126 #define CPG_MSOCKCR (CPG_BASE + 0x0014)
127 #define CPG_HDMICKCR (CPG_BASE + 0x0250)
128 #define CPG_CON_MASK 0x3F
129 #define CPG_CON_MAX 64
130 
131 #define CPG_FRQCRB_ZTRFC_MASK 0xF00000
132 #define CPG_FRQCRB_ZTRFC_24 0x800000
133 #define CPG_FRQCRB_ZTRFC_18 0x700000
134 #define CPG_FRQCRB_ZTRFC_16 0x600000
135 #define CPG_FRQCRB_ZTRFC_12 0x500000
136 #define CPG_FRQCRB_ZTRFC_8 0x400000
137 #define CPG_FRQCRB_ZTRFC_6 0x300000
138 #define CPG_FRQCRB_ZTFC_MASK 0xF0000
139 #define CPG_FRQCRB_ZTFC_24 0x80000
140 #define CPG_FRQCRB_ZTFC_18 0x70000
141 #define CPG_FRQCRB_ZTFC_16 0x60000
142 #define CPG_FRQCRB_ZTFC_12 0x50000
143 #define CPG_FRQCRB_ZTFC_8 0x40000
144 #define CPG_FRQCRB_ZTFC_6 0x30000
145 #define CPG_FRQCRB_ZTFC_4 0x20000
146 #define CPG_FRQCRB_ZTRD2FC_MASK 0xF
147 #define CPG_FRQCRB_ZTRD2FC_24 0x8
148 #define CPG_FRQCRB_ZTRD2FC_18 0x7
149 #define CPG_FRQCRB_ZTRD2FC_16 0x6
150 #define CPG_FRQCRB_ZTRD2FC_12 0x5
151 
152 #define CPG_PLL_CONFIG_INDEX(md) \
153     ((((md)&BIT(14)) >> 11) | (((md)&BIT(13)) >> 11) | \
154      (((md)&BIT(19)) >> 18) | (((md)&BIT(17)) >> 17))
155 
156 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
157     /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
158     {
159         1,
160         192,
161         1,
162         192,
163         1,
164         16,
165     },
166     {
167         1,
168         192,
169         1,
170         128,
171         1,
172         16,
173     },
174     { 0, /* Prohibited setting */ },
175     {
176         1,
177         192,
178         1,
179         192,
180         1,
181         16,
182     },
183     {
184         1,
185         160,
186         1,
187         160,
188         1,
189         19,
190     },
191     {
192         1,
193         160,
194         1,
195         106,
196         1,
197         19,
198     },
199     { 0, /* Prohibited setting */ },
200     {
201         1,
202         160,
203         1,
204         160,
205         1,
206         19,
207     },
208     {
209         1,
210         128,
211         1,
212         128,
213         1,
214         24,
215     },
216     {
217         1,
218         128,
219         1,
220         84,
221         1,
222         24,
223     },
224     { 0, /* Prohibited setting */ },
225     {
226         1,
227         128,
228         1,
229         128,
230         1,
231         24,
232     },
233     {
234         2,
235         192,
236         1,
237         192,
238         1,
239         32,
240     },
241     {
242         2,
243         192,
244         1,
245         128,
246         1,
247         32,
248     },
249     { 0, /* Prohibited setting */ },
250     {
251         2,
252         192,
253         1,
254         192,
255         1,
256         32,
257     },
258 };
259 
260 /*!
261  * @endcond
262  */
263 
264 /*!
265  * @}
266  */
267 
268 /*!
269  * @}
270  */
271 
272 #endif /* MOD_RCAR_SD_CLOCK_H */
273