1 /*
2  * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <platform_def.h>
10 
11 #include <common/debug.h>
12 #include <common/fdt_fixup.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15 
16 #include <sunxi_cpucfg.h>
17 #include <sunxi_private.h>
18 
19 static bool psci_is_scpi;
20 
21 #if SUNXI_PSCI_USE_SCPI
sunxi_psci_is_scpi(void)22 bool sunxi_psci_is_scpi(void)
23 {
24 	return psci_is_scpi;
25 }
26 #endif
27 
sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)28 int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
29 {
30 	/* The non-secure entry point must be in DRAM */
31 	if (ns_entrypoint < SUNXI_DRAM_BASE) {
32 		return PSCI_E_INVALID_ADDRESS;
33 	}
34 
35 	return PSCI_E_SUCCESS;
36 }
37 
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)38 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
39 			const plat_psci_ops_t **psci_ops)
40 {
41 	assert(psci_ops);
42 
43 	/* Program all CPU entry points. */
44 	for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) {
45 		mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
46 			      sec_entrypoint & 0xffffffff);
47 		mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
48 			      sec_entrypoint >> 32);
49 	}
50 
51 	if (sunxi_set_scpi_psci_ops(psci_ops) == 0) {
52 		INFO("PSCI: Suspend is available via SCPI\n");
53 		psci_is_scpi = true;
54 	} else {
55 		INFO("PSCI: Suspend is unavailable\n");
56 		sunxi_set_native_psci_ops(psci_ops);
57 	}
58 
59 	return 0;
60 }
61