1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH11K_HW_H
8 #define ATH11K_HW_H
9
10 #include "hal.h"
11 #include "wmi.h"
12
13 /* Target configuration defines */
14
15 /* Num VDEVS per radio */
16 #define TARGET_NUM_VDEVS(ab) (ab->hw_params.num_vdevs)
17
18 #define TARGET_NUM_PEERS_PDEV(ab) (ab->hw_params.num_peers + TARGET_NUM_VDEVS(ab))
19
20 /* Num of peers for Single Radio mode */
21 #define TARGET_NUM_PEERS_SINGLE(ab) (TARGET_NUM_PEERS_PDEV(ab))
22
23 /* Num of peers for DBS */
24 #define TARGET_NUM_PEERS_DBS(ab) (2 * TARGET_NUM_PEERS_PDEV(ab))
25
26 /* Num of peers for DBS_SBS */
27 #define TARGET_NUM_PEERS_DBS_SBS(ab) (3 * TARGET_NUM_PEERS_PDEV(ab))
28
29 /* Max num of stations (per radio) */
30 #define TARGET_NUM_STATIONS(ab) (ab->hw_params.num_peers)
31
32 #define TARGET_NUM_PEERS(ab, x) TARGET_NUM_PEERS_##x(ab)
33 #define TARGET_NUM_PEER_KEYS 2
34 #define TARGET_NUM_TIDS(ab, x) (2 * TARGET_NUM_PEERS(ab, x) + \
35 4 * TARGET_NUM_VDEVS(ab) + 8)
36
37 #define TARGET_AST_SKID_LIMIT 16
38 #define TARGET_NUM_OFFLD_PEERS 4
39 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
40
41 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
42 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
43 #define TARGET_RX_TIMEOUT_LO_PRI 100
44 #define TARGET_RX_TIMEOUT_HI_PRI 40
45
46 #define TARGET_DECAP_MODE_RAW 0
47 #define TARGET_DECAP_MODE_NATIVE_WIFI 1
48 #define TARGET_DECAP_MODE_ETH 2
49
50 #define TARGET_SCAN_MAX_PENDING_REQS 4
51 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
52 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
53 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
54 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
55 #define TARGET_NUM_MCAST_GROUPS 12
56 #define TARGET_NUM_MCAST_TABLE_ELEMS 64
57 #define TARGET_MCAST2UCAST_MODE 2
58 #define TARGET_TX_DBG_LOG_SIZE 1024
59 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
60 #define TARGET_VOW_CONFIG 0
61 #define TARGET_NUM_MSDU_DESC (2500)
62 #define TARGET_MAX_FRAG_ENTRIES 6
63 #define TARGET_MAX_BCN_OFFLD 16
64 #define TARGET_NUM_WDS_ENTRIES 32
65 #define TARGET_DMA_BURST_SIZE 1
66 #define TARGET_RX_BATCHMODE 1
67
68 #define ATH11K_HW_MAX_QUEUES 4
69 #define ATH11K_QUEUE_LEN 4096
70
71 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
72
73 #define ATH11K_FW_DIR "ath11k"
74
75 #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD"
76 #define ATH11K_BOARD_API2_FILE "board-2.bin"
77 #define ATH11K_DEFAULT_BOARD_FILE "board.bin"
78 #define ATH11K_DEFAULT_CAL_FILE "caldata.bin"
79 #define ATH11K_AMSS_FILE "amss.bin"
80 #define ATH11K_M3_FILE "m3.bin"
81 #define ATH11K_REGDB_FILE_NAME "regdb.bin"
82
83 #define ATH11K_CE_OFFSET(ab) (ab->mem_ce - ab->mem)
84
85 enum ath11k_hw_rate_cck {
86 ATH11K_HW_RATE_CCK_LP_11M = 0,
87 ATH11K_HW_RATE_CCK_LP_5_5M,
88 ATH11K_HW_RATE_CCK_LP_2M,
89 ATH11K_HW_RATE_CCK_LP_1M,
90 ATH11K_HW_RATE_CCK_SP_11M,
91 ATH11K_HW_RATE_CCK_SP_5_5M,
92 ATH11K_HW_RATE_CCK_SP_2M,
93 };
94
95 enum ath11k_hw_rate_ofdm {
96 ATH11K_HW_RATE_OFDM_48M = 0,
97 ATH11K_HW_RATE_OFDM_24M,
98 ATH11K_HW_RATE_OFDM_12M,
99 ATH11K_HW_RATE_OFDM_6M,
100 ATH11K_HW_RATE_OFDM_54M,
101 ATH11K_HW_RATE_OFDM_36M,
102 ATH11K_HW_RATE_OFDM_18M,
103 ATH11K_HW_RATE_OFDM_9M,
104 };
105
106 enum ath11k_bus {
107 ATH11K_BUS_AHB,
108 ATH11K_BUS_PCI,
109 };
110
111 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
112
113 struct hal_rx_desc;
114 struct hal_tcl_data_cmd;
115
116 struct ath11k_hw_ring_mask {
117 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
118 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
119 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
120 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];
121 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];
122 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
123 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];
124 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];
125 };
126
127 struct ath11k_hw_tcl2wbm_rbm_map {
128 u8 tcl_ring_num;
129 u8 wbm_ring_num;
130 u8 rbm_id;
131 };
132
133 struct ath11k_hw_hal_params {
134 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
135 const struct ath11k_hw_tcl2wbm_rbm_map *tcl2wbm_rbm_map;
136 };
137
138 struct ath11k_hw_params {
139 const char *name;
140 u16 hw_rev;
141 u8 max_radios;
142 u32 bdf_addr;
143
144 struct {
145 const char *dir;
146 size_t board_size;
147 size_t cal_offset;
148 } fw;
149
150 const struct ath11k_hw_ops *hw_ops;
151 const struct ath11k_hw_ring_mask *ring_mask;
152
153 bool internal_sleep_clock;
154
155 const struct ath11k_hw_regs *regs;
156 u32 qmi_service_ins_id;
157 const struct ce_attr *host_ce_config;
158 u32 ce_count;
159 const struct ce_pipe_config *target_ce_config;
160 u32 target_ce_count;
161 const struct service_to_pipe *svc_to_ce_map;
162 u32 svc_to_ce_map_len;
163 const struct ce_ie_addr *ce_ie_addr;
164 const struct ce_remap *ce_remap;
165
166 bool single_pdev_only;
167
168 bool rxdma1_enable;
169 int num_rxmda_per_pdev;
170 bool rx_mac_buf_ring;
171 bool vdev_start_delay;
172 bool htt_peer_map_v2;
173
174 struct {
175 u8 fft_sz;
176 u8 fft_pad_sz;
177 u8 summary_pad_sz;
178 u8 fft_hdr_len;
179 u16 max_fft_bins;
180 bool fragment_160mhz;
181 } spectral;
182
183 u16 interface_modes;
184 bool supports_monitor;
185 bool full_monitor_mode;
186 bool supports_shadow_regs;
187 bool idle_ps;
188 bool supports_sta_ps;
189 bool cold_boot_calib;
190 bool cbcal_restart_fw;
191 int fw_mem_mode;
192 u32 num_vdevs;
193 u32 num_peers;
194 bool supports_suspend;
195 u32 hal_desc_sz;
196 bool supports_regdb;
197 bool fix_l1ss;
198 bool credit_flow;
199 u8 max_tx_ring;
200 const struct ath11k_hw_hal_params *hal_params;
201 bool supports_dynamic_smps_6ghz;
202 bool alloc_cacheable_memory;
203 bool supports_rssi_stats;
204 bool fw_wmi_diag_event;
205 bool current_cc_support;
206 bool dbr_debug_support;
207 bool global_reset;
208 const struct cfg80211_sar_capa *bios_sar_capa;
209 bool m3_fw_support;
210 bool fixed_bdf_addr;
211 bool fixed_mem_region;
212 bool static_window_map;
213 bool hybrid_bus_type;
214 bool fixed_fw_mem;
215 bool support_off_channel_tx;
216 bool supports_multi_bssid;
217
218 struct {
219 u32 start;
220 u32 end;
221 } sram_dump;
222
223 bool tcl_ring_retry;
224 u32 tx_ring_size;
225 bool smp2p_wow_exit;
226 bool support_fw_mac_sequence;
227 bool ftm_responder;
228 };
229
230 struct ath11k_hw_ops {
231 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
232 void (*wmi_init_config)(struct ath11k_base *ab,
233 struct target_resource_config *config);
234 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);
235 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
236 void (*tx_mesh_enable)(struct ath11k_base *ab,
237 struct hal_tcl_data_cmd *tcl_cmd);
238 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
239 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
240 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
241 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
242 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
243 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
244 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
245 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
246 bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc);
247 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
248 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
249 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
250 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
251 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
252 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
253 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
254 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
255 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
256 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
257 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
258 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
259 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,
260 struct hal_rx_desc *ldesc);
261 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
262 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
263 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
264 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
265 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
266 void (*reo_setup)(struct ath11k_base *ab);
267 u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
268 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
269 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
270 u32 (*get_ring_selector)(struct sk_buff *skb);
271 };
272
273 extern const struct ath11k_hw_ops ipq8074_ops;
274 extern const struct ath11k_hw_ops ipq6018_ops;
275 extern const struct ath11k_hw_ops qca6390_ops;
276 extern const struct ath11k_hw_ops qcn9074_ops;
277 extern const struct ath11k_hw_ops wcn6855_ops;
278 extern const struct ath11k_hw_ops wcn6750_ops;
279 extern const struct ath11k_hw_ops ipq5018_ops;
280
281 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
282 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
283 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;
284 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750;
285
286 extern const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074;
287 extern const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018;
288
289 extern const struct ce_remap ath11k_ce_remap_ipq5018;
290
291 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074;
292 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390;
293 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750;
294
295 static inline
ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params * hw,int pdev_idx)296 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
297 int pdev_idx)
298 {
299 if (hw->hw_ops->get_hw_mac_from_pdev_id)
300 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
301
302 return 0;
303 }
304
ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params * hw,int mac_id)305 static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw,
306 int mac_id)
307 {
308 if (hw->hw_ops->mac_id_to_pdev_id)
309 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
310
311 return 0;
312 }
313
ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params * hw,int mac_id)314 static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw,
315 int mac_id)
316 {
317 if (hw->hw_ops->mac_id_to_srng_id)
318 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
319
320 return 0;
321 }
322
323 struct ath11k_fw_ie {
324 __le32 id;
325 __le32 len;
326 u8 data[];
327 };
328
329 enum ath11k_bd_ie_board_type {
330 ATH11K_BD_IE_BOARD_NAME = 0,
331 ATH11K_BD_IE_BOARD_DATA = 1,
332 };
333
334 enum ath11k_bd_ie_regdb_type {
335 ATH11K_BD_IE_REGDB_NAME = 0,
336 ATH11K_BD_IE_REGDB_DATA = 1,
337 };
338
339 enum ath11k_bd_ie_type {
340 /* contains sub IEs of enum ath11k_bd_ie_board_type */
341 ATH11K_BD_IE_BOARD = 0,
342 /* contains sub IEs of enum ath11k_bd_ie_regdb_type */
343 ATH11K_BD_IE_REGDB = 1,
344 };
345
346 struct ath11k_hw_regs {
347 u32 hal_tcl1_ring_base_lsb;
348 u32 hal_tcl1_ring_base_msb;
349 u32 hal_tcl1_ring_id;
350 u32 hal_tcl1_ring_misc;
351 u32 hal_tcl1_ring_tp_addr_lsb;
352 u32 hal_tcl1_ring_tp_addr_msb;
353 u32 hal_tcl1_ring_consumer_int_setup_ix0;
354 u32 hal_tcl1_ring_consumer_int_setup_ix1;
355 u32 hal_tcl1_ring_msi1_base_lsb;
356 u32 hal_tcl1_ring_msi1_base_msb;
357 u32 hal_tcl1_ring_msi1_data;
358 u32 hal_tcl2_ring_base_lsb;
359 u32 hal_tcl_ring_base_lsb;
360
361 u32 hal_tcl_status_ring_base_lsb;
362
363 u32 hal_reo1_ring_base_lsb;
364 u32 hal_reo1_ring_base_msb;
365 u32 hal_reo1_ring_id;
366 u32 hal_reo1_ring_misc;
367 u32 hal_reo1_ring_hp_addr_lsb;
368 u32 hal_reo1_ring_hp_addr_msb;
369 u32 hal_reo1_ring_producer_int_setup;
370 u32 hal_reo1_ring_msi1_base_lsb;
371 u32 hal_reo1_ring_msi1_base_msb;
372 u32 hal_reo1_ring_msi1_data;
373 u32 hal_reo2_ring_base_lsb;
374 u32 hal_reo1_aging_thresh_ix_0;
375 u32 hal_reo1_aging_thresh_ix_1;
376 u32 hal_reo1_aging_thresh_ix_2;
377 u32 hal_reo1_aging_thresh_ix_3;
378
379 u32 hal_reo1_ring_hp;
380 u32 hal_reo1_ring_tp;
381 u32 hal_reo2_ring_hp;
382
383 u32 hal_reo_tcl_ring_base_lsb;
384 u32 hal_reo_tcl_ring_hp;
385
386 u32 hal_reo_status_ring_base_lsb;
387 u32 hal_reo_status_hp;
388
389 u32 hal_reo_cmd_ring_base_lsb;
390 u32 hal_reo_cmd_ring_hp;
391
392 u32 hal_sw2reo_ring_base_lsb;
393 u32 hal_sw2reo_ring_hp;
394
395 u32 hal_seq_wcss_umac_ce0_src_reg;
396 u32 hal_seq_wcss_umac_ce0_dst_reg;
397 u32 hal_seq_wcss_umac_ce1_src_reg;
398 u32 hal_seq_wcss_umac_ce1_dst_reg;
399
400 u32 hal_wbm_idle_link_ring_base_lsb;
401 u32 hal_wbm_idle_link_ring_misc;
402
403 u32 hal_wbm_release_ring_base_lsb;
404
405 u32 hal_wbm0_release_ring_base_lsb;
406 u32 hal_wbm1_release_ring_base_lsb;
407
408 u32 pcie_qserdes_sysclk_en_sel;
409 u32 pcie_pcs_osc_dtct_config_base;
410
411 u32 hal_shadow_base_addr;
412 u32 hal_reo1_misc_ctl;
413 };
414
415 extern const struct ath11k_hw_regs ipq8074_regs;
416 extern const struct ath11k_hw_regs qca6390_regs;
417 extern const struct ath11k_hw_regs qcn9074_regs;
418 extern const struct ath11k_hw_regs wcn6855_regs;
419 extern const struct ath11k_hw_regs wcn6750_regs;
420 extern const struct ath11k_hw_regs ipq5018_regs;
421
ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)422 static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
423 {
424 switch (type) {
425 case ATH11K_BD_IE_BOARD:
426 return "board data";
427 case ATH11K_BD_IE_REGDB:
428 return "regdb data";
429 }
430
431 return "unknown";
432 }
433
434 extern const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855;
435
436 #endif
437