1 /*
2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdbool.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <lib/cassert.h>
12 #include <lib/el3_runtime/pubsub.h>
13 #include <lib/extensions/sve.h>
14
15 CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long);
16 CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short);
17 CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule);
18
19 /*
20 * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
21 * VECTOR_SIZE = (LEN+1) * 128
22 */
23 #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
24
sve_supported(void)25 static bool sve_supported(void)
26 {
27 uint64_t features;
28
29 features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
30 return (features & ID_AA64PFR0_SVE_MASK) == 1U;
31 }
32
sve_enable(cpu_context_t * context)33 void sve_enable(cpu_context_t *context)
34 {
35 u_register_t cptr_el3;
36
37 if (!sve_supported()) {
38 return;
39 }
40
41 cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
42
43 /* Enable access to SVE functionality for all ELs. */
44 cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
45 write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
46
47 /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */
48 write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
49 (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN)));
50 }
51
sve_disable(cpu_context_t * context)52 void sve_disable(cpu_context_t *context)
53 {
54 u_register_t reg;
55 el3_state_t *state;
56
57 /* Make sure SME is implemented in hardware before continuing. */
58 if (!sve_supported()) {
59 return;
60 }
61
62 /* Get the context state. */
63 state = get_el3state_ctx(context);
64
65 /* Disable SVE and FPU since they share registers. */
66 reg = read_ctx_reg(state, CTX_CPTR_EL3);
67 reg &= ~CPTR_EZ_BIT; /* Trap SVE */
68 reg |= TFP_BIT; /* Trap FPU/SIMD */
69 write_ctx_reg(state, CTX_CPTR_EL3, reg);
70 }
71