1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * N1SDP Timer Synchronization Device Driver. 9 */ 10 11 /** The use of "primary" may not be in sync with platform documentation **/ 12 13 #ifndef MOD_N1SDP_TIMER_SYNC_H 14 #define MOD_N1SDP_TIMER_SYNC_H 15 16 #include <fwk_id.h> 17 #include <fwk_macros.h> 18 19 #include <stdint.h> 20 21 /*! 22 * \addtogroup GroupN1SDPModule N1SDP Product Modules 23 * \{ 24 */ 25 26 /*! 27 * \defgroup GroupN1SDPTimerSync N1SDP Timer Synchronization Driver 28 * \{ 29 */ 30 31 /*! 32 * \brief Module API indices 33 */ 34 enum mod_n1sdp_timer_sync_api_idx { 35 /*! Timer synchronization API */ 36 N1SDP_TIMER_SYNC_API_IDX_TSYNC, 37 38 /*! Number of APIs */ 39 N1SDP_TIMER_SYNC_API_COUNT, 40 }; 41 42 /*! 43 * \brief N1SDP Timer Synchronization API 44 */ 45 struct n1sdp_timer_sync_api { 46 /*! 47 * \brief API to trigger synchronization in primary. 48 * 49 * \param id Identifier of the timer sync module. 50 * 51 * \retval ::FWK_SUCCESS If operation succeeds. 52 * \return One of the possible error return codes. 53 */ 54 int (*primary_sync)(fwk_id_t id); 55 /*! 56 * \brief API to trigger synchronization in secondary. 57 * 58 * \param id Identifier of the timer sync module. 59 * 60 * \retval ::FWK_SUCCESS If operation succeeds. 61 * \return One of the possible error return codes. 62 */ 63 int (*secondary_sync)(fwk_id_t id); 64 }; 65 66 /*! 67 * \brief Timer Synchronization Device Configuration 68 */ 69 struct mod_n1sdp_tsync_config { 70 /*! IRQ number of the timer synchronization module */ 71 unsigned int irq; 72 73 /*! Base address of the timer synchronization module */ 74 uintptr_t reg; 75 76 /*! CCIX network delay */ 77 uint32_t ccix_delay; 78 79 /*! GCNT sync timeout */ 80 uint32_t sync_timeout; 81 82 /*! GCNT sync interval */ 83 uint32_t sync_interval; 84 85 /*! GCNT offset threshold */ 86 uint32_t off_threshold; 87 88 /*! Target counter base address */ 89 uint32_t target_cnt_base; 90 91 /*! Offset to access target counter locally */ 92 uint32_t local_offset; 93 94 /*! Offset to access target counter remotely */ 95 uint64_t remote_offset; 96 }; 97 98 /*! 99 * \} 100 */ 101 102 /*! 103 * \} 104 */ 105 106 #endif /* MOD_N1SDP_TIMER_SYNC_H */ 107