1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include <sysdef_option.h>
9 
10 #include <internal/nic400.h>
11 
12 #include <fwk_macros.h>
13 
14 #include <stdbool.h>
15 #include <stddef.h>
16 #include <stdint.h>
17 
18 #define SYNQUACER_CHIP_VER_MP UINT32_C(1)
19 
20 static const uint32_t nic_config_mp[NIC_CONFIG_NUM] = {
21     1, NIC_SETUP_SKIP, NIC_SETUP_SKIP, 1, 0x7, END_OF_NIC_LIST
22 };
23 
24 static struct sysdef_option {
25     uint32_t clear_clkforce; /* Value to be set to CLKFORCE_SET register */
26     const uint32_t *scbm_mv_nic_config;
27     char *chip_version;
28     const struct sysdef_option_gpio_desc *gpio_desc_p;
29     uint32_t gpio_desc_num;
30     bool ap_reboot_enable;
31     uint32_t i2c_for_spd_read_addr;
32     uint32_t sensor_num;
33 } sysdef_option;
34 
35 static const struct sysdef_option_gpio_desc gpio_desc_synquacer_mp[] = {
36     { 14 /* pin_no */, true /* inv */, "pcie1-ep-detected" /* str */ }
37 };
38 
sysdef_option_get_clear_clkforce(void)39 uint32_t sysdef_option_get_clear_clkforce(void)
40 {
41     return sysdef_option.clear_clkforce;
42 }
43 
sysdef_option_get_ap_reboot_enable(void)44 bool sysdef_option_get_ap_reboot_enable(void)
45 {
46     return sysdef_option.ap_reboot_enable;
47 }
48 
sysdef_option_get_scbm_mv_nic_config(void)49 const uint32_t *sysdef_option_get_scbm_mv_nic_config(void)
50 {
51     return sysdef_option.scbm_mv_nic_config;
52 }
53 
sysdef_option_get_chip_version(void)54 char *sysdef_option_get_chip_version(void)
55 {
56     return sysdef_option.chip_version;
57 }
58 
sysdef_option_get_gpio_desc(const struct sysdef_option_gpio_desc ** gpio_desc_pp)59 uint32_t sysdef_option_get_gpio_desc(
60     const struct sysdef_option_gpio_desc **gpio_desc_pp)
61 {
62     if (gpio_desc_pp == NULL)
63         return 0;
64 
65     *gpio_desc_pp = sysdef_option.gpio_desc_p;
66     return sysdef_option.gpio_desc_num;
67 }
68 
sysdef_option_get_i2c_for_spd_read_addr(void)69 uint32_t sysdef_option_get_i2c_for_spd_read_addr(void)
70 {
71     return sysdef_option.i2c_for_spd_read_addr;
72 }
73 
74 #define CMN_ST2_OFFSET UINT32_C(0x7b4)
75 
fw_get_chip_ver(void)76 uint32_t fw_get_chip_ver(void)
77 {
78     return SYNQUACER_CHIP_VER_MP;
79 }
80 
sysdef_option_get_sensor_num(void)81 uint32_t sysdef_option_get_sensor_num(void)
82 {
83     return sysdef_option.sensor_num;
84 }
85 
sysdef_option_init_synquacer(void)86 void sysdef_option_init_synquacer(void)
87 {
88     sysdef_option.clear_clkforce = 0x144U;
89     sysdef_option.scbm_mv_nic_config = nic_config_mp;
90     sysdef_option.chip_version = "2";
91     sysdef_option.gpio_desc_p = gpio_desc_synquacer_mp;
92     sysdef_option.gpio_desc_num = FWK_ARRAY_SIZE(gpio_desc_synquacer_mp);
93     sysdef_option.ap_reboot_enable = false;
94     sysdef_option.i2c_for_spd_read_addr = I2C_MP_START_ADDR;
95     sysdef_option.sensor_num = 7;
96 }
97