1 #pragma once 2 #include <platform/zynq.h> 3 4 struct pktbuf; 5 6 typedef void (*gem_cb_t)(struct pktbuf *p); 7 status_t gem_init(uintptr_t regsbase); 8 void gem_set_callback(gem_cb_t rx); 9 void gem_set_macaddr(uint8_t mac[6]); 10 int gem_send_raw_pkt(struct pktbuf *p); 11 12 void gem_disable(void); 13 14 struct gem_regs { 15 uint32_t net_ctrl; 16 uint32_t net_cfg; 17 uint32_t net_status; 18 uint32_t ___reserved1; 19 uint32_t dma_cfg; 20 uint32_t tx_status; 21 uint32_t rx_qbar; 22 uint32_t tx_qbar; 23 uint32_t rx_status; 24 uint32_t intr_status; 25 uint32_t intr_en; 26 uint32_t intr_dis; 27 uint32_t intr_mask; 28 uint32_t phy_maint; 29 uint32_t rx_pauseq; 30 uint32_t tx_pauseq; 31 uint32_t ___reserved2[16]; 32 uint32_t hash_bot; 33 uint32_t hash_top; 34 uint32_t spec_addr1_bot; 35 uint32_t spec_addr1_top; 36 uint32_t spec_addr2_bot; 37 uint32_t spec_addr2_top; 38 uint32_t spec_addr3_bot; 39 uint32_t spec_addr3_top; 40 uint32_t spec_addr4_bot; 41 uint32_t spec_addr4_top; 42 uint32_t type_id_match1; 43 uint32_t type_id_match2; 44 uint32_t type_id_match3; 45 uint32_t type_id_match4; 46 uint32_t wake_on_lan; 47 uint32_t ipg_stretch; 48 uint32_t stacked_vlan; 49 uint32_t tx_pfc_pause; 50 uint32_t spec_addr1_mask_bot; 51 uint32_t spec_addr1_mask_top; 52 uint32_t ___reserved3[11]; 53 uint32_t module_id; 54 uint32_t octets_tx_bot; 55 uint32_t octets_tx_top; 56 uint32_t frames_tx; 57 uint32_t broadcast_frames_tx; 58 uint32_t multi_frames_tx; 59 uint32_t pause_frames_tx; 60 uint32_t frames_64b_tx; 61 uint32_t frames_65to127b_tx; 62 uint32_t frames_128to255b_tx; 63 uint32_t frames_256to511b_tx; 64 uint32_t frames_512to1023b_tx; 65 uint32_t frames_1024to1518b_tx; 66 uint32_t ___reserved4; 67 uint32_t tx_under_runs; 68 uint32_t single_collisn_frames; 69 uint32_t multi_collisn_frames; 70 uint32_t excessive_collisns; 71 uint32_t late_collisns; 72 uint32_t deferred_tx_frames; 73 uint32_t carrier_sense_errs; 74 uint32_t octets_rx_bot; 75 uint32_t octets_rx_top; 76 uint32_t frames_rx; 77 uint32_t bdcast_fames_rx; 78 uint32_t multi_frames_rx; 79 uint32_t pause_rx; 80 uint32_t frames_64b_rx; 81 uint32_t frames_65to127b_rx; 82 uint32_t frames_128to255b_rx; 83 uint32_t frames_256to511b_rx; 84 uint32_t frames_512to1023b_rx; 85 uint32_t frames_1024to1518b_rx; 86 uint32_t ___reserved5; 87 uint32_t undersz_rx; 88 uint32_t oversz_rx; 89 uint32_t jab_rx; 90 uint32_t fcs_errors; 91 uint32_t length_field_errors; 92 uint32_t rx_symbol_errors; 93 uint32_t align_errors; 94 uint32_t rx_resource_errors; 95 uint32_t rx_overrun_errors; 96 uint32_t ip_hdr_csum_errors; 97 uint32_t tcp_csum_errors; 98 uint32_t udp_csum_errors; 99 uint32_t ___reserved6[7]; 100 uint32_t timer_strobe_s; 101 uint32_t timer_strobe_ns; 102 uint32_t timer_s; 103 uint32_t timer_ns; 104 uint32_t timer_adjust; 105 uint32_t timer_incr; 106 uint32_t ptp_tx_s; 107 uint32_t ptp_tx_ns; 108 uint32_t ptp_rx_s; 109 uint32_t ptp_rx_ns; 110 uint32_t ptp_peer_tx_s; 111 uint32_t ptp_peer_tx_ns; 112 uint32_t ptp_peer_rx_s; 113 uint32_t ptp_peer_rx_ns; 114 uint32_t ___reserved7[22]; 115 uint32_t design_cfg2; 116 uint32_t design_cfg3; 117 uint32_t design_cfg4; 118 uint32_t design_cfg5; 119 }; 120 121 /* net_ctrl */ 122 #define NET_CTRL_LOOP_EN (1 << 1) 123 #define NET_CTRL_RX_EN (1 << 2) 124 #define NET_CTRL_TX_EN (1 << 3) 125 #define NET_CTRL_MD_EN (1 << 4) 126 #define NET_CTRL_STATCLR (1 << 5) 127 #define NET_CTRL_STATINC (1 << 6) 128 #define NET_CTRL_STATW_EN (1 << 7) 129 #define NET_CTRL_BACK_PRESSURE (1 << 8) 130 #define NET_CTRL_START_TX (1 << 9) 131 #define NET_CTRL_HALT_TX (1 << 10) 132 #define NET_CTRL_PAUSE_TX (1 << 11) 133 #define NET_CTRL_ZERO_PAUSE_TX (1 << 12) 134 #define NET_CTRL_STR_RX_TIMESTAMP (1 << 15) 135 #define NET_CTRL_EN_PFC_PRI_PAUSE_RX (1 << 16) 136 #define NET_CTRL_TX_PFC_PRI_PAUSE_FRAME (1 << 17) 137 #define NET_CTRL_FLUSH_NEXT_RX_DPRAM_PKT (1 << 18) 138 /* net_cfg */ 139 #define NET_CFG_SPEED_100 (1) 140 #define NET_CFG_FULL_DUPLEX (1 << 1) 141 #define NET_CFG_DISC_NON_VLAN (1 << 2) 142 #define NET_CFG_COPY_ALL (1 << 4) 143 #define NET_CFG_NO_BCAST (1 << 5) 144 #define NET_CFG_MULTI_HASH_EN (1 << 6) 145 #define NET_CFG_UNI_HASH_EN (1 << 7) 146 #define NET_CFG_RX_1536_BYTE (1 << 8) 147 #define NET_CFG_EXT_ADDR_MATCH_EN (1 << 9) 148 #define NET_CFG_GIGE_EN (1 << 10) 149 #define NET_CFG_PCS_SEL (1 << 11) 150 #define NET_CFG_RETRY_TEST (1 << 12) 151 #define NET_CFG_PAUSE_EN (1 << 13) 152 #define NET_CFG_RX_BUF_OFFSET(x) (x << 14) 153 #define NET_CFG_LEN_ERR_FRAME_DISC (1 << 16) 154 #define NET_CFG_FCS_REMOVE (1 << 17) 155 #define NET_CFG_MDC_CLK_DIV(x) (x << 18) 156 #define NET_CFG_DBUS_WIDTH(x) (x << 21) 157 #define NET_CFG_DIS_CP_PAUSE_FRAME (1 << 23) 158 #define NET_CFG_RX_CHKSUM_OFFLD_EN (1 << 24) 159 #define NET_CFG_RX_HD_WHILE_TX (1 << 25) 160 #define NET_CFG_IGNORE_RX_FCS (1 << 26) 161 #define NET_CFG_SGMII_EN (1 << 27) 162 #define NET_CFG_IPG_STRETCH_EN (1 << 28) 163 #define NET_CFG_RX_BAD_PREAMBLE (1 << 29) 164 #define NET_CFG_IGNORE_IPG_RX_ER (1 << 30) 165 #define NET_CFG_UNIDIR_EN (1 << 31) 166 /* net_status */ 167 #define NET_STATUS_PFC_PRI_PAUSE_NEG (1 << 6) 168 #define NET_STATUS_PCS_AUTONEG_PAUSE_TX_RES (1 << 5) 169 #define NET_STATUS_PCS_AUTONEG_PAUSE_RX_RES (1 << 4) 170 #define NET_STATUS_PCS_AUTONEG_DUP_RES (1 << 3) 171 #define NET_STATUS_PHY_MGMT_IDLE (1 << 2) 172 #define NET_STATUS_MDIO_IN_PIN_STATUS (1 << 1) 173 #define NET_STATUS_PCS_LINK_STATE (1 << 0) 174 /* dma_cfg */ 175 #define DMA_CFG_AHB_FIXED_BURST_LEN(x) (x) 176 #define DMA_CFG_AHB_ENDIAN_SWP_MGM (1 << 6) 177 #define DMA_CFG_AHB_ENDIAN_SWP_PKT_EN (1 << 7) 178 #define DMA_CFG_RX_PKTBUF_MEMSZ_SEL(x) (x << 8) 179 #define DMA_CFG_TX_PKTBUF_MEMSZ_SEL (1 << 10) 180 #define DMA_CFG_CSUM_GEN_OFFLOAD_EN (1 << 11) 181 #define DMA_CFG_AHB_MEM_RX_BUF_SIZE(x) (x << 16) 182 #define DMA_CFG_DISC_WHEN_NO_AHB (1 << 24) 183 184 /* tx descriptor */ 185 #define TX_BUF_LEN(x) (x & 0x3FFF) 186 #define TX_LAST_BUF (1 << 15) 187 #define TX_CHKSUM_GEN_ERR(x) ((x >> 20) & 0x7) 188 #define TX_NO_CRC (1 << 16) 189 #define TX_LATE_COLLISION (1 << 26) 190 #define TX_RETRY_EXCEEDED (1 << 29) 191 #define TX_DESC_WRAP (1 << 30) 192 #define TX_DESC_USED (1 << 31) 193 194 /* rx descriptor */ 195 #define RX_DESC_USED (1 << 0) 196 #define RX_DESC_WRAP (1 << 1) 197 #define RX_BUF_LEN(x) (x & 0x1FFF) 198 #define RX_FCS_BAD_FCS (1 << 13) 199 #define RX_START_OF_FRAME (1 << 14) 200 #define RX_END_OF_FRAME (1 << 15) 201 #define RX_CFI (1 << 16) 202 #define RX_VLAN_PRIO(x) ((x >> 17) & 0x7) 203 #define RX_PRIO_TAG (1 << 20) 204 #define RX_VLAN_DETECT (1 << 21) 205 #define RX_CHKSUM_MATCH(x) ((1 >> 22) & 0x3) 206 #define RX_SNAP_ENCODED (1 << 24) 207 #define RX_ADDR_REG_MATCH(x) ((1 >> 25) & 0x3) 208 #define RX_SPECIFIC_ADDR_MATCH (1 << 27) 209 #define RX_EXT_MATCH (1 << 28) 210 #define RX_UNICAST_MATCH (1 << 30) 211 #define RX_MULTICAST_MATCH (1 << 31) 212 213 #define INTR_MGMT_SENT (1 << 0) 214 #define INTR_RX_COMPLETE (1 << 1) 215 #define INTR_RX_USED_READ (1 << 2) 216 #define INTR_TX_USED_READ (1 << 3) 217 #define INTR_RETRY_EX (1 << 5) 218 #define INTR_TX_CORRUPT (1 << 6) 219 #define INTR_TX_COMPLETE (1 << 7) 220 #define INTR_RX_OVERRUN (1 << 10) 221 #define INTR_HRESP_NOT_OK (1 << 11) 222 223 #define TX_STATUS_USED_READ (1) 224 #define TX_STATUS_COLLISION (1 << 1) 225 #define TX_STATUS_RETRY_LIMIT (1 << 2) 226 #define TX_STATUS_GO (1 << 3) 227 #define TX_STATUS_CORR_AHB (1 << 4) 228 #define TX_STATUS_COMPLETE (1 << 5) 229 #define TX_STATUS_UNDER_RUN (1 << 6) 230 #define TX_STATUS_LATE_COLLISION (1 << 7) 231 #define TX_STATUS_HRESP_NOT_OK (1 << 8) 232 233 #define RX_STATUS_BUFFER_NOT_AVAIL (1) 234 #define RX_STATUS_FRAME_RECD (1 << 1) 235 #define RX_STATUS_RX_OVERRUN (1 << 2) 236 #define RX_STATUS_HRESP_NOT_OK (1 << 3) 237