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Searched defs:val (Results 1 – 22 of 22) sorted by relevance

/SCP-firmware-master/product/synquacer/module/hsspi/src/
A Dhsspi_reg.h48 #define MCTRL_MES(val) (((val)&0x1) << 4) argument
50 #define MCTRL_CDSS(val) (((val)&0x1) << 3) argument
52 #define MCTRL_CSEN(val) (((val)&0x1) << 1) argument
54 #define MCTRL_MEN(val) ((val)&0x1) argument
78 #define CSCFG_BOOTEN(val) (((val)&0x1) << 4) argument
81 #define CSCFG_SPICHG(val) (((val)&0x1) << 3) argument
84 #define CSCFG_MBM(val) (((val)&0x3) << 1) argument
90 #define CSCFG_SRAM(val) ((val)&0x1) argument
100 #define DATA(val) (((val)&0xFF) << 8) argument
101 #define TRP(val) (((val)&0x3) << 1) argument
[all …]
A Dmod_hsspi.c39 #define REG_MASK_WRITE(addr, mask, val) \ argument
84 uint32_t mask, val; in set_pcc() local
114 uint32_t mask, val; in set_cscfg() local
148 uint32_t mask, val; in enable_cs_access_mode() local
247 uint16_t *val) in set_command_sequence()
/SCP-firmware-master/product/synquacer/include/nor/
A Ddevice_nor_s25.h86 #define S25_QUAD_DISABLE(val) ((val) &= ~S25_QUAD_BIT) argument
87 #define S25_QUAD_ENABLE(val) ((val) |= S25_QUAD_BIT) argument
88 #define S25_IS_QUAD_ENABLE(val) (((val)&S25_QUAD_BIT) != 0) argument
92 #define S25_4BYTE_DISABLE(val) ((val) &= ~S25_EXTADD_BIT) argument
93 #define S25_4BYTE_ENABLE(val) ((val) |= S25_EXTADD_BIT) argument
94 #define S25_IS_4BYTE_ENABLE(val) (((val)&S25_EXTADD_BIT) != 0) argument
A Ddevice_nor_w25.h85 #define W25_QUAD_DISABLE(val) ((val) &= ~W25_QE_BIT) argument
86 #define W25_QUAD_ENABLE(val) ((val) |= W25_QE_BIT) argument
87 #define W25_IS_QUAD_ENABLE(val) (((val)&W25_QE_BIT) != 0) argument
A Ddevice_nor_mt25.h74 #define MT25_QUAD_DISABLE(val) ((val) |= MT25_RESETHOLD_BIT) argument
75 #define MT25_QUAD_ENABLE(val) ((val) &= ~MT25_RESETHOLD_BIT) // 0 is enable argument
76 #define MT25_IS_QUAD_ENABLE(val) (((val)&MT25_RESETHOLD_BIT) == 0) argument
A Ddevice_nor_mx25.h70 #define MX25_QUAD_DISABLE(val) ((val) &= ~MX25_QE_BIT) argument
71 #define MX25_QUAD_ENABLE(val) ((val) |= MX25_QE_BIT) argument
72 #define MX25_IS_QUAD_ENABLE(val) (((val)&MX25_QE_BIT) != 0) argument
/SCP-firmware-master/product/rcar/module/rcar_system/src/
A DFreeRTOS_tick_config.c78 void write_cntv_tval(uint32_t val) in write_cntv_tval()
87 uint32_t val; in read_cntfrq() local
95 uint32_t val; in read_cntv_tval() local
A Drcar_common.c40 uint64_t val; in get_cntfrq() local
47 uint64_t val; in get_cntvct() local
/SCP-firmware-master/debugger/src/cli/
A Dcli_fifo.c29 uint32_t fifo_get(fifo_st *fifo, char *val) in fifo_get()
51 uint32_t fifo_put(fifo_st *fifo, char *val) in fifo_put()
/SCP-firmware-master/product/rcar/module/rcar_mock_pmic_bd9571/src/
A Dmod_rcar_mock_pmic_bd9571_driver_api.c50 uint8_t val; in api_set_voltage() local
89 uint8_t val; in api_set_pmic() local
/SCP-firmware-master/product/rcar/module/rcar_clock/src/
A Dmod_rcar_clock.c548 unsigned int val; in pll0_clk_recalc_rate() local
565 uint32_t val; in pll0_clk_set_rate() local
605 unsigned int val; in pll2_clk_recalc_rate() local
622 uint32_t val; in pll2_clk_set_rate() local
672 unsigned int val; in z_clk_recalc_rate() local
689 uint32_t val, kick; in z_clk_set_rate() local
769 unsigned int val; in z2_clk_recalc_rate() local
785 uint32_t val, kick; in z2_clk_set_rate() local
/SCP-firmware-master/product/synquacer/include/
A Dbootctl_reg.h24 #define ADRDEC_HSSPIx(val, bs) (((val)&0x1) << (bs)) argument
26 #define CMDSEL_HSSPIx(val, bs) (((val)&0x1) << (bs)) argument
/SCP-firmware-master/arch/arm/armv8-a/src/
A Darch_gic.c203 unsigned int val) in gicd_write_isenabler()
217 unsigned int val) in gicd_write_icenabler()
231 unsigned int val) in gicd_write_ispendr()
245 unsigned int val) in gicd_write_icpendr()
277 uint8_t val = (uint8_t)(pri & GIC_PRI_MASK); in gicd_set_ipriorityr() local
297 static void gicc_write_ctlr(uintptr_t base, unsigned int val) in gicc_write_ctlr()
302 static void gicc_write_pmr(uintptr_t base, unsigned int val) in gicc_write_pmr()
313 unsigned int val; in gic_cpuif_enable() local
333 unsigned int val; in gic_cpuif_disable() local
/SCP-firmware-master/arch/arm/armv8-a/include/
A Darch_helpers.h209 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) argument
210 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) argument
/SCP-firmware-master/module/cdns_i2c/src/
A Dmod_cdns_i2c.c37 #define I2C_REG_RMW(reg, mask, shift, val) \ argument
41 #define I2C_REG_W(reg, mask, shift, val) ((reg) = ((val) << (shift)) & (mask)) argument
/SCP-firmware-master/module/dwt_pmi/src/
A Dmod_dwt_pmi.c64 uint32_t val = *(ctx.config->dwt_ctrl_addr); in check_cyccnt_supported() local
/SCP-firmware-master/product/rcar/module/rcar_reg_sensor/src/
A Dmod_rcar_reg_sensor.c88 int mcelsius, val; in rcar_gen3_thermal_get_temp() local
/SCP-firmware-master/product/rcar/src/CMSIS-FreeRTOS/CMSIS/RTOS2/FreeRTOS/Source/
A Dcmsis_os2_tiny4scp.c55 uint32_t val; in is_irq() local
/SCP-firmware-master/arch/arm/armv8-a/include/lib/
A Dutils_def.h57 #define div_round_up(val, div) \ argument
/SCP-firmware-master/product/synquacer/module/nor/src/
A Dmod_nor.c25 #define IS_WEL_ENABLE(val) (((val)&WEL_ENABLE) != 0) argument
29 #define IS_WIP_BUSY(val) (((val)&WIP_BUSY) != 0) argument
/SCP-firmware-master/product/rcar/module/rcar_clock/include/
A Dmod_rcar_clock.h359 #define clamp(val, lo, hi) min((__typeof__(val))max(val, lo), hi) argument
/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/
A Dmod_juno_soc_clock_ram.c77 uint32_t val; member

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