1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HyperV Detection code.
4 *
5 * Copyright (C) 2010, Novell, Inc.
6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com>
7 */
8
9 #include <linux/types.h>
10 #include <linux/time.h>
11 #include <linux/clocksource.h>
12 #include <linux/init.h>
13 #include <linux/export.h>
14 #include <linux/hardirq.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kexec.h>
19 #include <linux/i8253.h>
20 #include <linux/random.h>
21 #include <linux/swiotlb.h>
22 #include <asm/processor.h>
23 #include <asm/hypervisor.h>
24 #include <asm/hyperv-tlfs.h>
25 #include <asm/mshyperv.h>
26 #include <asm/desc.h>
27 #include <asm/idtentry.h>
28 #include <asm/irq_regs.h>
29 #include <asm/i8259.h>
30 #include <asm/apic.h>
31 #include <asm/timer.h>
32 #include <asm/reboot.h>
33 #include <asm/nmi.h>
34 #include <clocksource/hyperv_timer.h>
35 #include <asm/numa.h>
36 #include <asm/coco.h>
37
38 /* Is Linux running as the root partition? */
39 bool hv_root_partition;
40 /* Is Linux running on nested Microsoft Hypervisor */
41 bool hv_nested;
42 struct ms_hyperv_info ms_hyperv;
43
44 #if IS_ENABLED(CONFIG_HYPERV)
hv_get_nested_reg(unsigned int reg)45 static inline unsigned int hv_get_nested_reg(unsigned int reg)
46 {
47 if (hv_is_sint_reg(reg))
48 return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0;
49
50 switch (reg) {
51 case HV_REGISTER_SIMP:
52 return HV_REGISTER_NESTED_SIMP;
53 case HV_REGISTER_SIEFP:
54 return HV_REGISTER_NESTED_SIEFP;
55 case HV_REGISTER_SVERSION:
56 return HV_REGISTER_NESTED_SVERSION;
57 case HV_REGISTER_SCONTROL:
58 return HV_REGISTER_NESTED_SCONTROL;
59 case HV_REGISTER_EOM:
60 return HV_REGISTER_NESTED_EOM;
61 default:
62 return reg;
63 }
64 }
65
hv_get_non_nested_register(unsigned int reg)66 u64 hv_get_non_nested_register(unsigned int reg)
67 {
68 u64 value;
69
70 if (hv_is_synic_reg(reg) && hv_isolation_type_snp())
71 hv_ghcb_msr_read(reg, &value);
72 else
73 rdmsrl(reg, value);
74 return value;
75 }
76 EXPORT_SYMBOL_GPL(hv_get_non_nested_register);
77
hv_set_non_nested_register(unsigned int reg,u64 value)78 void hv_set_non_nested_register(unsigned int reg, u64 value)
79 {
80 if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) {
81 hv_ghcb_msr_write(reg, value);
82
83 /* Write proxy bit via wrmsl instruction */
84 if (hv_is_sint_reg(reg))
85 wrmsrl(reg, value | 1 << 20);
86 } else {
87 wrmsrl(reg, value);
88 }
89 }
90 EXPORT_SYMBOL_GPL(hv_set_non_nested_register);
91
hv_get_register(unsigned int reg)92 u64 hv_get_register(unsigned int reg)
93 {
94 if (hv_nested)
95 reg = hv_get_nested_reg(reg);
96
97 return hv_get_non_nested_register(reg);
98 }
99 EXPORT_SYMBOL_GPL(hv_get_register);
100
hv_set_register(unsigned int reg,u64 value)101 void hv_set_register(unsigned int reg, u64 value)
102 {
103 if (hv_nested)
104 reg = hv_get_nested_reg(reg);
105
106 hv_set_non_nested_register(reg, value);
107 }
108 EXPORT_SYMBOL_GPL(hv_set_register);
109
110 static void (*vmbus_handler)(void);
111 static void (*hv_stimer0_handler)(void);
112 static void (*hv_kexec_handler)(void);
113 static void (*hv_crash_handler)(struct pt_regs *regs);
114
DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)115 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)
116 {
117 struct pt_regs *old_regs = set_irq_regs(regs);
118
119 inc_irq_stat(irq_hv_callback_count);
120 if (vmbus_handler)
121 vmbus_handler();
122
123 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED)
124 ack_APIC_irq();
125
126 set_irq_regs(old_regs);
127 }
128
hv_setup_vmbus_handler(void (* handler)(void))129 void hv_setup_vmbus_handler(void (*handler)(void))
130 {
131 vmbus_handler = handler;
132 }
133
hv_remove_vmbus_handler(void)134 void hv_remove_vmbus_handler(void)
135 {
136 /* We have no way to deallocate the interrupt gate */
137 vmbus_handler = NULL;
138 }
139
140 /*
141 * Routines to do per-architecture handling of stimer0
142 * interrupts when in Direct Mode
143 */
DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)144 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)
145 {
146 struct pt_regs *old_regs = set_irq_regs(regs);
147
148 inc_irq_stat(hyperv_stimer0_count);
149 if (hv_stimer0_handler)
150 hv_stimer0_handler();
151 add_interrupt_randomness(HYPERV_STIMER0_VECTOR);
152 ack_APIC_irq();
153
154 set_irq_regs(old_regs);
155 }
156
157 /* For x86/x64, override weak placeholders in hyperv_timer.c */
hv_setup_stimer0_handler(void (* handler)(void))158 void hv_setup_stimer0_handler(void (*handler)(void))
159 {
160 hv_stimer0_handler = handler;
161 }
162
hv_remove_stimer0_handler(void)163 void hv_remove_stimer0_handler(void)
164 {
165 /* We have no way to deallocate the interrupt gate */
166 hv_stimer0_handler = NULL;
167 }
168
hv_setup_kexec_handler(void (* handler)(void))169 void hv_setup_kexec_handler(void (*handler)(void))
170 {
171 hv_kexec_handler = handler;
172 }
173
hv_remove_kexec_handler(void)174 void hv_remove_kexec_handler(void)
175 {
176 hv_kexec_handler = NULL;
177 }
178
hv_setup_crash_handler(void (* handler)(struct pt_regs * regs))179 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs))
180 {
181 hv_crash_handler = handler;
182 }
183
hv_remove_crash_handler(void)184 void hv_remove_crash_handler(void)
185 {
186 hv_crash_handler = NULL;
187 }
188
189 #ifdef CONFIG_KEXEC_CORE
hv_machine_shutdown(void)190 static void hv_machine_shutdown(void)
191 {
192 if (kexec_in_progress && hv_kexec_handler)
193 hv_kexec_handler();
194
195 /*
196 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
197 * corrupts the old VP Assist Pages and can crash the kexec kernel.
198 */
199 if (kexec_in_progress && hyperv_init_cpuhp > 0)
200 cpuhp_remove_state(hyperv_init_cpuhp);
201
202 /* The function calls stop_other_cpus(). */
203 native_machine_shutdown();
204
205 /* Disable the hypercall page when there is only 1 active CPU. */
206 if (kexec_in_progress)
207 hyperv_cleanup();
208 }
209
hv_machine_crash_shutdown(struct pt_regs * regs)210 static void hv_machine_crash_shutdown(struct pt_regs *regs)
211 {
212 if (hv_crash_handler)
213 hv_crash_handler(regs);
214
215 /* The function calls crash_smp_send_stop(). */
216 native_machine_crash_shutdown(regs);
217
218 /* Disable the hypercall page when there is only 1 active CPU. */
219 hyperv_cleanup();
220 }
221 #endif /* CONFIG_KEXEC_CORE */
222 #endif /* CONFIG_HYPERV */
223
ms_hyperv_platform(void)224 static uint32_t __init ms_hyperv_platform(void)
225 {
226 u32 eax;
227 u32 hyp_signature[3];
228
229 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
230 return 0;
231
232 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS,
233 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]);
234
235 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX ||
236 memcmp("Microsoft Hv", hyp_signature, 12))
237 return 0;
238
239 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */
240 eax = cpuid_eax(HYPERV_CPUID_FEATURES);
241 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) {
242 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n");
243 return 0;
244 }
245 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) {
246 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n");
247 return 0;
248 }
249
250 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
251 }
252
hv_get_nmi_reason(void)253 static unsigned char hv_get_nmi_reason(void)
254 {
255 return 0;
256 }
257
258 #ifdef CONFIG_X86_LOCAL_APIC
259 /*
260 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes
261 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle
262 * unknown NMI on the first CPU which gets it.
263 */
hv_nmi_unknown(unsigned int val,struct pt_regs * regs)264 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
265 {
266 static atomic_t nmi_cpu = ATOMIC_INIT(-1);
267
268 if (!unknown_nmi_panic)
269 return NMI_DONE;
270
271 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1)
272 return NMI_HANDLED;
273
274 return NMI_DONE;
275 }
276 #endif
277
hv_get_tsc_khz(void)278 static unsigned long hv_get_tsc_khz(void)
279 {
280 unsigned long freq;
281
282 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
283
284 return freq / 1000;
285 }
286
287 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV)
hv_smp_prepare_boot_cpu(void)288 static void __init hv_smp_prepare_boot_cpu(void)
289 {
290 native_smp_prepare_boot_cpu();
291 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS)
292 hv_init_spinlocks();
293 #endif
294 }
295
hv_smp_prepare_cpus(unsigned int max_cpus)296 static void __init hv_smp_prepare_cpus(unsigned int max_cpus)
297 {
298 #ifdef CONFIG_X86_64
299 int i;
300 int ret;
301 #endif
302
303 native_smp_prepare_cpus(max_cpus);
304
305 #ifdef CONFIG_X86_64
306 for_each_present_cpu(i) {
307 if (i == 0)
308 continue;
309 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i));
310 BUG_ON(ret);
311 }
312
313 for_each_present_cpu(i) {
314 if (i == 0)
315 continue;
316 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i);
317 BUG_ON(ret);
318 }
319 #endif
320 }
321 #endif
322
ms_hyperv_init_platform(void)323 static void __init ms_hyperv_init_platform(void)
324 {
325 int hv_max_functions_eax;
326 int hv_host_info_eax;
327 int hv_host_info_ebx;
328 int hv_host_info_ecx;
329 int hv_host_info_edx;
330
331 #ifdef CONFIG_PARAVIRT
332 pv_info.name = "Hyper-V";
333 #endif
334
335 /*
336 * Extract the features and hints
337 */
338 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES);
339 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES);
340 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES);
341 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO);
342
343 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS);
344
345 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n",
346 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints,
347 ms_hyperv.misc_features);
348
349 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS);
350 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS);
351
352 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n",
353 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index);
354
355 /*
356 * Check CPU management privilege.
357 *
358 * To mirror what Windows does we should extract CPU management
359 * features and use the ReservedIdentityBit to detect if Linux is the
360 * root partition. But that requires negotiating CPU management
361 * interface (a process to be finalized).
362 *
363 * For now, use the privilege flag as the indicator for running as
364 * root.
365 */
366 if (cpuid_ebx(HYPERV_CPUID_FEATURES) & HV_CPU_MANAGEMENT) {
367 hv_root_partition = true;
368 pr_info("Hyper-V: running as root partition\n");
369 }
370
371 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) {
372 hv_nested = true;
373 pr_info("Hyper-V: running on a nested hypervisor\n");
374 }
375
376 /*
377 * Extract host information.
378 */
379 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) {
380 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION);
381 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION);
382 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION);
383 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION);
384
385 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n",
386 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF,
387 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF,
388 hv_host_info_ecx, hv_host_info_edx >> 24);
389 }
390
391 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
392 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
393 x86_platform.calibrate_tsc = hv_get_tsc_khz;
394 x86_platform.calibrate_cpu = hv_get_tsc_khz;
395 }
396
397 if (ms_hyperv.priv_high & HV_ISOLATION) {
398 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG);
399 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG);
400 ms_hyperv.shared_gpa_boundary =
401 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits);
402
403 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n",
404 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b);
405
406 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) {
407 static_branch_enable(&isolation_type_snp);
408 #ifdef CONFIG_SWIOTLB
409 swiotlb_unencrypted_base = ms_hyperv.shared_gpa_boundary;
410 #endif
411 }
412 /* Isolation VMs are unenlightened SEV-based VMs, thus this check: */
413 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) {
414 if (hv_get_isolation_type() != HV_ISOLATION_TYPE_NONE)
415 cc_set_vendor(CC_VENDOR_HYPERV);
416 }
417 }
418
419 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) {
420 ms_hyperv.nested_features =
421 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES);
422 pr_info("Hyper-V: Nested features: 0x%x\n",
423 ms_hyperv.nested_features);
424 }
425
426 #ifdef CONFIG_X86_LOCAL_APIC
427 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
428 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
429 /*
430 * Get the APIC frequency.
431 */
432 u64 hv_lapic_frequency;
433
434 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
435 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
436 lapic_timer_period = hv_lapic_frequency;
437 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
438 lapic_timer_period);
439 }
440
441 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST,
442 "hv_nmi_unknown");
443 #endif
444
445 #ifdef CONFIG_X86_IO_APIC
446 no_timer_check = 1;
447 #endif
448
449 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE)
450 machine_ops.shutdown = hv_machine_shutdown;
451 machine_ops.crash_shutdown = hv_machine_crash_shutdown;
452 #endif
453 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
454 /*
455 * Writing to synthetic MSR 0x40000118 updates/changes the
456 * guest visible CPUIDs. Setting bit 0 of this MSR enables
457 * guests to report invariant TSC feature through CPUID
458 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
459 * early_init_intel() where this bit is examined. The
460 * setting of this MSR bit should happen before init_intel()
461 * is called.
462 */
463 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC);
464 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
465 }
466
467 /*
468 * Generation 2 instances don't support reading the NMI status from
469 * 0x61 port.
470 */
471 if (efi_enabled(EFI_BOOT))
472 x86_platform.get_nmi_reason = hv_get_nmi_reason;
473
474 /*
475 * Hyper-V VMs have a PIT emulation quirk such that zeroing the
476 * counter register during PIT shutdown restarts the PIT. So it
477 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter
478 * to false tells pit_shutdown() not to zero the counter so that
479 * the PIT really is shutdown. Generation 2 VMs don't have a PIT,
480 * and setting this value has no effect.
481 */
482 i8253_clear_counter_on_shutdown = false;
483
484 #if IS_ENABLED(CONFIG_HYPERV)
485 /*
486 * Setup the hook to get control post apic initialization.
487 */
488 x86_platform.apic_post_init = hyperv_init;
489 hyperv_setup_mmu_ops();
490 /* Setup the IDT for hypervisor callback */
491 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback);
492
493 /* Setup the IDT for reenlightenment notifications */
494 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) {
495 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR,
496 asm_sysvec_hyperv_reenlightenment);
497 }
498
499 /* Setup the IDT for stimer0 */
500 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) {
501 alloc_intr_gate(HYPERV_STIMER0_VECTOR,
502 asm_sysvec_hyperv_stimer0);
503 }
504
505 # ifdef CONFIG_SMP
506 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu;
507 if (hv_root_partition)
508 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus;
509 # endif
510
511 /*
512 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
513 * set x2apic destination mode to physical mode when x2apic is available
514 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs
515 * have 8-bit APIC id.
516 */
517 # ifdef CONFIG_X86_X2APIC
518 if (x2apic_supported())
519 x2apic_phys = 1;
520 # endif
521
522 /* Register Hyper-V specific clocksource */
523 hv_init_clocksource();
524 #endif
525 /*
526 * TSC should be marked as unstable only after Hyper-V
527 * clocksource has been initialized. This ensures that the
528 * stability of the sched_clock is not altered.
529 */
530 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
531 mark_tsc_unstable("running on Hyper-V");
532
533 hardlockup_detector_disable();
534 }
535
ms_hyperv_x2apic_available(void)536 static bool __init ms_hyperv_x2apic_available(void)
537 {
538 return x2apic_supported();
539 }
540
541 /*
542 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping()
543 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the
544 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg().
545 *
546 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which
547 * (logically) generates MSIs directly to the system APIC irq domain.
548 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the
549 * pci-hyperv host bridge.
550 *
551 * Note: for a Hyper-V root partition, this will always return false.
552 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by
553 * default, they are implemented as intercepts by the Windows Hyper-V stack.
554 * Even a nested root partition (L2 root) will not get them because the
555 * nested (L1) hypervisor filters them out.
556 */
ms_hyperv_msi_ext_dest_id(void)557 static bool __init ms_hyperv_msi_ext_dest_id(void)
558 {
559 u32 eax;
560
561 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE);
562 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE)
563 return false;
564
565 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES);
566 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE;
567 }
568
569 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
570 .name = "Microsoft Hyper-V",
571 .detect = ms_hyperv_platform,
572 .type = X86_HYPER_MS_HYPERV,
573 .init.x2apic_available = ms_hyperv_x2apic_available,
574 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id,
575 .init.init_platform = ms_hyperv_init_platform,
576 };
577