1/*
2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <arch.h>
10#include <asm_macros.S>
11#include <drivers/arm/gicv3.h>
12#include <platform_def.h>
13
14	.globl	plat_secondary_cold_boot_setup
15	.globl	plat_is_my_cpu_primary
16	.globl	platform_mem_init
17	.globl	plat_my_core_pos
18	.globl	plat_crash_console_init
19	.globl	plat_crash_console_putc
20	.globl	plat_crash_console_flush
21
22	/* -----------------------------------------------------
23	 * void plat_secondary_cold_boot_setup (void);
24	 *
25	 * This function performs any platform specific actions
26	 * needed for a secondary cpu after a cold reset e.g
27	 * mark the cpu's presence, mechanism to place it in a
28	 * holding pen etc.
29	 * TODO: Should we read the PSYS register to make sure
30	 * that the request has gone through.
31	 * -----------------------------------------------------
32	 */
33func plat_secondary_cold_boot_setup
34	mrs	x0, mpidr_el1
35
36	/*
37	 * There is no sane reason to come out of this wfi. This
38	 * cpu will be powered on and reset by the cpu_on pm api
39	 */
40	dsb	sy
41	bl	plat_panic_handler
42endfunc plat_secondary_cold_boot_setup
43
44func plat_is_my_cpu_primary
45	mov	x9, x30
46	bl	plat_my_core_pos
47	cmp	x0, #VERSAL_NET_PRIMARY_CPU
48	cset	x0, eq
49	ret	x9
50endfunc plat_is_my_cpu_primary
51
52	/* -----------------------------------------------------
53	 *  unsigned int plat_my_core_pos(void)
54	 *  This function uses the plat_core_pos_by_mpidr()
55	 *  definition to get the index of the calling CPU.
56	 * -----------------------------------------------------
57	 */
58func plat_my_core_pos
59	mrs	x0, mpidr_el1
60	b	plat_core_pos_by_mpidr
61endfunc plat_my_core_pos
62
63	/* ---------------------------------------------------------------------
64	 * We don't need to carry out any memory initialization on Versal NET
65	 * platform. The Secure RAM is accessible straight away.
66	 * ---------------------------------------------------------------------
67	 */
68func platform_mem_init
69	ret
70endfunc platform_mem_init
71
72
73	/* ---------------------------------------------
74	 * int plat_crash_console_init(void)
75	 * Function to initialize the crash console
76	 * without a C Runtime to print crash report.
77	 * Clobber list : x0, x1, x2
78	 * ---------------------------------------------
79	 */
80func plat_crash_console_init
81/*	mov_imm	x0, PLAT_VERSAL_NET_CRASH_UART_BASE
82	mov_imm	x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ
83	mov_imm	x2, VERSAL_NET_CONSOLE_BAUDRATE
84	b	console_pl011_core_init */
85endfunc plat_crash_console_init
86
87	/* ---------------------------------------------
88	 * int plat_crash_console_putc(int c)
89	 * Function to print a character on the crash
90	 * console without a C Runtime.
91	 * Clobber list : x1, x2
92	 * ---------------------------------------------
93	 */
94func plat_crash_console_putc
95	mov_imm	x1, PLAT_VERSAL_NET_CRASH_UART_BASE
96	b	console_pl011_core_putc
97endfunc plat_crash_console_putc
98
99	/* ---------------------------------------------
100	 * void plat_crash_console_flush()
101	 * Function to force a write of all buffered
102	 * data that hasn't been output.
103	 * Out : void.
104	 * Clobber list : x0, x1
105	 * ---------------------------------------------
106	 */
107func plat_crash_console_flush
108	mov_imm	x0, PLAT_VERSAL_NET_CRASH_UART_BASE
109	b	console_pl011_core_flush
110endfunc plat_crash_console_flush
111