1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "synquacer_config.h"
9 #include "synquacer_ddr.h"
10 
11 #include <boot_ctl.h>
12 #include <ddr_init.h>
13 
14 #include <internal/reg_DDRPHY_CONFIG.h>
15 #include <internal/reg_DMC520.h>
16 #include <mod_synquacer_memc.h>
17 
18 #include <stdint.h>
19 
20 extern void usleep_en(uint32_t usec);
21 
22 int ddr_init_mc0_mp(REG_ST_DMC520 *REG_DMC520);
23 int ddr_init_phy0_mp(REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
24                      int retention_en);
25 int ddr_init_phy1_mp(REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
26                      int retention_en);
27 int ddr_init_sdram_mp(
28     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
29     int retention_en);
30 int ddr_init_mc1_mp(REG_ST_DMC520 *REG_DMC520);
31 int ddr_init_train_mp(
32     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
33     int retention_en);
34 int ddr_init_mc2_mp(REG_ST_DMC520 *REG_DMC520);
35 
36 int g_DDR4_DMC520_INIT_CH = 0;
37 
38 #define DDR_DIP_SW3_SECURE_DRAM_ENABLE (0x04)
ddr_is_secure_dram_enabled(void)39 uint8_t ddr_is_secure_dram_enabled(void)
40 {
41     return get_dsw3_status(DDR_DIP_SW3_SECURE_DRAM_ENABLE);
42 }
43 
Wait_for_ddr(uint32_t count)44 void Wait_for_ddr(uint32_t count)
45 {
46     uint32_t i;
47     for (i = 0; i < count; i++)
48         __NOP();
49 }
50 
usleep_en(uint32_t usec)51 void usleep_en(uint32_t usec)
52 {
53     dmb();
54     synquacer_memc_timer_api->delay(
55         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0),
56         (usec + 2000));
57     return;
58 }
59 
60 enum ddr_wait_cond_type {
61     DDR_DMC520_MEMC_STATUS,
62     DDR_DDRPHY_CONFIG_PGSR0,
63     DDR_DDRPHY_CONFIG_PGSR0_1,
64 };
65 
66 struct ddr_wait_cond {
67     enum ddr_wait_cond_type type;
68     volatile void *reg;
69     uint32_t mask;
70     uint32_t comp_val;
71 };
72 
ddr_check_wait_cond(void * data)73 static bool ddr_check_wait_cond(void *data)
74 {
75     struct ddr_wait_cond *cond = (struct ddr_wait_cond *)data;
76 
77     /* continue to wait until this function returns true */
78     switch (cond->type) {
79     case DDR_DMC520_MEMC_STATUS:
80         return ((((REG_ST_DMC520 *)cond->reg)->memc_status & cond->mask) ==
81                 cond->comp_val);
82     case DDR_DDRPHY_CONFIG_PGSR0:
83         return ((((REG_ST_DDRPHY_CONFIG_t *)cond->reg)->PGSR0 & cond->mask) ==
84                 cond->comp_val);
85     case DDR_DDRPHY_CONFIG_PGSR0_1:
86         return ((((REG_ST_DDRPHY_CONFIG_t *)cond->reg)->PGSR0 & cond->mask) ==
87                 cond->comp_val ||
88                 (((REG_ST_DDRPHY_CONFIG_t *)cond->reg)->PGSR0 & 0x4FF80000) != 0);
89     default:
90         fwk_unexpected();
91         return false;
92     }
93 }
94 
ddr_dual_ch_init_mp(void)95 int ddr_dual_ch_init_mp(void)
96 {
97     int ret_val;
98     REG_ST_DMC520 *REG_DMC520_0;
99     REG_ST_DMC520 *REG_DMC520_1;
100     struct ddr_wait_cond wait_cond;
101 
102     ret_val = ddr_ch0_init_mp();
103     if (ret_val != 0)
104         return ret_val;
105 
106     ret_val = ddr_ch1_init_mp();
107     if (ret_val != 0)
108         return ret_val;
109 
110     REG_DMC520_0 = (REG_ST_DMC520 *)(uint32_t)REG_DMC520_0_BA;
111 
112     REG_DMC520_1 = (REG_ST_DMC520 *)(uint32_t)REG_DMC520_1_BA;
113     REG_DMC520_0->memc_cmd = 0x00000000;
114 
115     wait_cond.type = DDR_DMC520_MEMC_STATUS;
116     wait_cond.reg = REG_DMC520_0;
117     wait_cond.mask = 0x7;
118     wait_cond.comp_val = 0x0;
119     synquacer_memc_timer_api->wait(
120         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
121         ddr_check_wait_cond, &wait_cond);
122 
123     REG_DMC520_0->address_map_next = 0xFF000005;
124     REG_DMC520_0->memc_status;
125     REG_DMC520_0->memc_status;
126     REG_DMC520_0->memc_status;
127     REG_DMC520_0->memc_status;
128     REG_DMC520_0->memc_cmd = 0x00000003;
129     REG_DMC520_0->memc_status;
130     REG_DMC520_0->memc_cmd = 0x00000004;
131 
132     wait_cond.type = DDR_DMC520_MEMC_STATUS;
133     wait_cond.reg = REG_DMC520_0;
134     wait_cond.mask = 0x7;
135     wait_cond.comp_val = 0x3;
136     synquacer_memc_timer_api->wait(
137         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
138         ddr_check_wait_cond, &wait_cond);
139 
140     REG_DMC520_1->memc_cmd = 0x00000000;
141 
142     wait_cond.type = DDR_DMC520_MEMC_STATUS;
143     wait_cond.reg = REG_DMC520_1;
144     wait_cond.mask = 0x7;
145     wait_cond.comp_val = 0x0;
146     synquacer_memc_timer_api->wait(
147         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
148         ddr_check_wait_cond, &wait_cond);
149 
150     REG_DMC520_1->address_map_next = 0xFF000005;
151     REG_DMC520_1->memc_status;
152     REG_DMC520_1->memc_status;
153     REG_DMC520_1->memc_status;
154     REG_DMC520_1->memc_status;
155     REG_DMC520_1->memc_cmd = 0x00000003;
156     REG_DMC520_1->memc_status;
157     REG_DMC520_1->memc_cmd = 0x00000004;
158 
159     wait_cond.type = DDR_DMC520_MEMC_STATUS;
160     wait_cond.reg = REG_DMC520_1;
161     wait_cond.mask = 0x7;
162     wait_cond.comp_val = 0x3;
163     synquacer_memc_timer_api->wait(
164         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
165         ddr_check_wait_cond, &wait_cond);
166 
167 
168 
169     return 0;
170 }
171 
172 /* ch0 : DMC 0 + PHY 0 */
ddr_ch0_init_mp(void)173 int ddr_ch0_init_mp(void)
174 {
175     int status;
176     REG_ST_DMC520 *REG_DMC520_0;
177     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG_0;
178 
179     REG_DMC520_0 = (REG_ST_DMC520 *)(uint32_t)REG_DMC520_0_BA;
180     REG_DDRPHY_CONFIG_0 =
181         (REG_ST_DDRPHY_CONFIG_t *)(uint32_t)REG_DDRPHY_CONFIG_0_BA;
182 
183     g_DDR4_DMC520_INIT_CH = 0;
184 
185     FWK_LOG_INFO("[DDR] Initializing DDR ch0");
186 
187     ddr_init_mc0_mp(REG_DMC520_0);
188 
189     /* allocate 62MiB secure DRAM for secure software */
190     if (ddr_is_secure_dram_enabled()) {
191         FWK_LOG_INFO("[DDR] secure DRAM enabled");
192         REG_DMC520_0->access_address_min0_31_00_next = 0xFBE0000C;
193         REG_DMC520_0->access_address_min0_43_32_next = 0x00000000;
194         REG_DMC520_0->access_address_max0_31_00_next = 0xFFBF0000;
195         REG_DMC520_0->access_address_max0_43_32_next = 0x00000000;
196     }
197 
198     status = ddr_init_phy0_mp(REG_DDRPHY_CONFIG_0, 0);
199     if (status != 0) {
200         FWK_LOG_CRIT("[DDR] ch0 initialize failed. ddr_init_phy0_mp()");
201         return status;
202     }
203     status = ddr_init_phy1_mp(REG_DDRPHY_CONFIG_0, 0);
204     if (status != 0) {
205         FWK_LOG_CRIT("[DDR] ch0 initialize failed. ddr_init_phy1_mp()");
206         return status;
207     }
208 
209     status = ddr_init_sdram_mp(REG_DDRPHY_CONFIG_0, 0);
210     if (status != 0) {
211         FWK_LOG_CRIT("[DDR] ch0 initialize failed. ddr_init_sdram_mp()");
212         return status;
213     }
214 
215     status = ddr_init_mc1_mp(REG_DMC520_0);
216     if (status != 0) {
217         FWK_LOG_CRIT("[DDR] ch0 initialize failed. ddr_init_mc1_mp()");
218         return status;
219     }
220 
221     status = ddr_init_train_mp(REG_DDRPHY_CONFIG_0, 0);
222     if (status != 0) {
223         FWK_LOG_CRIT("[DDR] ch0 fatal error occurred.");
224         return status;
225     }
226     status = ddr_init_mc2_mp(REG_DMC520_0);
227     if (status != 0) {
228         FWK_LOG_CRIT("[DDR] ch0 initialize failed. ddr_init_mc1_mp()");
229         return status;
230     }
231 
232     FWK_LOG_INFO("[DDR] Finished initializing DDR ch0");
233 
234     return 0;
235 }
236 
237 /* ch1 : DMC 1 + PHY 1 */
ddr_ch1_init_mp(void)238 int ddr_ch1_init_mp(void)
239 {
240     int status;
241     REG_ST_DMC520 *REG_DMC520_1;
242     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG_1;
243 
244     REG_DMC520_1 = (REG_ST_DMC520 *)(uint32_t)REG_DMC520_1_BA;
245     REG_DDRPHY_CONFIG_1 =
246         (REG_ST_DDRPHY_CONFIG_t *)(uint32_t)REG_DDRPHY_CONFIG_1_BA;
247 
248     g_DDR4_DMC520_INIT_CH = 1;
249 
250     FWK_LOG_INFO("[DDR] Initializing DDR ch1");
251 
252     status = ddr_init_mc0_mp(REG_DMC520_1);
253     if (status != 0) {
254         FWK_LOG_CRIT("[DDR] ch1 initialize failed. ddr_init_mc0_mp()");
255         return status;
256     }
257 
258     status = ddr_init_phy0_mp(REG_DDRPHY_CONFIG_1, 0);
259     if (status != 0) {
260         FWK_LOG_CRIT("[DDR] ch1 initialize failed. ddr_init_phy0_mp()");
261         return status;
262     }
263 
264     status = ddr_init_phy1_mp(REG_DDRPHY_CONFIG_1, 0);
265     if (status != 0) {
266         FWK_LOG_CRIT("[DDR] ch1 initialize failed. ddr_init_phy1_mp()");
267         return status;
268     }
269 
270     status = ddr_init_sdram_mp(REG_DDRPHY_CONFIG_1, 0);
271     if (status != 0) {
272         FWK_LOG_CRIT("[DDR] ch1 initialize failed. ddr_init_sdram_mp()");
273         return status;
274     }
275 
276     status = ddr_init_mc1_mp(REG_DMC520_1);
277     if (status != 0) {
278         FWK_LOG_CRIT("[DDR] ch1 initialize failed. ddr_init_mc1_mp()");
279         return status;
280     }
281 
282     status = ddr_init_train_mp(REG_DDRPHY_CONFIG_1, 0);
283     if (status != 0) {
284         FWK_LOG_CRIT("[DDR] ch1 fatal error occurred.");
285         return status;
286     }
287 
288     status = ddr_init_mc2_mp(REG_DMC520_1);
289     if (status != 0) {
290         FWK_LOG_CRIT("[DDR] ch1 initialize failed. ddr_init_mc2_mp()");
291         return status;
292     }
293 
294     FWK_LOG_INFO("[DDR] Finished initializing DDR ch1");
295 
296     return 0;
297 }
298 
ddr_init_mc0_mp(REG_ST_DMC520 * REG_DMC520)299 int ddr_init_mc0_mp(REG_ST_DMC520 *REG_DMC520)
300 {
301     uint32_t ddr_memory_type;
302     ddr_memory_type = fw_get_memory_type();
303 
304     REG_DMC520->memc_status;
305     REG_DMC520->memc_config;
306 
307     REG_DMC520->address_control_next = fw_get_address_control_next();
308     REG_DMC520->decode_control_next = 0x00000002;
309     REG_DMC520->format_control = 0x00000003;
310     REG_DMC520->address_map_next = 0xFF800004;
311     REG_DMC520->memory_address_max_31_00_next = 0xFFFF001F;
312     REG_DMC520->memory_address_max_43_32_next = 0x00000007;
313     REG_DMC520->access_address_min0_31_00_next = 0x00000000;
314     REG_DMC520->access_address_min0_43_32_next = 0x00000000;
315     REG_DMC520->access_address_max0_31_00_next = 0x00000000;
316     REG_DMC520->access_address_max0_43_32_next = 0x00000000;
317     REG_DMC520->access_address_min1_31_00_next = 0x00000000;
318     REG_DMC520->access_address_min1_43_32_next = 0x00000000;
319     REG_DMC520->access_address_max1_31_00_next = 0x00000000;
320     REG_DMC520->access_address_max1_43_32_next = 0x00000000;
321     REG_DMC520->access_address_min2_31_00_next = 0x00000000;
322     REG_DMC520->access_address_min2_43_32_next = 0x00000000;
323     REG_DMC520->access_address_max2_31_00_next = 0x00000000;
324     REG_DMC520->access_address_max2_43_32_next = 0x00000000;
325     REG_DMC520->access_address_min3_31_00_next = 0x00000000;
326     REG_DMC520->access_address_min3_43_32_next = 0x00000000;
327     REG_DMC520->access_address_max3_31_00_next = 0x00000000;
328     REG_DMC520->access_address_max3_43_32_next = 0x00000000;
329     REG_DMC520->access_address_min4_31_00_next = 0x00000000;
330     REG_DMC520->access_address_min4_43_32_next = 0x00000000;
331     REG_DMC520->access_address_max4_31_00_next = 0x00000000;
332     REG_DMC520->access_address_max4_43_32_next = 0x00000000;
333     REG_DMC520->access_address_min5_31_00_next = 0x00000000;
334     REG_DMC520->access_address_min5_43_32_next = 0x00000000;
335     REG_DMC520->access_address_max5_31_00_next = 0x00000000;
336     REG_DMC520->access_address_max5_43_32_next = 0x00000000;
337     REG_DMC520->access_address_min6_31_00_next = 0x00000000;
338     REG_DMC520->access_address_min6_43_32_next = 0x00000000;
339     REG_DMC520->access_address_max6_31_00_next = 0x00000000;
340     REG_DMC520->access_address_max6_43_32_next = 0x00000000;
341     REG_DMC520->access_address_min7_31_00_next = 0x00000000;
342     REG_DMC520->access_address_min7_43_32_next = 0x00000000;
343     REG_DMC520->access_address_max7_31_00_next = 0x00000000;
344     REG_DMC520->access_address_max7_43_32_next = 0x00000000;
345     REG_DMC520->dci_replay_type_next = 0x00000002;
346     REG_DMC520->dci_strb = 0x0000000F;
347     REG_DMC520->refresh_control_next = 0x00000000;
348     REG_DMC520->memory_type_next = fw_get_memory_type_next();
349     REG_DMC520->feature_config = 0x00000000;
350     REG_DMC520->scrub_control0_next = 0x08000000;
351     REG_DMC520->scrub_control1_next = 0x08000000;
352     REG_DMC520->scrub_control2_next = 0x08000000;
353     REG_DMC520->scrub_control3_next = 0x08000000;
354     REG_DMC520->scrub_control4_next = 0x08000000;
355     REG_DMC520->scrub_control5_next = 0x08000000;
356     REG_DMC520->scrub_control6_next = 0x08000000;
357     REG_DMC520->scrub_control7_next = 0x08000000;
358 
359     if ((ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
360         (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH))
361         REG_DMC520->feature_control_next = 0x00A100F0;
362     else if (
363         (ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
364         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
365         REG_DMC520->feature_control_next = 0x000000F8;
366     else if (
367         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH) ||
368         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH))
369         REG_DMC520->feature_control_next = 0x00A100F8;
370 
371     REG_DMC520->mux_control_next = 0x000000D0;
372 
373     if (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH)
374         REG_DMC520->rank_remap_control_next = 0xFEDC10BA;
375     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
376         REG_DMC520->rank_remap_control_next = 0xFEDC3210;
377     else if (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH)
378         REG_DMC520->rank_remap_control_next = 0xFEDCBA10;
379     else if (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH)
380         REG_DMC520->rank_remap_control_next = 0xFEDCBA90;
381     else if (
382         (ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
383         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
384         REG_DMC520->rank_remap_control_next = 0xFEDC90BA;
385 
386     REG_DMC520->t_refi_next = 0x0009040F;
387     REG_DMC520->t_rfc_next = 0x0005D976;
388     REG_DMC520->t_mrr_next = 0x00000001;
389     REG_DMC520->t_mrw_next = 0x00180018;
390     REG_DMC520->t_rdpden_next = 0x00000014;
391     REG_DMC520->t_rcd_next = 0x00000010;
392     REG_DMC520->t_ras_next = 0x00000024;
393     REG_DMC520->t_rp_next = 0x00000010;
394     REG_DMC520->t_rpall_next = 0x00000010;
395     REG_DMC520->t_rrd_next = 0x00000604;
396     REG_DMC520->t_act_window_next = 0x00000017;
397     REG_DMC520->t_rtr_next = 0x000E0604;
398     REG_DMC520->t_rtw_next = 0x000F0F0F;
399     REG_DMC520->t_rtp_next = 0x00000009;
400     REG_DMC520->t_wr_next = 0x00000021;
401     REG_DMC520->t_wtr_next = 0x00181818;
402     REG_DMC520->t_wtw_next = 0x000A0604;
403     REG_DMC520->t_xmpd_next = 0x00000480;
404     REG_DMC520->t_ep_next = 0x00000006;
405     REG_DMC520->t_xp_next = 0x00100007;
406     REG_DMC520->t_esr_next = 0x00000007;
407     REG_DMC520->t_xsr_next = 0x03000180;
408     REG_DMC520->t_esrck_next = 0x0000000B;
409     REG_DMC520->t_ckxsr_next = 0x0000000B;
410     REG_DMC520->t_cmd_next = 0x00000000;
411     REG_DMC520->t_parity_next = 0x00001A00;
412     REG_DMC520->t_zqcs_next = 0x00000080;
413     REG_DMC520->t_rw_odt_clr_next = 0x0000000C;
414 
415     if ((ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
416         (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)) {
417         REG_DMC520->t_rddata_en_next = 0x0000000C;
418         REG_DMC520->t_phyrdlat_next = 0x0000001E;
419         REG_DMC520->t_phywrlat_next = 0x0000000A;
420     } else if (
421         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH) ||
422         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH)) {
423         REG_DMC520->t_rddata_en_next = 0x0000000B;
424         REG_DMC520->t_phyrdlat_next = 0x00000022;
425         REG_DMC520->t_phywrlat_next = 0x00000009;
426     } else if (
427         (ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
428         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH)) {
429         REG_DMC520->t_rddata_en_next = 0x0000000B;
430         REG_DMC520->t_phyrdlat_next = 0x00000021;
431         REG_DMC520->t_phywrlat_next = 0x00000009;
432     }
433 
434     REG_DMC520->rdlvl_control_next = 0x00000000;
435     REG_DMC520->rdlvl_mrs_next = 0x00000000;
436     REG_DMC520->t_rdlvl_en_next = 0x00000000;
437     REG_DMC520->t_rdlvl_rr_next = 0x00000000;
438     REG_DMC520->wrlvl_control_next = 0x00000000;
439     REG_DMC520->wrlvl_mrs_next = 0x00000000;
440     REG_DMC520->t_wrlvl_en_next = 0x00000000;
441     REG_DMC520->t_wrlvl_ww_next = 0x00000000;
442     REG_DMC520->phy_power_control_next = 0x09999900;
443     REG_DMC520->t_lpresp_next = 0x00000000;
444     REG_DMC520->phy_update_control_next = 0x001F0000;
445     REG_DMC520->odt_timing_next = 0x0C020800;
446     REG_DMC520->t_odth_next = 0x00000008;
447 
448     if (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH)
449         REG_DMC520->odt_wr_control_31_00_next = 0x08040000;
450     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
451         REG_DMC520->odt_wr_control_31_00_next = 0x0A050A05;
452     else if (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH)
453         REG_DMC520->odt_wr_control_31_00_next = 0x00000201;
454     else if (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH)
455         REG_DMC520->odt_wr_control_31_00_next = 0x00000001;
456     else if (
457         (ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
458         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
459         REG_DMC520->odt_wr_control_31_00_next = 0x00040000;
460 
461     REG_DMC520->odt_wr_control_63_32_next = 0x00000000;
462 
463     if ((ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
464         (ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
465         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
466         REG_DMC520->odt_rd_control_31_00_next = 0x00000000;
467     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
468         REG_DMC520->odt_rd_control_31_00_next = 0x02010804;
469 
470     REG_DMC520->odt_rd_control_63_32_next = 0x00000000;
471 
472     if (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH) {
473         // for bit swap on sever board
474         if (g_DDR4_DMC520_INIT_CH == 0) {
475             REG_DMC520->dq_map_control_15_00_next = 0x2D032E0D;
476             REG_DMC520->dq_map_control_31_16_next = 0x2E0D0E24;
477             REG_DMC520->dq_map_control_47_32_next = 0x2B152B15;
478             REG_DMC520->dq_map_control_63_48_next = 0x35162C0B;
479             REG_DMC520->dq_map_control_71_64_next = 0x00AA2E03;
480         } else if (g_DDR4_DMC520_INIT_CH == 1) {
481             REG_DMC520->dq_map_control_15_00_next = 0x240E2D0E;
482             REG_DMC520->dq_map_control_31_16_next = 0x31120923;
483             REG_DMC520->dq_map_control_47_32_next = 0x350C2B15;
484             REG_DMC520->dq_map_control_63_48_next = 0x2C0B3616;
485             REG_DMC520->dq_map_control_71_64_next = 0x00AA3118;
486         }
487     } else if (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) {
488         // for bit swap on sever board
489         if (g_DDR4_DMC520_INIT_CH == 0) {
490             REG_DMC520->dq_map_control_15_00_next = 0x0B36042E;
491             REG_DMC520->dq_map_control_31_16_next = 0x0C2C2D0D;
492             REG_DMC520->dq_map_control_47_32_next = 0x2E0D0C2C;
493             REG_DMC520->dq_map_control_63_48_next = 0x2E03162C;
494             REG_DMC520->dq_map_control_71_64_next = 0x00AA2E0D;
495         } else if (g_DDR4_DMC520_INIT_CH == 1) {
496             REG_DMC520->dq_map_control_15_00_next = 0x162B032D;
497             REG_DMC520->dq_map_control_31_16_next = 0x0A27370E;
498             REG_DMC520->dq_map_control_47_32_next = 0x24040C2C;
499             REG_DMC520->dq_map_control_63_48_next = 0x230E0C35;
500             REG_DMC520->dq_map_control_71_64_next = 0x00AA3113;
501         }
502     } else {
503         REG_DMC520->dq_map_control_15_00_next =
504             fw_get_ddr4_sdram_dq_map_control(0);
505         REG_DMC520->dq_map_control_31_16_next =
506             fw_get_ddr4_sdram_dq_map_control(1);
507         REG_DMC520->dq_map_control_47_32_next =
508             fw_get_ddr4_sdram_dq_map_control(2);
509         REG_DMC520->dq_map_control_63_48_next =
510             fw_get_ddr4_sdram_dq_map_control(3);
511         REG_DMC520->dq_map_control_71_64_next =
512             (fw_get_ddr4_sdram_dq_map_control(4) | 0x00AA0000);
513     }
514 
515     REG_DMC520->phy_rdwrdata_cs_mask_31_00 = 0x00000000;
516     REG_DMC520->phy_rdwrdata_cs_mask_63_32 = 0x00000000;
517     REG_DMC520->phy_request_cs_remap = 0x00000000;
518     REG_DMC520->odt_cp_control_31_00_next = 0x08040201;
519     REG_DMC520->odt_cp_control_63_32_next = 0x80402010;
520     REG_DMC520->interrupt_control = 0x000003FF;
521 
522 #ifdef DDR_DBI_ON
523     REG_DMC520->t_rtw_next += 0x00030303;
524     REG_DMC520->t_rtp_next += 0x00000003; // + tDBI=3clk
525     REG_DMC520->t_rddata_en_next += 0x00000003;
526     REG_DMC520->odt_timing_next += 0x03030000;
527     REG_DMC520->t_rw_odt_clr_next += 0x00000003;
528     REG_DMC520->feature_config |= 0x00000010;
529     REG_DMC520->feature_control_next |= 0x00000005;
530 #endif // DDR_DBI_ON
531 
532 #ifdef DDR_CA_Parity_ON
533     dmb();
534     REG_DMC520->t_mrw_next += 0x00040004;
535     REG_DMC520->t_wr_next += 0x00000004;
536     REG_DMC520->t_wtr_next += 0x00040404;
537     REG_DMC520->t_esrck_next += 0x00000004;
538     REG_DMC520->t_parity_next += 0x00000400;
539     REG_DMC520->t_rddata_en_next += 0x00000004;
540     REG_DMC520->t_phyrdlat_next += 0x00000004;
541     REG_DMC520->t_phywrlat_next += 0x00000004;
542 #endif // DDR_CA_Parity_ON
543 
544 #ifdef DDR_CRC_ON
545     dmb();
546     REG_DMC520->t_wr_next += 0x00000005;
547     REG_DMC520->t_wtr_next += 0x00050505;
548     REG_DMC520->t_wtw_next += 0x00000001;
549     REG_DMC520->t_parity_next = 0x00002F00;
550     REG_DMC520->odt_timing_next += 0x00000100;
551     REG_DMC520->t_odth_next += 0x00000001;
552     REG_DMC520->feature_control_next |= 0x00000002;
553 #endif // DDR_CRC_ON
554 
555     if (dram_ecc_is_enabled())
556         REG_DMC520->feature_config |= 0x00000015;
557 
558     // UPDATE
559     REG_DMC520->direct_cmd = 0x0001000C;
560 
561     // TRAIN
562     REG_DMC520->direct_addr = 0x00000004;
563     REG_DMC520->direct_cmd = 0x0001000A;
564 
565     // dfi_data_byte_disable control
566     if (fw_get_ddr4_sdram_ecc_available()) {
567         if ((REG_DMC520->feature_config & 0x3) == 0) {
568             // [1:0] ecc_enable = b01 (ECC BYTE dfi_data_byte_disable=0)
569             REG_DMC520->feature_config |= 0x00000001;
570         }
571     } else {
572         // [1:0] ecc_enable = b00 (ECC BYTE dfi_data_byte_disable=1)
573         REG_DMC520->feature_config &= 0xFFFFFFFC;
574     }
575 
576     REG_DMC520->memc_status;
577     REG_DMC520->memc_config;
578 
579     return 0;
580 }
581 
ddr_init_phy0_mp(REG_ST_DDRPHY_CONFIG_t * REG_DDRPHY_CONFIG,int retention_en)582 int ddr_init_phy0_mp(
583     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
584     int retention_en)
585 {
586     uint32_t ddr_memory_type;
587     ddr_memory_type = fw_get_memory_type();
588 
589     REG_DDRPHY_CONFIG->PGSR0;
590     REG_DDRPHY_CONFIG->PGSR1;
591 
592     REG_DDRPHY_CONFIG->PGCR0 = 0x07D81E01;
593     REG_DDRPHY_CONFIG->PGCR1 = 0x02004660;
594     REG_DDRPHY_CONFIG->PGCR2 = 0x00012480;
595     REG_DDRPHY_CONFIG->PTR0 = 0x42C21510;
596     REG_DDRPHY_CONFIG->PTR1 = 0xD05612C0;
597     REG_DDRPHY_CONFIG->PTR3 = 0x18082356;
598     REG_DDRPHY_CONFIG->PTR4 = 0x10034156;
599     REG_DDRPHY_CONFIG->PLLCR = 0x00038000;
600     REG_DDRPHY_CONFIG->DXCCR = 0x20C00004;
601     REG_DDRPHY_CONFIG->DSGCR = 0x0020403E;
602 
603     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
604         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH)) {
605         REG_DDRPHY_CONFIG->RANKIDR = 0x00000002;
606         REG_DDRPHY_CONFIG->ODTCR = 0x00040000;
607         REG_DDRPHY_CONFIG->DCR = 0x38000404;
608     } else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH) {
609         REG_DDRPHY_CONFIG->RANKIDR = 0x00000000;
610         REG_DDRPHY_CONFIG->ODTCR = 0x00050004;
611         REG_DDRPHY_CONFIG->RANKIDR = 0x00000001;
612         REG_DDRPHY_CONFIG->ODTCR = 0x000A0008;
613         REG_DDRPHY_CONFIG->RANKIDR = 0x00000002;
614         REG_DDRPHY_CONFIG->ODTCR = 0x00050001;
615         REG_DDRPHY_CONFIG->RANKIDR = 0x00000003;
616         REG_DDRPHY_CONFIG->ODTCR = 0x000A0002;
617         REG_DDRPHY_CONFIG->DCR = 0x08000404;
618     } else if (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH) {
619         REG_DDRPHY_CONFIG->RANKIDR = 0x00000000;
620         REG_DDRPHY_CONFIG->ODTCR = 0x00010000;
621         REG_DDRPHY_CONFIG->RANKIDR = 0x00000001;
622         REG_DDRPHY_CONFIG->ODTCR = 0x00020000;
623         REG_DDRPHY_CONFIG->DCR = 0x38000404;
624     } else if (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) {
625         REG_DDRPHY_CONFIG->RANKIDR = 0x00000000;
626         REG_DDRPHY_CONFIG->ODTCR = 0x00010000;
627         REG_DDRPHY_CONFIG->DCR = 0x38000404;
628     } else if (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) {
629         REG_DDRPHY_CONFIG->RANKIDR = 0x00000002;
630         REG_DDRPHY_CONFIG->ODTCR = 0x00040000;
631         REG_DDRPHY_CONFIG->RANKIDR = 0x00000003;
632         REG_DDRPHY_CONFIG->ODTCR = 0x00080000;
633         REG_DDRPHY_CONFIG->DCR = 0x08000404;
634     }
635 
636     REG_DDRPHY_CONFIG->DTPR0 = 0x06241009;
637     REG_DDRPHY_CONFIG->DTPR1 = 0x28270008;
638     REG_DDRPHY_CONFIG->DTPR2 = 0x00060200;
639     REG_DDRPHY_CONFIG->DTPR3 = 0x22800101;
640     REG_DDRPHY_CONFIG->DTPR4 = 0x01760B07;
641     REG_DDRPHY_CONFIG->DTPR5 = 0x00341008;
642     REG_DDRPHY_CONFIG->DTPR6 = 0x00000505;
643 
644     if ((ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
645         (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)) {
646         if (retention_en == 0)
647             REG_DDRPHY_CONFIG->RDIMMGCR0 = 0xBC410001;
648         else
649             REG_DDRPHY_CONFIG->RDIMMGCR0 = 0xBC410009;
650 
651         REG_DDRPHY_CONFIG->RDIMMGCR1 = 0x00001903;
652         REG_DDRPHY_CONFIG->RDIMMGCR2 = 0x07FFFF3F;
653         REG_DDRPHY_CONFIG->RDIMMCR0 = 0x00555100;
654         REG_DDRPHY_CONFIG->RDIMMCR1 = 0x00C0A208;
655         REG_DDRPHY_CONFIG->RDIMMCR2 = 0x002C0100;
656         REG_DDRPHY_CONFIG->RDIMMCR3 = 0x00000000;
657         REG_DDRPHY_CONFIG->RDIMMCR4 = 0x00070000;
658     }
659 
660     REG_DDRPHY_CONFIG->MR0 = 0x00000830;
661     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
662         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH)) {
663         REG_DDRPHY_CONFIG->MR1 = 0x00000703;
664         REG_DDRPHY_CONFIG->MR2 = 0x00000010;
665     } else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH) {
666         REG_DDRPHY_CONFIG->MR1 = 0x00000701;
667         REG_DDRPHY_CONFIG->MR2 = 0x00000210;
668     } else if (
669         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
670         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH) ||
671         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH)) {
672         REG_DDRPHY_CONFIG->MR1 = 0x00000701;
673         REG_DDRPHY_CONFIG->MR2 = 0x00000010;
674     }
675 
676     REG_DDRPHY_CONFIG->MR3 = 0x00000200;
677     REG_DDRPHY_CONFIG->MR4 = 0x00000000;
678     REG_DDRPHY_CONFIG->MR5 = 0x00000500;
679 
680     if ((ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
681         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
682         REG_DDRPHY_CONFIG->MR6 = 0x0000082B;
683     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
684         REG_DDRPHY_CONFIG->MR6 = 0x00000829;
685     else if (
686         (ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
687         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
688         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
689         REG_DDRPHY_CONFIG->MR6 = 0x0000082D;
690 
691     REG_DDRPHY_CONFIG->DTCR0 = 0x8000B0C7;
692     if (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH)
693         REG_DDRPHY_CONFIG->DTCR1 = 0x000C2237;
694     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
695         REG_DDRPHY_CONFIG->DTCR1 = 0x000F0237;
696     else if (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH)
697         REG_DDRPHY_CONFIG->DTCR1 = 0x00030237;
698     else if (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH)
699         REG_DDRPHY_CONFIG->DTCR1 = 0x00010237;
700     else if (
701         (ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
702         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
703         REG_DDRPHY_CONFIG->DTCR1 = 0x00042237;
704 
705     REG_DDRPHY_CONFIG->DTAR0 = 0x04000000;
706     REG_DDRPHY_CONFIG->DTAR1 = 0x00010000;
707     REG_DDRPHY_CONFIG->DTAR2 = 0x00030002;
708     REG_DDRPHY_CONFIG->DCUTPR = 0x000000FF;
709     REG_DDRPHY_CONFIG->BISTRR = 0x03E40000;
710     REG_DDRPHY_CONFIG->BISTUDPR = 0xA5A5A5A5;
711     REG_DDRPHY_CONFIG->RIOCR0 = 0x0FFF0000;
712     REG_DDRPHY_CONFIG->RIOCR1 = 0xFF00FF00;
713 
714     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
715         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH)) {
716         REG_DDRPHY_CONFIG->RIOCR2 = 0x0000008A;
717         REG_DDRPHY_CONFIG->RIOCR4 = 0x0000008A;
718         REG_DDRPHY_CONFIG->RIOCR5 = 0x0000008A;
719         REG_DDRPHY_CONFIG->ACIOCR0 = 0x30003C10;
720         REG_DDRPHY_CONFIG->ACIOCR1 = 0x00000000;
721         REG_DDRPHY_CONFIG->ACIOCR3 = 0x0000008A;
722     } else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH) {
723         REG_DDRPHY_CONFIG->RIOCR2 = 0x00000000;
724         REG_DDRPHY_CONFIG->RIOCR4 = 0x00000000;
725         REG_DDRPHY_CONFIG->RIOCR5 = 0x00000000;
726         REG_DDRPHY_CONFIG->ACIOCR0 = 0xF0003C10;
727         REG_DDRPHY_CONFIG->ACIOCR1 = 0x00000000;
728         REG_DDRPHY_CONFIG->ACIOCR3 = 0x00000000;
729     } else if (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH) {
730         REG_DDRPHY_CONFIG->RIOCR2 = 0x000000A0;
731         REG_DDRPHY_CONFIG->RIOCR4 = 0x000000A0;
732         REG_DDRPHY_CONFIG->RIOCR5 = 0x000000A0;
733         REG_DDRPHY_CONFIG->ACIOCR0 = 0x30003C10;
734         REG_DDRPHY_CONFIG->ACIOCR1 = 0x00000000;
735         REG_DDRPHY_CONFIG->ACIOCR3 = 0x000000A0;
736     } else if (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) {
737         REG_DDRPHY_CONFIG->RIOCR2 = 0x000000A8;
738         REG_DDRPHY_CONFIG->RIOCR4 = 0x000000A8;
739         REG_DDRPHY_CONFIG->RIOCR5 = 0x000000A8;
740         REG_DDRPHY_CONFIG->ACIOCR0 = 0x30003C10;
741         REG_DDRPHY_CONFIG->ACIOCR1 = 0x00000000;
742         REG_DDRPHY_CONFIG->ACIOCR3 = 0x000000A8;
743     } else if (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) {
744         REG_DDRPHY_CONFIG->RIOCR2 = 0x0000000A;
745         REG_DDRPHY_CONFIG->RIOCR4 = 0x0000000A;
746         REG_DDRPHY_CONFIG->RIOCR5 = 0x0000000A;
747         REG_DDRPHY_CONFIG->ACIOCR0 = 0x30003C10;
748         REG_DDRPHY_CONFIG->ACIOCR1 = 0x00000000;
749         REG_DDRPHY_CONFIG->ACIOCR3 = 0x0000000A;
750     }
751 
752     REG_DDRPHY_CONFIG->IOVCR0 = 0x0F090025;
753     REG_DDRPHY_CONFIG->IOVCR1 = 0x00000109;
754 
755     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
756         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
757         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH)) {
758         REG_DDRPHY_CONFIG->VTCR0 = 0x70030AAD;
759         REG_DDRPHY_CONFIG->VTCR1 = 0x0FC0F076;
760         REG_DDRPHY_CONFIG->ZQCR = 0x03058F00;
761         REG_DDRPHY_CONFIG->ZQ0PR = 0x0001DD1D;
762         REG_DDRPHY_CONFIG->ZQ1PR = 0x00079979;
763         REG_DDRPHY_CONFIG->ZQ2PR = 0x000BDDBD;
764         REG_DDRPHY_CONFIG->ZQ3PR = 0x000BDDBD;
765     } else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH) {
766         REG_DDRPHY_CONFIG->VTCR0 = 0x7002C9A9;
767         REG_DDRPHY_CONFIG->VTCR1 = 0x0F77F076;
768         REG_DDRPHY_CONFIG->ZQCR = 0x03058F00;
769         REG_DDRPHY_CONFIG->ZQ0PR = 0x00019919;
770         REG_DDRPHY_CONFIG->ZQ1PR = 0x0005DD5D;
771         REG_DDRPHY_CONFIG->ZQ2PR = 0x00011111;
772         REG_DDRPHY_CONFIG->ZQ3PR = 0x00011111;
773     } else if (
774         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
775         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH)) {
776         REG_DDRPHY_CONFIG->VTCR0 = 0x7002EA2B;
777         REG_DDRPHY_CONFIG->VTCR1 = 0x0FC0F076;
778         REG_DDRPHY_CONFIG->ZQCR = 0x03058F00;
779         REG_DDRPHY_CONFIG->ZQ0PR = 0x0001DD1D;
780         REG_DDRPHY_CONFIG->ZQ1PR = 0x0009DD9D;
781         REG_DDRPHY_CONFIG->ZQ2PR = 0x000BDDBD;
782         REG_DDRPHY_CONFIG->ZQ3PR = 0x000BDDBD;
783     }
784 
785     REG_DDRPHY_CONFIG->DX0GCR0 = 0x40000205;
786     REG_DDRPHY_CONFIG->DX0GCR1 = 0xAAAA0000;
787     REG_DDRPHY_CONFIG->DX0GCR2 = 0x00000000;
788     REG_DDRPHY_CONFIG->DX0GCR3 = 0xFFFC0808;
789 
790     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
791         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
792         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
793         REG_DDRPHY_CONFIG->DX0GCR5 = 0x2B2B2B2B;
794     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
795         REG_DDRPHY_CONFIG->DX0GCR5 = 0x3A3A3A3A;
796     else if (
797         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
798         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
799         REG_DDRPHY_CONFIG->DX0GCR5 = 0x32323232;
800 
801     REG_DDRPHY_CONFIG->DX0GCR7 = 0x00810808;
802     REG_DDRPHY_CONFIG->DX1GCR0 = 0x40000205;
803     REG_DDRPHY_CONFIG->DX1GCR1 = 0xAAAA0000;
804     REG_DDRPHY_CONFIG->DX1GCR2 = 0x00000000;
805     REG_DDRPHY_CONFIG->DX1GCR3 = 0xFFFC0808;
806 
807     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
808         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
809         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
810         REG_DDRPHY_CONFIG->DX1GCR5 = 0x2B2B2B2B;
811     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
812         REG_DDRPHY_CONFIG->DX1GCR5 = 0x3A3A3A3A;
813     else if (
814         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
815         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
816         REG_DDRPHY_CONFIG->DX1GCR5 = 0x32323232;
817 
818     REG_DDRPHY_CONFIG->DX1GCR7 = 0x00810808;
819     REG_DDRPHY_CONFIG->DX2GCR0 = 0x40000205;
820     REG_DDRPHY_CONFIG->DX2GCR1 = 0xAAAA0000;
821     REG_DDRPHY_CONFIG->DX2GCR2 = 0x00000000;
822     REG_DDRPHY_CONFIG->DX2GCR3 = 0xFFFC0808;
823 
824     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
825         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
826         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
827         REG_DDRPHY_CONFIG->DX2GCR5 = 0x2B2B2B2B;
828     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
829         REG_DDRPHY_CONFIG->DX2GCR5 = 0x3A3A3A3A;
830     else if (
831         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
832         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
833         REG_DDRPHY_CONFIG->DX2GCR5 = 0x32323232;
834 
835     REG_DDRPHY_CONFIG->DX2GCR7 = 0x00810808;
836     REG_DDRPHY_CONFIG->DX3GCR0 = 0x40000205;
837     REG_DDRPHY_CONFIG->DX3GCR1 = 0xAAAA0000;
838     REG_DDRPHY_CONFIG->DX3GCR2 = 0x00000000;
839     REG_DDRPHY_CONFIG->DX3GCR3 = 0xFFFC0808;
840 
841     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
842         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
843         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
844         REG_DDRPHY_CONFIG->DX3GCR5 = 0x2B2B2B2B;
845     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
846         REG_DDRPHY_CONFIG->DX3GCR5 = 0x3A3A3A3A;
847     else if (
848         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
849         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
850         REG_DDRPHY_CONFIG->DX3GCR5 = 0x32323232;
851 
852     REG_DDRPHY_CONFIG->DX3GCR7 = 0x00810808;
853     REG_DDRPHY_CONFIG->DX4GCR0 = 0x40000205;
854     REG_DDRPHY_CONFIG->DX4GCR1 = 0xAAAA0000;
855     REG_DDRPHY_CONFIG->DX4GCR2 = 0x00000000;
856     REG_DDRPHY_CONFIG->DX4GCR3 = 0xFFFC0808;
857 
858     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
859         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
860         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
861         REG_DDRPHY_CONFIG->DX4GCR5 = 0x2B2B2B2B;
862     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
863         REG_DDRPHY_CONFIG->DX4GCR5 = 0x3A3A3A3A;
864     else if (
865         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
866         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
867         REG_DDRPHY_CONFIG->DX4GCR5 = 0x32323232;
868 
869     REG_DDRPHY_CONFIG->DX4GCR7 = 0x00810808;
870     REG_DDRPHY_CONFIG->DX5GCR0 = 0x40000205;
871     REG_DDRPHY_CONFIG->DX5GCR1 = 0xAAAA0000;
872     REG_DDRPHY_CONFIG->DX5GCR2 = 0x00000000;
873     REG_DDRPHY_CONFIG->DX5GCR3 = 0xFFFC0808;
874 
875     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
876         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
877         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
878         REG_DDRPHY_CONFIG->DX5GCR5 = 0x2B2B2B2B;
879     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
880         REG_DDRPHY_CONFIG->DX5GCR5 = 0x3A3A3A3A;
881     else if (
882         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
883         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
884         REG_DDRPHY_CONFIG->DX5GCR5 = 0x32323232;
885 
886     REG_DDRPHY_CONFIG->DX5GCR7 = 0x00810808;
887     REG_DDRPHY_CONFIG->DX6GCR0 = 0x40000205;
888     REG_DDRPHY_CONFIG->DX6GCR1 = 0xAAAA0000;
889     REG_DDRPHY_CONFIG->DX6GCR2 = 0x00000000;
890     REG_DDRPHY_CONFIG->DX6GCR3 = 0xFFFC0808;
891 
892     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
893         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
894         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
895         REG_DDRPHY_CONFIG->DX6GCR5 = 0x2B2B2B2B;
896     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
897         REG_DDRPHY_CONFIG->DX6GCR5 = 0x3A3A3A3A;
898     else if (
899         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
900         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
901         REG_DDRPHY_CONFIG->DX6GCR5 = 0x32323232;
902 
903     REG_DDRPHY_CONFIG->DX6GCR7 = 0x00810808;
904     REG_DDRPHY_CONFIG->DX7GCR0 = 0x40000205;
905     REG_DDRPHY_CONFIG->DX7GCR1 = 0xAAAA0000;
906     REG_DDRPHY_CONFIG->DX7GCR2 = 0x00000000;
907     REG_DDRPHY_CONFIG->DX7GCR3 = 0xFFFC0808;
908 
909     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
910         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
911         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
912         REG_DDRPHY_CONFIG->DX7GCR5 = 0x2B2B2B2B;
913     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
914         REG_DDRPHY_CONFIG->DX7GCR5 = 0x3A3A3A3A;
915     else if (
916         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
917         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
918         REG_DDRPHY_CONFIG->DX7GCR5 = 0x32323232;
919 
920     REG_DDRPHY_CONFIG->DX7GCR7 = 0x00810808;
921     REG_DDRPHY_CONFIG->DX8GCR0 = 0x40000205;
922     REG_DDRPHY_CONFIG->DX8GCR1 = 0xAAAA0000;
923     REG_DDRPHY_CONFIG->DX8GCR2 = 0x00000000;
924     REG_DDRPHY_CONFIG->DX8GCR3 = 0xFFFC0808;
925 
926     if ((ddr_memory_type == UDIMM_4GBPERSLOT_1SLOTPERCH) ||
927         (ddr_memory_type == SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH) ||
928         (ddr_memory_type == UDIMM_8GBPERSLOT_1SLOTPERCH))
929         REG_DDRPHY_CONFIG->DX8GCR5 = 0x2B2B2B2B;
930     else if (ddr_memory_type == RDIMM_16GBPERSLOT_2SLOTPERCH)
931         REG_DDRPHY_CONFIG->DX8GCR5 = 0x3A3A3A3A;
932     else if (
933         (ddr_memory_type == RDIMM_16GBPERSLOT_1SLOTPERCH) ||
934         (ddr_memory_type == SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH))
935         REG_DDRPHY_CONFIG->DX8GCR5 = 0x32323232;
936 
937     REG_DDRPHY_CONFIG->DX8GCR7 = 0x00810808;
938 
939 #ifdef DDR_DBI_ON
940     REG_DDRPHY_CONFIG->PGCR3 =
941         (REG_DDRPHY_CONFIG->PGCR3 & 0xF1FFFF1F) | 0x08000060; // [7:5]RDBICL=3
942     REG_DDRPHY_CONFIG->MR0 = (REG_DDRPHY_CONFIG->MR0 & 0xFFFFFF8B) |
943         0x00000040; // [6:5][2] CL +3 (15 -> 18)
944     REG_DDRPHY_CONFIG->MR5 = (REG_DDRPHY_CONFIG->MR5 & 0xFFFFE3FF) | 0x00001800;
945     REG_DDRPHY_CONFIG->DTCR0 =
946         (REG_DDRPHY_CONFIG->DTCR0 & 0xFFFF3FFF) | 0x00004000; // DBI de-skew
947 #endif // DDR_DBI_ON
948 
949 #ifdef DDR_CRC_ON
950     REG_DDRPHY_CONFIG->MR2 = (REG_DDRPHY_CONFIG->MR2 & 0xFFFFEFFF) | 0x00001000;
951 #endif // DDR_CRC_ON
952 
953 #ifdef DDR_CA_Parity_ON
954     REG_DDRPHY_CONFIG->MR5 = (REG_DDRPHY_CONFIG->MR5 & 0xFFFFFFF8) | 0x00000001;
955 #endif // DDR_CA_Parity_ON
956 
957     if (fw_get_ddr4_sdram_ecc_available()) {
958         REG_DDRPHY_CONFIG->DX8GCR0 = 0x40000205;
959         REG_DDRPHY_CONFIG->DX8GCR1 = 0xAAAA0000;
960         REG_DDRPHY_CONFIG->DX8GCR2 = 0x00000000;
961         REG_DDRPHY_CONFIG->DX8GCR3 = 0xFFFC0808;
962         REG_DDRPHY_CONFIG->DX8GCR7 = 0x00810808;
963     } else {
964         REG_DDRPHY_CONFIG->DX8GCR0 = 0x00023220;
965         REG_DDRPHY_CONFIG->DX8GCR1 = 0x55550000;
966         REG_DDRPHY_CONFIG->DX8GCR2 = 0xAAAAAAAA;
967         REG_DDRPHY_CONFIG->DX8GCR3 = 0xC0FCA4A4;
968         REG_DDRPHY_CONFIG->DX8GCR7 = 0x00E8A4A4;
969     }
970 
971     return 0;
972 }
973 
ddr_init_phy1_mp(REG_ST_DDRPHY_CONFIG_t * REG_DDRPHY_CONFIG,int retention_en)974 int ddr_init_phy1_mp(
975     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
976     int retention_en)
977 {
978     struct ddr_wait_cond wait_cond;
979 
980     if (retention_en == 0)
981         REG_DDRPHY_CONFIG->PIR =
982             (REG_DDRPHY_CONFIG->PIR & 0xFFFFFF8C) | 0x00000073;
983     else
984         REG_DDRPHY_CONFIG->PIR =
985             (REG_DDRPHY_CONFIG->PIR & 0xBFFFFF8C) | 0x40000071;
986 
987     // Wait by completion of PHY initialization.
988     dmb();
989     Wait_for_ddr(1);
990     usleep_en(1);
991 
992     // [0]IDONE, [1]PLDONE, [2]DCDONE, [3]ZCDONE, [31]APLOCK
993     wait_cond.type = DDR_DDRPHY_CONFIG_PGSR0;
994     wait_cond.reg = REG_DDRPHY_CONFIG;
995     wait_cond.mask = 0x8000000F;
996     wait_cond.comp_val = 0x8000000F;
997     synquacer_memc_timer_api->wait(
998         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
999         ddr_check_wait_cond, &wait_cond);
1000 
1001     REG_DDRPHY_CONFIG->PGSR0;
1002     REG_DDRPHY_CONFIG->PGSR1;
1003 
1004     return 0;
1005 }
1006 
ddr_init_sdram_mp(REG_ST_DDRPHY_CONFIG_t * REG_DDRPHY_CONFIG,int retention_en)1007 int ddr_init_sdram_mp(
1008     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
1009     int retention_en)
1010 {
1011     uint32_t mr6;
1012     uint32_t mr6_vref_training_on;
1013     uint32_t mr6_vref_training_off;
1014     uint32_t Addr_Invert;
1015     struct ddr_wait_cond wait_cond;
1016 
1017     if (retention_en == 0) {
1018         REG_DDRPHY_CONFIG->PIR = (REG_DDRPHY_CONFIG->PIR & 0xFFF7FE7E) |
1019             0x00000181 | ((REG_DDRPHY_CONFIG->RDIMMGCR0 & 0x1) << 19);
1020         dmb();
1021         usleep_en(500);
1022 
1023         // Wait by completion of DRAM initialization.
1024         dmb();
1025         Wait_for_ddr(1);
1026         // [0]IDONE, [4]DIDONE
1027         wait_cond.type = DDR_DDRPHY_CONFIG_PGSR0;
1028         wait_cond.reg = REG_DDRPHY_CONFIG;
1029         wait_cond.mask = 0x00000011;
1030         wait_cond.comp_val = 0x00000011;
1031         synquacer_memc_timer_api->wait(
1032             FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
1033             ddr_check_wait_cond, &wait_cond);
1034 
1035         Addr_Invert =
1036             (((REG_DDRPHY_CONFIG->RDIMMCR0 & 0x1) == 0) &&
1037              ((REG_DDRPHY_CONFIG->RDIMMGCR0 & 0x1) == 1));
1038         mr6 = REG_DDRPHY_CONFIG->MR6;
1039         mr6_vref_training_on =
1040             (mr6 & 0xFFFFFF7F) | (1 << 7); // [7]VrefDQ Training Enable = 1
1041         mr6_vref_training_off =
1042             (mr6 & 0xFFFFFF7F) | (0 << 7); // [7]VrefDQ Training Enable = 0
1043 
1044         REG_DDRPHY_CONFIG->SCHCR0 =
1045             (REG_DDRPHY_CONFIG->SCHCR0 & 0xFFFFFF0F) | 0x00000010; // [7:4]CMD
1046 
1047         // VrefDQ Training On
1048         REG_DDRPHY_CONFIG->SCHCR1 = (REG_DDRPHY_CONFIG->SCHCR1 & 0xF000000F) |
1049             ((mr6_vref_training_on << 8) | (0x1 << 6) | (0x2 << 4) |
1050              (0x1 << 2)); //[27:8]SCADDR,[7:6]SCBG,[5:4]SCBK,[2]ALLRANK
1051         REG_DDRPHY_CONFIG->SCHCR0 = (REG_DDRPHY_CONFIG->SCHCR0 & 0xFFFFFFF0) |
1052             0x00000001; // [3:0]SCHTRIG
1053         if (Addr_Invert == 1) { // for RDIMM B-side
1054             REG_DDRPHY_CONFIG->SCHCR1 =
1055                 (REG_DDRPHY_CONFIG->SCHCR1 & 0xF000000F) |
1056                 ((mr6_vref_training_on << 8) | (0x3 << 6) | (0x2 << 4) |
1057                  (0x1 << 2)); //[27:8]SCADDR,[7:6]SCBG,[5:4]SCBK,[2]ALLRANK
1058             REG_DDRPHY_CONFIG->SCHCR0 =
1059                 (REG_DDRPHY_CONFIG->SCHCR0 & 0xFFFFFFF0) |
1060                 0x00000001; // [3:0]SCHTRIG
1061         }
1062         // wait tVREFDQE //
1063         // New VrefDQ Value
1064         REG_DDRPHY_CONFIG->SCHCR1 = (REG_DDRPHY_CONFIG->SCHCR1 & 0xF000000F) |
1065             ((mr6_vref_training_on << 8) | (0x1 << 6) | (0x2 << 4) |
1066              (0x1 << 2)); //[27:8]SCADDR,[7:6]SCBG,[5:4]SCBK,[2]ALLRANK
1067         REG_DDRPHY_CONFIG->SCHCR0 = (REG_DDRPHY_CONFIG->SCHCR0 & 0xFFFFFFF0) |
1068             0x00000001; // [3:0]SCHTRIG
1069         if (Addr_Invert == 1) { // for RDIMM B-side
1070             REG_DDRPHY_CONFIG->SCHCR1 =
1071                 (REG_DDRPHY_CONFIG->SCHCR1 & 0xF000000F) |
1072                 ((mr6_vref_training_on << 8) | (0x3 << 6) | (0x2 << 4) |
1073                  (0x1 << 2)); //[27:8]SCADDR,[7:6]SCBG,[5:4]SCBK,[2]ALLRANK
1074             REG_DDRPHY_CONFIG->SCHCR0 =
1075                 (REG_DDRPHY_CONFIG->SCHCR0 & 0xFFFFFFF0) |
1076                 0x00000001; // [3:0]SCHTRIG
1077         }
1078         // wait tVREFDQE //
1079         // VrefDQ Training Off
1080         REG_DDRPHY_CONFIG->SCHCR1 = (REG_DDRPHY_CONFIG->SCHCR1 & 0xF000000F) |
1081             ((mr6_vref_training_off << 8) | (0x1 << 6) | (0x2 << 4) |
1082              (0x1 << 2)); //[27:8]SCADDR,[7:6]SCBG,[5:4]SCBK,[2]ALLRANK
1083         REG_DDRPHY_CONFIG->SCHCR0 = (REG_DDRPHY_CONFIG->SCHCR0 & 0xFFFFFFF0) |
1084             0x00000001; // [3:0]SCHTRIG
1085         if (Addr_Invert == 1) { // for RDIMM B-side
1086             REG_DDRPHY_CONFIG->SCHCR1 =
1087                 (REG_DDRPHY_CONFIG->SCHCR1 & 0xF000000F) |
1088                 ((mr6_vref_training_off << 8) | (0x3 << 6) | (0x2 << 4) |
1089                  (0x1 << 2)); //[27:8]SCADDR,[7:6]SCBG,[5:4]SCBK,[2]ALLRANK
1090             REG_DDRPHY_CONFIG->SCHCR0 =
1091                 (REG_DDRPHY_CONFIG->SCHCR0 & 0xFFFFFFF0) |
1092                 0x00000001; // [3:0]SCHTRIGy
1093         }
1094     }
1095 
1096     REG_DDRPHY_CONFIG->PGSR0;
1097     dmb();
1098     usleep_en(500);
1099     REG_DDRPHY_CONFIG->PGSR1;
1100     dmb();
1101     usleep_en(500);
1102 
1103     return 0;
1104 }
1105 
ddr_init_mc1_mp(REG_ST_DMC520 * REG_DMC520)1106 int ddr_init_mc1_mp(REG_ST_DMC520 *REG_DMC520)
1107 {
1108     REG_DMC520->memc_status;
1109     REG_DMC520->memc_config;
1110 
1111     // POWERDOWN_ENTRY
1112     REG_DMC520->direct_addr = 0x00000006;
1113     REG_DMC520->direct_cmd = 0x000F0004;
1114     REG_DMC520->memc_status;
1115 
1116     // wait
1117     usleep_en(500);
1118 
1119     // INVALIDATE RESET
1120     REG_DMC520->direct_addr = 0x00000000;
1121     REG_DMC520->direct_cmd = 0x0001000B;
1122     REG_DMC520->memc_status;
1123 
1124     // wait
1125     usleep_en(500);
1126 
1127     // INVALIDATE RESET
1128     REG_DMC520->direct_addr = 0x00000001;
1129     REG_DMC520->direct_cmd = 0x000F000B;
1130     REG_DMC520->memc_status;
1131 
1132     // wait
1133     usleep_en(500);
1134 
1135     // WAIT
1136     REG_DMC520->direct_addr = 0x000003E8;
1137     REG_DMC520->direct_cmd = 0x0001000D;
1138     REG_DMC520->memc_status;
1139     REG_DMC520->direct_addr = 0x00000258;
1140     REG_DMC520->direct_cmd = 0x0001000D;
1141     REG_DMC520->memc_status;
1142 
1143     // INVALIDATE RESET
1144     REG_DMC520->direct_addr = 0x00010001;
1145     REG_DMC520->direct_cmd = 0x000F000B;
1146     REG_DMC520->memc_status;
1147 
1148     // wait
1149     usleep_en(500);
1150 
1151     // WAIT
1152     REG_DMC520->direct_addr = 0x0000003C;
1153     REG_DMC520->direct_cmd = 0x0001000D;
1154     REG_DMC520->memc_status;
1155 
1156     // NOP
1157     REG_DMC520->direct_addr = 0x00000000;
1158     REG_DMC520->direct_cmd = 0x000F0000;
1159     REG_DMC520->memc_status;
1160 
1161     return 0;
1162 }
1163 
ddr_init_train_mp(REG_ST_DDRPHY_CONFIG_t * REG_DDRPHY_CONFIG,int retention_en)1164 int ddr_init_train_mp(
1165     REG_ST_DDRPHY_CONFIG_t *REG_DDRPHY_CONFIG,
1166     int retention_en)
1167 {
1168     int status = 0;
1169     uint32_t phy_status_0;
1170     struct ddr_wait_cond wait_cond;
1171 
1172     REG_DDRPHY_CONFIG->PGSR0;
1173     REG_DDRPHY_CONFIG->PGSR1;
1174 
1175     /////////////////////////////////////////////////////////////////////
1176     //  1. Write Leveling, Gate Training, Write Leveling Adjust
1177     /////////////////////////////////////////////////////////////////////
1178     REG_DDRPHY_CONFIG->PGCR3 =
1179         (REG_DDRPHY_CONFIG->PGCR3 & 0xFFFFFFE7) | 0x00000000;
1180     dmb();
1181 
1182 #ifdef DDR_DQSTRAINWA_ON
1183     REG_DDRPHY_CONFIG->PIR = (REG_DDRPHY_CONFIG->PIR & 0xFFFFFDFE) | 0x00000201;
1184     dmb();
1185     Wait_for_ddr(1);
1186     dmb();
1187     // [0]IDONE, [5]WLDONE
1188     while (((REG_DDRPHY_CONFIG->PGSR0 & 0x00000021) != 0x00000021) &&
1189            ((REG_DDRPHY_CONFIG->PGSR0 & 0x4FF80000) == 0))
1190         ;
1191 
1192     REG_DDRPHY_CONFIG->DXCCR =
1193         (REG_DDRPHY_CONFIG->DXCCR & 0xFFBFFFFF) | 0x00000000;
1194     dmb();
1195 
1196     REG_DDRPHY_CONFIG->PIR = (REG_DDRPHY_CONFIG->PIR & 0xFFFFFBFE) | 0x00000401;
1197     dmb();
1198     Wait_for_ddr(1);
1199     dmb();
1200     // [0]IDONE, [6]QSGDONE
1201     while (((REG_DDRPHY_CONFIG->PGSR0 & 0x00000041) != 0x00000041) &&
1202            ((REG_DDRPHY_CONFIG->PGSR0 & 0x4FF80000) == 0))
1203         ;
1204 
1205     REG_DDRPHY_CONFIG->DXCCR =
1206         (REG_DDRPHY_CONFIG->DXCCR & 0xFFBFFFFF) | 0x00400000;
1207     dmb();
1208 
1209     REG_DDRPHY_CONFIG->PIR = (REG_DDRPHY_CONFIG->PIR & 0xFFFFF7FE) | 0x00000801;
1210     dmb();
1211     Wait_for_ddr(1);
1212     dmb();
1213     // [0]IDONE, [7]WLADONE
1214     while (((REG_DDRPHY_CONFIG->PGSR0 & 0x00000081) != 0x00000081) &&
1215            ((REG_DDRPHY_CONFIG->PGSR0 & 0x4FF80000) == 0))
1216         ;
1217 
1218 #else
1219     REG_DDRPHY_CONFIG->PIR = (REG_DDRPHY_CONFIG->PIR & 0xFFFFF1FE) | 0x00000E01;
1220     dmb();
1221     // Wait by completion of Data Training.
1222     Wait_for_ddr(1);
1223     dmb();
1224 
1225     // [0]IDONE, [5]WLDONE, [6]QSGDONE, [7]WLADONE
1226     wait_cond.type = DDR_DDRPHY_CONFIG_PGSR0_1;
1227     wait_cond.reg = REG_DDRPHY_CONFIG;
1228     wait_cond.mask = 0x000000E1;
1229     wait_cond.comp_val = 0x000000E1;
1230     synquacer_memc_timer_api->wait(
1231         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
1232         ddr_check_wait_cond, &wait_cond);
1233 
1234     if ((REG_DDRPHY_CONFIG->PGSR0 & 0x4FF80000) != 0) {
1235         FWK_LOG_CRIT(
1236             "[DDR] error : Write Leveling, Gate Training, Write Leveling "
1237             "Adjust");
1238         status = 0x3002;
1239         goto ERROR_END;
1240     }
1241 #endif
1242 
1243     /////////////////////////////////////////////////////////////////////
1244     //  2. Data Bit Deskew, Data Eye, Static Read
1245     /////////////////////////////////////////////////////////////////////
1246     REG_DDRPHY_CONFIG->PGCR0 =
1247         (REG_DDRPHY_CONFIG->PGCR0 & 0xFBFFFFFF) | 0x00000000;
1248     dmb();
1249     // Wait for more than 10cycle with reference to pclk.
1250     Wait_for_ddr(1);
1251 
1252     REG_DDRPHY_CONFIG->PGCR3 =
1253         (REG_DDRPHY_CONFIG->PGCR3 & 0xFFFFFFE7) | 0x00000008;
1254     dmb();
1255 
1256     // Wait for more than 10cycle with reference to pclk.
1257     Wait_for_ddr(1);
1258 
1259     REG_DDRPHY_CONFIG->PGCR0 =
1260         (REG_DDRPHY_CONFIG->PGCR0 & 0xFBFFFFFF) | 0x04000000;
1261     dmb();
1262 
1263     // Wait for more than 10cycle with reference to pclk.
1264     Wait_for_ddr(1);
1265 
1266     REG_DDRPHY_CONFIG->PIR = (REG_DDRPHY_CONFIG->PIR & 0xFFFE0FFE) | 0x0001F001;
1267     dmb();
1268 
1269     // Wait by completion of Data Training.
1270     Wait_for_ddr(1);
1271     // [0]IDONE, [8]RDDONE, [9]WDDONE, [10]REDONE, [11]WEDONE, [13]SRDDONE
1272     // [note] timeout : Data Bit Deskew, Data Eye, Static Read
1273     wait_cond.type = DDR_DDRPHY_CONFIG_PGSR0_1;
1274     wait_cond.reg = REG_DDRPHY_CONFIG;
1275     wait_cond.mask = 0x00002F01;
1276     wait_cond.comp_val = 0x00002F01;
1277     synquacer_memc_timer_api->wait(
1278         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
1279         ddr_check_wait_cond, &wait_cond);
1280 
1281     if ((REG_DDRPHY_CONFIG->PGSR0 & 0x4FF80000) != 0) {
1282         FWK_LOG_CRIT("[DDR] error : Data Bit Deskew, Data Eye, Static Read");
1283         status = 0x3004;
1284         goto ERROR_END;
1285     }
1286 
1287     /////////////////////////////////////////////////////////////////////
1288     //  3. VREF Training
1289     /////////////////////////////////////////////////////////////////////
1290     if (retention_en == 0) {
1291         REG_DDRPHY_CONFIG->DTCR0 =
1292             (REG_DDRPHY_CONFIG->DTCR0 & 0x0FFFFFFF) | 0x00000000;
1293         dmb();
1294 
1295         REG_DDRPHY_CONFIG->PIR =
1296             (REG_DDRPHY_CONFIG->PIR & 0xFFFDFFFE) | 0x00020001;
1297         dmb();
1298 
1299         // 76 Wait by completion of Data Training.
1300         Wait_for_ddr(20);
1301 
1302         // [14]VDONE
1303         wait_cond.type = DDR_DDRPHY_CONFIG_PGSR0_1;
1304         wait_cond.reg = REG_DDRPHY_CONFIG;
1305         wait_cond.mask = 0x00004001;
1306         wait_cond.comp_val = 0x00004001;
1307         synquacer_memc_timer_api->wait(
1308             FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
1309             ddr_check_wait_cond, &wait_cond);
1310 
1311         if ((REG_DDRPHY_CONFIG->PGSR0 & 0x4FF80000) != 0) {
1312             FWK_LOG_CRIT("[DDR] error : VREF Training");
1313             status = 0x3006;
1314             goto ERROR_END;
1315         }
1316 
1317         REG_DDRPHY_CONFIG->DTCR0 =
1318             (REG_DDRPHY_CONFIG->DTCR0 & 0x0FFFFFFF) | 0x80000000;
1319     }
1320 
1321 ERROR_END:
1322     /////////////////////////////////////////////////////////////////////
1323     //  Check Status
1324     /////////////////////////////////////////////////////////////////////
1325     phy_status_0 = REG_DDRPHY_CONFIG->PGSR0;
1326     if (((phy_status_0 >> 19) & 0x1) == 0x1) {
1327         FWK_LOG_CRIT("[DDR] %s VREF Training Error", __func__);
1328         status = 0x3010;
1329     }
1330     if (((phy_status_0 >> 20) & 0x1) == 0x1) {
1331         FWK_LOG_CRIT("[DDR] %s Impedance Calibration Error", __func__);
1332         status = 0x3011;
1333     }
1334     if (((phy_status_0 >> 21) & 0x1) == 0x1) {
1335         FWK_LOG_CRIT("[DDR] %s Write Leveling Error", __func__);
1336         status = 0x3012;
1337     }
1338     if (((phy_status_0 >> 22) & 0x1) == 0x1) {
1339         FWK_LOG_CRIT("[DDR] %s DQS Gate Training Error", __func__);
1340         status = 0x3013;
1341     }
1342     if (((phy_status_0 >> 23) & 0x1) == 0x1) {
1343         FWK_LOG_CRIT("[DDR] %s Write Leveling Adjustment Error", __func__);
1344         status = 0x3014;
1345     }
1346     if (((phy_status_0 >> 24) & 0x1) == 0x1) {
1347         FWK_LOG_CRIT("[DDR] %s Read Bit Deskew Error", __func__);
1348         status = 0x3015;
1349     }
1350     if (((phy_status_0 >> 25) & 0x1) == 0x1) {
1351         FWK_LOG_CRIT("[DDR] %s Write Bit Deskew Error", __func__);
1352         status = 0x3016;
1353     }
1354     if (((phy_status_0 >> 26) & 0x1) == 0x1) {
1355         FWK_LOG_CRIT("[DDR] %s Read Eye Training Error", __func__);
1356         status = 0x3017;
1357     }
1358     if (((phy_status_0 >> 27) & 0x1) == 0x1) {
1359         FWK_LOG_CRIT("[DDR] %s Write Eye Training Error", __func__);
1360         status = 0x3018;
1361     }
1362     if (((phy_status_0 >> 30) & 0x1) == 0x1) {
1363         FWK_LOG_CRIT("[DDR] %s Static Read Error", __func__);
1364         status = 0x3019;
1365     }
1366 
1367     if (status != 0)
1368         return status;
1369 
1370 #ifdef DDR_TRAINING_RESULT
1371     ddr_init_train_result(REG_DDRPHY_CONFIG);
1372 #endif // DDR_TRAINING_RESULT
1373 
1374     REG_DDRPHY_CONFIG->PGCR1 =
1375         (REG_DDRPHY_CONFIG->PGCR1 & 0xFFFFFFBF) | 0x00000000;
1376 
1377     REG_DDRPHY_CONFIG->PGSR0;
1378     REG_DDRPHY_CONFIG->PGSR1;
1379 
1380     return 0;
1381 }
1382 
ddr_init_mc2_mp(REG_ST_DMC520 * REG_DMC520)1383 int ddr_init_mc2_mp(REG_ST_DMC520 *REG_DMC520)
1384 {
1385     struct ddr_wait_cond wait_cond;
1386 
1387     REG_DMC520->memc_status;
1388     REG_DMC520->memc_config;
1389 
1390     if (!dram_ecc_is_enabled())
1391         REG_DMC520->feature_config &= 0xFFFFFFFC;
1392 
1393     // UPDATE
1394     REG_DMC520->direct_cmd = 0x0001000C;
1395 
1396     // ZQC
1397     REG_DMC520->direct_addr = 0x00000400;
1398     REG_DMC520->direct_cmd = 0x000F0005;
1399     dmb();
1400     REG_DMC520->memc_status;
1401 
1402     // Wait
1403     REG_DMC520->direct_addr = 0x000003ff;
1404     REG_DMC520->direct_cmd = 0x0001000d;
1405     dmb();
1406     REG_DMC520->memc_status;
1407 
1408     REG_DMC520->memc_status;
1409     REG_DMC520->memc_status;
1410     REG_DMC520->memc_status;
1411     REG_DMC520->memc_status;
1412     REG_DMC520->memc_cmd = 0x00000003;
1413     dmb();
1414     REG_DMC520->memc_status;
1415     REG_DMC520->memc_cmd = 0x00000004;
1416     dmb();
1417 
1418     wait_cond.type = DDR_DMC520_MEMC_STATUS;
1419     wait_cond.reg = REG_DMC520;
1420     wait_cond.mask = 0x7;
1421     wait_cond.comp_val = 0x3;
1422     synquacer_memc_timer_api->wait(
1423         FWK_ID_ELEMENT(FWK_MODULE_IDX_TIMER, 0), DDR_WAIT_TIMEOUT_US,
1424         ddr_check_wait_cond, &wait_cond);
1425 
1426     REG_DMC520->memc_status;
1427     REG_DMC520->memc_config;
1428 
1429     return 0;
1430 }
1431