1 /* 2 * Copyright 2018 The Hafnium Authors. 3 * 4 * Use of this source code is governed by a BSD-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/BSD-3-Clause. 7 */ 8 9 #ifndef __ASSEMBLER__ 10 11 #pragma once 12 13 #include <stddef.h> 14 15 #include "hf/arch/cpu.h" 16 17 /** 18 * Macros to stringify a parameter, and to allow the results of a macro to be 19 * stringified in turn. 20 */ 21 #define str_(s) #s 22 #define str(s) str_(s) 23 24 /** 25 * Reads a system register, supported by the current assembler, and returns the 26 * result. 27 */ 28 #define read_msr(name) \ 29 __extension__({ \ 30 uintreg_t __v; \ 31 __asm__ volatile("mrs %0, " str(name) : "=r"(__v)); \ 32 __v; \ 33 }) 34 35 /** 36 * Writes the value to the system register, supported by the current assembler. 37 */ 38 #define write_msr(name, value) \ 39 __extension__({ \ 40 __asm__ volatile("msr " str(name) ", %x0" \ 41 : \ 42 : "rZ"((uintreg_t)(value))); \ 43 }) 44 45 #endif /* __ASSEMBLER__ */ 46 47 /* 48 * Encodings for registers supported after Armv8.0. 49 * We aim to build one binary that supports a variety of platforms, therefore, 50 * use encodings in Arm Architecture Reference Manual Armv8-a, D13.2 for 51 * registers supported after Armv8.0. 52 */ 53 54 /* 55 * Registers supported from Armv8.1 onwards. 56 */ 57 58 /* 59 * Registers for feature Armv8.1-LOR (Limited Ordering Regions). 60 */ 61 62 /** 63 * Encoding for the LORegion Control register (LORC_EL1). 64 * This register enables and disables LORegions (Armv8.1). 65 */ 66 #define MSR_LORC_EL1 S3_0_C10_C4_3 67 68 /* 69 * Registers supported from Armv8.4 onwards. 70 */ 71 72 /* 73 * VSTTBR_EL2, Virtualization Secure Translation Table Base Register 74 */ 75 #define MSR_VSTTBR_EL2 S3_4_C2_C6_0 76 77 /* 78 * VSTCR_EL2, Virtualization Secure Translation Control Register 79 */ 80 #define MSR_VSTCR_EL2 S3_4_C2_C6_2 81 82 /* 83 * SVE Control Register for EL2. 84 */ 85 #define MSR_ZCR_EL2 S3_4_C1_C2_0 86 87 #if BRANCH_PROTECTION 88 89 #define APIAKEYLO_EL1 S3_0_C2_C1_0 90 #define APIAKEYHI_EL1 S3_0_C2_C1_1 91 #define APIBKEYLO_EL1 S3_0_C2_C1_2 92 #define APIBKEYHI_EL1 S3_0_C2_C1_3 93 #define APDAKEYLO_EL1 S3_0_C2_C2_0 94 #define APDAKEYHI_EL1 S3_0_C2_C2_1 95 #define APDBKEYLO_EL1 S3_0_C2_C2_2 96 #define APDBKEYHI_EL1 S3_0_C2_C2_3 97 #define APGAKEYLO_EL1 S3_0_C2_C3_0 98 #define APGAKEYHI_EL1 S3_0_C2_C3_1 99 100 #endif 101 102 #if ENABLE_VHE 103 /* 104 * EL1 register encodings when ARMv8.1 VHE is enabled, as defined in table 105 * D5-47 of the ARMv8 ARM (DDI0487F). 106 */ 107 #define MSR_SCTLR_EL12 S3_5_C1_C0_0 108 #define MSR_CPACR_EL12 S3_5_C1_C0_2 109 #define MSR_ZCR_EL12 S3_5_C1_C2_0 110 #define MSR_TRFCR_EL12 S3_5_C1_C2_1 111 #define MSR_TTBR0_EL12 S3_5_C2_C0_0 112 #define MSR_TTBR1_EL12 S3_5_C2_C0_1 113 #define MSR_TCR_EL12 S3_5_C2_C0_2 114 #define MSR_AFSR0_EL12 S3_5_C5_C1_0 115 #define MSR_AFSR1_EL12 S3_5_C5_C1_1 116 #define MSR_ESR_EL12 S3_5_C5_C2_0 117 #define MSR_FAR_EL12 S3_5_C6_C0_0 118 #define MSR_PMSCR_EL12 S3_5_C9_C9_0 119 #define MSR_MAIR_EL12 S3_5_C10_C2_0 120 #define MSR_AMAIR_EL12 S3_5_C10_C3_0 121 #define MSR_VBAR_EL12 S3_5_C12_C0_0 122 #define MSR_CONTEXTIDR_EL12 S3_5_C13_C0_1 123 #define MSR_CNTKCTL_EL12 S3_5_C14_C1_0 124 #define MSR_CNTP_TVAL_EL02 S3_5_C14_C2_0 125 #define MSR_CNTP_CTL_EL02 S3_5_C14_C2_1 126 #define MSR_CNTP_CVAL_EL02 S3_5_C14_C2_2 127 #define MSR_CNTV_TVAL_EL02 S3_5_C14_C3_0 128 #define MSR_CNTV_CTL_EL02 S3_5_C14_C3_1 129 #define MSR_CNTV_CVAL_EL02 S3_5_C14_C3_2 130 #define MSR_SPSR_EL12 S3_5_C4_C0_0 131 #define MSR_ELR_EL12 S3_5_C4_C0_1 132 133 #endif 134