1Marvell Armada AP80x System Controller
2======================================
3
4The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
57K/8K/931x SoCs. It contains system controllers, which provide several
6registers giving access to numerous features: clocks, pin-muxing and
7many other SoC configuration items. This DT binding allows to describe
8these system controllers.
9
10For the top level node:
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
13
14SYSTEM CONTROLLER 0
15===================
16
17Clocks:
18-------
19
20
21The Device Tree node representing the AP806/AP807 system controller
22provides a number of clocks:
23
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
28
29Required properties:
30
31 - compatible: must be one of:
32   * "marvell,ap806-clock"
33   * "marvell,ap807-clock"
34 - #clock-cells: must be set to 1
35
36Pinctrl:
37--------
38
39For common binding part and usage, refer to
40Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
41
42Required properties:
43- compatible must be "marvell,ap806-pinctrl",
44
45Available mpp pins/groups and functions:
46Note: brackets (x) are not part of the mpp name for marvell,function and given
47only for more detailed description in this document.
48
49name	pins	functions
50================================================================================
51mpp0	0	gpio, sdio(clk), spi0(clk)
52mpp1	1	gpio, sdio(cmd), spi0(miso)
53mpp2	2	gpio, sdio(d0), spi0(mosi)
54mpp3	3	gpio, sdio(d1), spi0(cs0n)
55mpp4	4	gpio, sdio(d2), i2c0(sda)
56mpp5	5	gpio, sdio(d3), i2c0(sdk)
57mpp6	6	gpio, sdio(ds)
58mpp7	7	gpio, sdio(d4), uart1(rxd)
59mpp8	8	gpio, sdio(d5), uart1(txd)
60mpp9	9	gpio, sdio(d6), spi0(cs1n)
61mpp10	10	gpio, sdio(d7)
62mpp11	11	gpio, uart0(txd)
63mpp12	12	gpio, sdio(pw_off), sdio(hw_rst)
64mpp13	13	gpio
65mpp14	14	gpio
66mpp15	15	gpio
67mpp16	16	gpio
68mpp17	17	gpio
69mpp18	18	gpio
70mpp19	19	gpio, uart0(rxd), sdio(pw_off)
71
72GPIO:
73-----
74For common binding part and usage, refer to
75Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
76
77Required properties:
78
79- compatible: "marvell,armada-8k-gpio"
80
81- offset: offset address inside the syscon block
82
83Optional properties:
84
85- marvell,pwm-offset: offset address of PWM duration control registers inside
86  the syscon block
87
88Example:
89ap_syscon: system-controller@6f4000 {
90	compatible = "syscon", "simple-mfd";
91	reg = <0x6f4000 0x1000>;
92
93	ap_clk: clock {
94		compatible = "marvell,ap806-clock";
95		#clock-cells = <1>;
96	};
97
98	ap_pinctrl: pinctrl {
99		compatible = "marvell,ap806-pinctrl";
100	};
101
102	ap_gpio: gpio {
103		compatible = "marvell,armada-8k-gpio";
104		offset = <0x1040>;
105		ngpios = <19>;
106		gpio-controller;
107		#gpio-cells = <2>;
108		gpio-ranges = <&ap_pinctrl 0 0 19>;
109		marvell,pwm-offset = <0x10c0>;
110		#pwm-cells = <2>;
111		clocks = <&ap_clk 3>;
112	};
113};
114
115SYSTEM CONTROLLER 1
116===================
117
118Thermal:
119--------
120
121For common binding part and usage, refer to
122Documentation/devicetree/bindings/thermal/thermal*.yaml
123
124The thermal IP can probe the temperature all around the processor. It
125may feature several channels, each of them wired to one sensor.
126
127It is possible to setup an overheat interrupt by giving at least one
128critical point to any subnode of the thermal-zone node.
129
130Required properties:
131- compatible: must be one of:
132  * marvell,armada-ap806-thermal
133- reg: register range associated with the thermal functions.
134
135Optional properties:
136- interrupts: overheat interrupt handle. Should point to line 18 of the
137  SEI irqchip. See interrupt-controller/interrupts.txt
138- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
139  to this IP and represents the channel ID. There is one sensor per
140  channel. O refers to the thermal IP internal channel, while positive
141  IDs refer to each CPU.
142
143Example:
144ap_syscon1: system-controller@6f8000 {
145	compatible = "syscon", "simple-mfd";
146	reg = <0x6f8000 0x1000>;
147
148	ap_thermal: thermal-sensor@80 {
149		compatible = "marvell,armada-ap806-thermal";
150		reg = <0x80 0x10>;
151		interrupt-parent = <&sei>;
152		interrupts = <18>;
153		#thermal-sensor-cells = <1>;
154	};
155};
156
157Cluster clocks:
158---------------
159
160Device Tree Clock bindings for cluster clock of Marvell
161AP806/AP807. Each cluster contain up to 2 CPUs running at the same
162frequency.
163
164Required properties:
165 - compatible: must be one of:
166   * "marvell,ap806-cpu-clock"
167   * "marvell,ap807-cpu-clock"
168- #clock-cells : should be set to 1.
169
170- clocks : shall be the input parent clock(s) phandle for the clock
171           (one per cluster)
172
173- reg: register range associated with the cluster clocks
174
175ap_syscon1: system-controller@6f8000 {
176	compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
177	reg = <0x6f8000 0x1000>;
178
179	cpu_clk: clock-cpu@278 {
180		compatible = "marvell,ap806-cpu-clock";
181		clocks = <&ap_clk 0>, <&ap_clk 1>;
182		#clock-cells = <1>;
183		reg = <0x278 0xa30>;
184	};
185};
186