1 /********************************************************************* 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 ********************************************************************** 5 * * 6 * (c) 1995 - 2021 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: support@segger.com * 9 * * 10 ********************************************************************** 11 * * 12 * SEGGER SystemView * Real-time application analysis * 13 * * 14 ********************************************************************** 15 * * 16 * All rights reserved. * 17 * * 18 * SEGGER strongly recommends to not make any changes * 19 * to or modify the source code of this software in order to stay * 20 * compatible with the SystemView and RTT protocol, and J-Link. * 21 * * 22 * Redistribution and use in source and binary forms, with or * 23 * without modification, are permitted provided that the following * 24 * condition is met: * 25 * * 26 * o Redistributions of source code must retain the above copyright * 27 * notice, this condition and the following disclaimer. * 28 * * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 30 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 31 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 33 * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * 34 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 36 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 38 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 40 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 41 * DAMAGE. * 42 * * 43 ********************************************************************** 44 * * 45 * SystemView version: 3.30 * 46 * * 47 ********************************************************************** 48 ---------------------------END-OF-HEADER------------------------------ 49 File : SEGGER_RTT_Conf.h 50 Purpose : Implementation of SEGGER real-time transfer (RTT) which 51 allows real-time communication on targets which support 52 debugger memory accesses while the CPU is running. 53 Revision: $Rev: 21386 $ 54 55 */ 56 57 #ifndef SEGGER_RTT_CONF_H 58 #define SEGGER_RTT_CONF_H 59 60 #ifdef __IAR_SYSTEMS_ICC__ 61 #include <intrinsics.h> 62 #endif 63 64 /********************************************************************* 65 * 66 * Defines, configurable 67 * 68 ********************************************************************** 69 */ 70 71 // 72 // Take in and set to correct values for Cortex-A systems with CPU cache 73 // 74 //#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system 75 //#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached 76 // 77 // Most common case: 78 // Up-channel 0: RTT 79 // Up-channel 1: SystemView 80 // 81 #ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS 82 #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) 83 #endif 84 // 85 // Most common case: 86 // Down-channel 0: RTT 87 // Down-channel 1: SystemView 88 // 89 #ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 90 #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) 91 #endif 92 93 #ifndef BUFFER_SIZE_UP 94 #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) 95 #endif 96 97 #ifndef BUFFER_SIZE_DOWN 98 #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) 99 #endif 100 101 #ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE 102 #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) 103 #endif 104 105 #ifndef SEGGER_RTT_MODE_DEFAULT 106 #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) 107 #endif 108 109 /********************************************************************* 110 * 111 * RTT memcpy configuration 112 * 113 * memcpy() is good for large amounts of data, 114 * but the overhead is big for small amounts, which are usually stored via RTT. 115 * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. 116 * 117 * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. 118 * This is may be required with memory access restrictions, 119 * such as on Cortex-A devices with MMU. 120 */ 121 #ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP 122 #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop 123 #endif 124 // 125 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets 126 // 127 //#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) 128 // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) 129 //#endif 130 131 // 132 // Target is not allowed to perform other RTT operations while string still has not been stored completely. 133 // Otherwise we would probably end up with a mixed string in the buffer. 134 // If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. 135 // 136 // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. 137 // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. 138 // When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. 139 // (Higher priority = lower priority number) 140 // Default value for embOS: 128u 141 // Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) 142 // In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC 143 // or define SEGGER_RTT_LOCK() to completely disable interrupts. 144 // 145 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 146 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) 147 #endif 148 149 /********************************************************************* 150 * 151 * RTT lock configuration for SEGGER Embedded Studio, 152 * Rowley CrossStudio and GCC 153 */ 154 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) 155 #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) 156 #define SEGGER_RTT_LOCK() { \ 157 unsigned int _SEGGER_RTT__LockState; \ 158 __asm volatile ("mrs %0, primask \n\t" \ 159 "movs r1, #1 \n\t" \ 160 "msr primask, r1 \n\t" \ 161 : "=r" (_SEGGER_RTT__LockState) \ 162 : \ 163 : "r1", "cc" \ 164 ); 165 166 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ 167 : \ 168 : "r" (_SEGGER_RTT__LockState) \ 169 : \ 170 ); \ 171 } 172 #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) 173 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 174 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 175 #endif 176 #define SEGGER_RTT_LOCK() { \ 177 unsigned int _SEGGER_RTT__LockState; \ 178 __asm volatile ("mrs %0, basepri \n\t" \ 179 "mov r1, %1 \n\t" \ 180 "msr basepri, r1 \n\t" \ 181 : "=r" (_SEGGER_RTT__LockState) \ 182 : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ 183 : "r1", "cc" \ 184 ); 185 186 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ 187 : \ 188 : "r" (_SEGGER_RTT__LockState) \ 189 : \ 190 ); \ 191 } 192 193 #elif defined(__ARM_ARCH_7A__) 194 #define SEGGER_RTT_LOCK() { \ 195 unsigned int _SEGGER_RTT__LockState; \ 196 __asm volatile ("mrs r1, CPSR \n\t" \ 197 "mov %0, r1 \n\t" \ 198 "orr r1, r1, #0xC0 \n\t" \ 199 "msr CPSR_c, r1 \n\t" \ 200 : "=r" (_SEGGER_RTT__LockState) \ 201 : \ 202 : "r1", "cc" \ 203 ); 204 205 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 206 "mrs r1, CPSR \n\t" \ 207 "bic r1, r1, #0xC0 \n\t" \ 208 "and r0, r0, #0xC0 \n\t" \ 209 "orr r1, r1, r0 \n\t" \ 210 "msr CPSR_c, r1 \n\t" \ 211 : \ 212 : "r" (_SEGGER_RTT__LockState) \ 213 : "r0", "r1", "cc" \ 214 ); \ 215 } 216 #elif defined(__riscv) || defined(__riscv_xlen) 217 #define SEGGER_RTT_LOCK() { \ 218 unsigned int _SEGGER_RTT__LockState; \ 219 __asm volatile ("csrr %0, mstatus \n\t" \ 220 "csrci mstatus, 8 \n\t" \ 221 "andi %0, %0, 8 \n\t" \ 222 : "=r" (_SEGGER_RTT__LockState) \ 223 : \ 224 : \ 225 ); 226 227 #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ 228 "or %0, %0, a1 \n\t" \ 229 "csrs mstatus, %0 \n\t" \ 230 : \ 231 : "r" (_SEGGER_RTT__LockState) \ 232 : "a1" \ 233 ); \ 234 } 235 #else 236 #define SEGGER_RTT_LOCK() 237 #define SEGGER_RTT_UNLOCK() 238 #endif 239 #endif 240 241 /********************************************************************* 242 * 243 * RTT lock configuration for IAR EWARM 244 */ 245 #ifdef __ICCARM__ 246 #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ 247 (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) 248 #define SEGGER_RTT_LOCK() { \ 249 unsigned int _SEGGER_RTT__LockState; \ 250 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 251 __set_PRIMASK(1); 252 253 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 254 } 255 #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ 256 (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ 257 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ 258 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) 259 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 260 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 261 #endif 262 #define SEGGER_RTT_LOCK() { \ 263 unsigned int _SEGGER_RTT__LockState; \ 264 _SEGGER_RTT__LockState = __get_BASEPRI(); \ 265 __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 266 267 #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ 268 } 269 #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ 270 (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) 271 #define SEGGER_RTT_LOCK() { \ 272 unsigned int _SEGGER_RTT__LockState; \ 273 __asm volatile ("mrs r1, CPSR \n\t" \ 274 "mov %0, r1 \n\t" \ 275 "orr r1, r1, #0xC0 \n\t" \ 276 "msr CPSR_c, r1 \n\t" \ 277 : "=r" (_SEGGER_RTT__LockState) \ 278 : \ 279 : "r1", "cc" \ 280 ); 281 282 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 283 "mrs r1, CPSR \n\t" \ 284 "bic r1, r1, #0xC0 \n\t" \ 285 "and r0, r0, #0xC0 \n\t" \ 286 "orr r1, r1, r0 \n\t" \ 287 "msr CPSR_c, r1 \n\t" \ 288 : \ 289 : "r" (_SEGGER_RTT__LockState) \ 290 : "r0", "r1", "cc" \ 291 ); \ 292 } 293 #endif 294 #endif 295 296 /********************************************************************* 297 * 298 * RTT lock configuration for IAR RX 299 */ 300 #ifdef __ICCRX__ 301 #define SEGGER_RTT_LOCK() { \ 302 unsigned long _SEGGER_RTT__LockState; \ 303 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 304 __disable_interrupt(); 305 306 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 307 } 308 #endif 309 310 /********************************************************************* 311 * 312 * RTT lock configuration for IAR RL78 313 */ 314 #ifdef __ICCRL78__ 315 #define SEGGER_RTT_LOCK() { \ 316 __istate_t _SEGGER_RTT__LockState; \ 317 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 318 __disable_interrupt(); 319 320 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 321 } 322 #endif 323 324 /********************************************************************* 325 * 326 * RTT lock configuration for KEIL ARM 327 */ 328 #ifdef __CC_ARM 329 #if (defined __TARGET_ARCH_6S_M) 330 #define SEGGER_RTT_LOCK() { \ 331 unsigned int _SEGGER_RTT__LockState; \ 332 register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ 333 _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ 334 _SEGGER_RTT__PRIMASK = 1u; \ 335 __schedule_barrier(); 336 337 #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ 338 __schedule_barrier(); \ 339 } 340 #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) 341 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 342 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 343 #endif 344 #define SEGGER_RTT_LOCK() { \ 345 unsigned int _SEGGER_RTT__LockState; \ 346 register unsigned char BASEPRI __asm( "basepri"); \ 347 _SEGGER_RTT__LockState = BASEPRI; \ 348 BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ 349 __schedule_barrier(); 350 351 #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ 352 __schedule_barrier(); \ 353 } 354 #endif 355 #endif 356 357 /********************************************************************* 358 * 359 * RTT lock configuration for TI ARM 360 */ 361 #ifdef __TI_ARM__ 362 #if defined (__TI_ARM_V6M0__) 363 #define SEGGER_RTT_LOCK() { \ 364 unsigned int _SEGGER_RTT__LockState; \ 365 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 366 __set_PRIMASK(1); 367 368 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 369 } 370 #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) 371 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 372 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 373 #endif 374 #define SEGGER_RTT_LOCK() { \ 375 unsigned int _SEGGER_RTT__LockState; \ 376 _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 377 378 #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ 379 } 380 #endif 381 #endif 382 383 /********************************************************************* 384 * 385 * RTT lock configuration for CCRX 386 */ 387 #ifdef __RX 388 #include <machine.h> 389 #define SEGGER_RTT_LOCK() { \ 390 unsigned long _SEGGER_RTT__LockState; \ 391 _SEGGER_RTT__LockState = get_psw() & 0x010000; \ 392 clrpsw_i(); 393 394 #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ 395 } 396 #endif 397 398 /********************************************************************* 399 * 400 * RTT lock configuration for embOS Simulation on Windows 401 * (Can also be used for generic RTT locking with embOS) 402 */ 403 #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) 404 405 void OS_SIM_EnterCriticalSection(void); 406 void OS_SIM_LeaveCriticalSection(void); 407 408 #define SEGGER_RTT_LOCK() { \ 409 OS_SIM_EnterCriticalSection(); 410 411 #define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ 412 } 413 #endif 414 415 /********************************************************************* 416 * 417 * RTT lock configuration fallback 418 */ 419 #ifndef SEGGER_RTT_LOCK 420 #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) 421 #endif 422 423 #ifndef SEGGER_RTT_UNLOCK 424 #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) 425 #endif 426 427 #endif 428 /*************************** End of file ****************************/ 429