1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifndef __AMDGPU_GFX_H__
25 #define __AMDGPU_GFX_H__
26
27 /*
28 * GFX stuff
29 */
30 #include "clearstate_defs.h"
31 #include "amdgpu_ring.h"
32 #include "amdgpu_rlc.h"
33 #include "amdgpu_imu.h"
34 #include "soc15.h"
35 #include "amdgpu_ras.h"
36 #include "amdgpu_ring_mux.h"
37
38 /* GFX current status */
39 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
40 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
41 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
42 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
43 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
44
45 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
46 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
47
48 enum amdgpu_gfx_pipe_priority {
49 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
50 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
51 };
52
53 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
54 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
55
56 struct amdgpu_mec {
57 struct amdgpu_bo *hpd_eop_obj;
58 u64 hpd_eop_gpu_addr;
59 struct amdgpu_bo *mec_fw_obj;
60 u64 mec_fw_gpu_addr;
61 struct amdgpu_bo *mec_fw_data_obj;
62 u64 mec_fw_data_gpu_addr;
63
64 u32 num_mec;
65 u32 num_pipe_per_mec;
66 u32 num_queue_per_pipe;
67 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
68
69 /* These are the resources for which amdgpu takes ownership */
70 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
71 };
72
73 enum amdgpu_unmap_queues_action {
74 PREEMPT_QUEUES = 0,
75 RESET_QUEUES,
76 DISABLE_PROCESS_QUEUES,
77 PREEMPT_QUEUES_NO_UNMAP,
78 };
79
80 struct kiq_pm4_funcs {
81 /* Support ASIC-specific kiq pm4 packets*/
82 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
83 uint64_t queue_mask);
84 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
85 struct amdgpu_ring *ring);
86 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
87 struct amdgpu_ring *ring,
88 enum amdgpu_unmap_queues_action action,
89 u64 gpu_addr, u64 seq);
90 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
91 struct amdgpu_ring *ring,
92 u64 addr,
93 u64 seq);
94 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
95 uint16_t pasid, uint32_t flush_type,
96 bool all_hub);
97 /* Packet sizes */
98 int set_resources_size;
99 int map_queues_size;
100 int unmap_queues_size;
101 int query_status_size;
102 int invalidate_tlbs_size;
103 };
104
105 struct amdgpu_kiq {
106 u64 eop_gpu_addr;
107 struct amdgpu_bo *eop_obj;
108 spinlock_t ring_lock;
109 struct amdgpu_ring ring;
110 struct amdgpu_irq_src irq;
111 const struct kiq_pm4_funcs *pmf;
112 };
113
114 /*
115 * GFX configurations
116 */
117 #define AMDGPU_GFX_MAX_SE 4
118 #define AMDGPU_GFX_MAX_SH_PER_SE 2
119
120 struct amdgpu_rb_config {
121 uint32_t rb_backend_disable;
122 uint32_t user_rb_backend_disable;
123 uint32_t raster_config;
124 uint32_t raster_config_1;
125 };
126
127 struct gb_addr_config {
128 uint16_t pipe_interleave_size;
129 uint8_t num_pipes;
130 uint8_t max_compress_frags;
131 uint8_t num_banks;
132 uint8_t num_se;
133 uint8_t num_rb_per_se;
134 uint8_t num_pkrs;
135 };
136
137 struct amdgpu_gfx_config {
138 unsigned max_shader_engines;
139 unsigned max_tile_pipes;
140 unsigned max_cu_per_sh;
141 unsigned max_sh_per_se;
142 unsigned max_backends_per_se;
143 unsigned max_texture_channel_caches;
144 unsigned max_gprs;
145 unsigned max_gs_threads;
146 unsigned max_hw_contexts;
147 unsigned sc_prim_fifo_size_frontend;
148 unsigned sc_prim_fifo_size_backend;
149 unsigned sc_hiz_tile_fifo_size;
150 unsigned sc_earlyz_tile_fifo_size;
151
152 unsigned num_tile_pipes;
153 unsigned backend_enable_mask;
154 unsigned mem_max_burst_length_bytes;
155 unsigned mem_row_size_in_kb;
156 unsigned shader_engine_tile_size;
157 unsigned num_gpus;
158 unsigned multi_gpu_tile_size;
159 unsigned mc_arb_ramcfg;
160 unsigned num_banks;
161 unsigned num_ranks;
162 unsigned gb_addr_config;
163 unsigned num_rbs;
164 unsigned gs_vgt_table_depth;
165 unsigned gs_prim_buffer_depth;
166
167 uint32_t tile_mode_array[32];
168 uint32_t macrotile_mode_array[16];
169
170 struct gb_addr_config gb_addr_config_fields;
171 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
172
173 /* gfx configure feature */
174 uint32_t double_offchip_lds_buf;
175 /* cached value of DB_DEBUG2 */
176 uint32_t db_debug2;
177 /* gfx10 specific config */
178 uint32_t num_sc_per_sh;
179 uint32_t num_packer_per_sc;
180 uint32_t pa_sc_tile_steering_override;
181 /* Whether texture coordinate truncation is conformant. */
182 bool ta_cntl2_truncate_coord_mode;
183 uint64_t tcc_disabled_mask;
184 uint32_t gc_num_tcp_per_sa;
185 uint32_t gc_num_sdp_interface;
186 uint32_t gc_num_tcps;
187 uint32_t gc_num_tcp_per_wpg;
188 uint32_t gc_tcp_l1_size;
189 uint32_t gc_num_sqc_per_wgp;
190 uint32_t gc_l1_instruction_cache_size_per_sqc;
191 uint32_t gc_l1_data_cache_size_per_sqc;
192 uint32_t gc_gl1c_per_sa;
193 uint32_t gc_gl1c_size_per_instance;
194 uint32_t gc_gl2c_per_gpu;
195 };
196
197 struct amdgpu_cu_info {
198 uint32_t simd_per_cu;
199 uint32_t max_waves_per_simd;
200 uint32_t wave_front_size;
201 uint32_t max_scratch_slots_per_cu;
202 uint32_t lds_size;
203
204 /* total active CU number */
205 uint32_t number;
206 uint32_t ao_cu_mask;
207 uint32_t ao_cu_bitmap[4][4];
208 uint32_t bitmap[4][4];
209 };
210
211 struct amdgpu_gfx_ras {
212 struct amdgpu_ras_block_object ras_block;
213 void (*enable_watchdog_timer)(struct amdgpu_device *adev);
214 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
215 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,
216 struct amdgpu_irq_src *source,
217 struct amdgpu_iv_entry *entry);
218 int (*poison_consumption_handler)(struct amdgpu_device *adev,
219 struct amdgpu_iv_entry *entry);
220 };
221
222 struct amdgpu_gfx_funcs {
223 /* get the gpu clock counter */
224 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
225 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
226 u32 sh_num, u32 instance);
227 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
228 uint32_t wave, uint32_t *dst, int *no_fields);
229 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
230 uint32_t wave, uint32_t thread, uint32_t start,
231 uint32_t size, uint32_t *dst);
232 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
233 uint32_t wave, uint32_t start, uint32_t size,
234 uint32_t *dst);
235 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
236 u32 queue, u32 vmid);
237 void (*init_spm_golden)(struct amdgpu_device *adev);
238 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
239 };
240
241 struct sq_work {
242 struct work_struct work;
243 unsigned ih_data;
244 };
245
246 struct amdgpu_pfp {
247 struct amdgpu_bo *pfp_fw_obj;
248 uint64_t pfp_fw_gpu_addr;
249 uint32_t *pfp_fw_ptr;
250
251 struct amdgpu_bo *pfp_fw_data_obj;
252 uint64_t pfp_fw_data_gpu_addr;
253 uint32_t *pfp_fw_data_ptr;
254 };
255
256 struct amdgpu_ce {
257 struct amdgpu_bo *ce_fw_obj;
258 uint64_t ce_fw_gpu_addr;
259 uint32_t *ce_fw_ptr;
260 };
261
262 struct amdgpu_me {
263 struct amdgpu_bo *me_fw_obj;
264 uint64_t me_fw_gpu_addr;
265 uint32_t *me_fw_ptr;
266
267 struct amdgpu_bo *me_fw_data_obj;
268 uint64_t me_fw_data_gpu_addr;
269 uint32_t *me_fw_data_ptr;
270
271 uint32_t num_me;
272 uint32_t num_pipe_per_me;
273 uint32_t num_queue_per_pipe;
274 void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
275
276 /* These are the resources for which amdgpu takes ownership */
277 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
278 };
279
280 struct amdgpu_gfx {
281 struct mutex gpu_clock_mutex;
282 struct amdgpu_gfx_config config;
283 struct amdgpu_rlc rlc;
284 struct amdgpu_pfp pfp;
285 struct amdgpu_ce ce;
286 struct amdgpu_me me;
287 struct amdgpu_mec mec;
288 struct amdgpu_kiq kiq;
289 struct amdgpu_imu imu;
290 bool rs64_enable; /* firmware format */
291 const struct firmware *me_fw; /* ME firmware */
292 uint32_t me_fw_version;
293 const struct firmware *pfp_fw; /* PFP firmware */
294 uint32_t pfp_fw_version;
295 const struct firmware *ce_fw; /* CE firmware */
296 uint32_t ce_fw_version;
297 const struct firmware *rlc_fw; /* RLC firmware */
298 uint32_t rlc_fw_version;
299 const struct firmware *mec_fw; /* MEC firmware */
300 uint32_t mec_fw_version;
301 const struct firmware *mec2_fw; /* MEC2 firmware */
302 uint32_t mec2_fw_version;
303 const struct firmware *imu_fw; /* IMU firmware */
304 uint32_t imu_fw_version;
305 uint32_t me_feature_version;
306 uint32_t ce_feature_version;
307 uint32_t pfp_feature_version;
308 uint32_t rlc_feature_version;
309 uint32_t rlc_srlc_fw_version;
310 uint32_t rlc_srlc_feature_version;
311 uint32_t rlc_srlg_fw_version;
312 uint32_t rlc_srlg_feature_version;
313 uint32_t rlc_srls_fw_version;
314 uint32_t rlc_srls_feature_version;
315 uint32_t rlcp_ucode_version;
316 uint32_t rlcp_ucode_feature_version;
317 uint32_t rlcv_ucode_version;
318 uint32_t rlcv_ucode_feature_version;
319 uint32_t mec_feature_version;
320 uint32_t mec2_feature_version;
321 bool mec_fw_write_wait;
322 bool me_fw_write_wait;
323 bool cp_fw_write_wait;
324 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
325 unsigned num_gfx_rings;
326 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
327 unsigned num_compute_rings;
328 struct amdgpu_irq_src eop_irq;
329 struct amdgpu_irq_src priv_reg_irq;
330 struct amdgpu_irq_src priv_inst_irq;
331 struct amdgpu_irq_src cp_ecc_error_irq;
332 struct amdgpu_irq_src sq_irq;
333 struct amdgpu_irq_src rlc_gc_fed_irq;
334 struct sq_work sq_work;
335
336 /* gfx status */
337 uint32_t gfx_current_status;
338 /* ce ram size*/
339 unsigned ce_ram_size;
340 struct amdgpu_cu_info cu_info;
341 const struct amdgpu_gfx_funcs *funcs;
342
343 /* reset mask */
344 uint32_t grbm_soft_reset;
345 uint32_t srbm_soft_reset;
346
347 /* gfx off */
348 bool gfx_off_state; /* true: enabled, false: disabled */
349 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */
350 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
351 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
352 uint32_t gfx_off_residency; /* last logged residency */
353 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
354
355 /* pipe reservation */
356 struct mutex pipe_reserve_mutex;
357 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
358
359 /*ras */
360 struct ras_common_if *ras_if;
361 struct amdgpu_gfx_ras *ras;
362
363 bool is_poweron;
364
365 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
366 struct amdgpu_ring_mux muxer;
367 };
368
369 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
370 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
371 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
372 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
373
374 /**
375 * amdgpu_gfx_create_bitmask - create a bitmask
376 *
377 * @bit_width: length of the mask
378 *
379 * create a variable length bit mask.
380 * Returns the bitmask.
381 */
amdgpu_gfx_create_bitmask(u32 bit_width)382 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
383 {
384 return (u32)((1ULL << bit_width) - 1);
385 }
386
387 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
388 unsigned max_sh);
389
390 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
391 struct amdgpu_ring *ring,
392 struct amdgpu_irq_src *irq);
393
394 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
395
396 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
397 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
398 unsigned hpd_size);
399
400 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
401 unsigned mqd_size);
402 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
403 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
404 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
405
406 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
407 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
408
409 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
410 int pipe, int queue);
411 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
412 int *mec, int *pipe, int *queue);
413 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
414 int pipe, int queue);
415 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
416 struct amdgpu_ring *ring);
417 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
418 struct amdgpu_ring *ring);
419 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
420 int pipe, int queue);
421 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
422 int *me, int *pipe, int *queue);
423 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
424 int pipe, int queue);
425 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
426 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
427 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
428 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
429 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
430 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
431 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
432 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
433 void *err_data,
434 struct amdgpu_iv_entry *entry);
435 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
436 struct amdgpu_irq_src *source,
437 struct amdgpu_iv_entry *entry);
438 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
439 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
440 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
441 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
442
443 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev);
444 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
445 struct amdgpu_iv_entry *entry);
446 #endif
447