1 /* 2 * Routines to access hardware 3 * 4 * Copyright (c) 2013 Realtek Semiconductor Corp. 5 * 6 * This module is a confidential and proprietary property of RealTek and 7 * possession or use of this module requires written permission of RealTek. 8 */ 9 10 #ifndef _RTL8195A_OTG_H_ 11 #define _RTL8195A_OTG_H_ 12 13 #define OTG_FAST_INIT 1 14 #define DWC_EN_ISOC 1 15 //#define DWC_EN_ISOC 0 16 #if defined(DWC_EN_ISOC) 17 #define USB_REQ_ISO_ASAP 1 18 #endif 19 20 #if defined(DWC_DEVICE_ONLY) 21 //#define USB_DEV_FULL_SPEED 22 #endif 23 24 #define DWC_RM_DEV_RDNT_SRC 25 #define DWC_RM_HOST_RDNT_SRC 26 #define HAL_OTG_READ32(addr) HAL_READ32(USB_OTG_REG_BASE, (u32)addr) 27 #define HAL_OTG_WRITE32(addr, value) HAL_WRITE32(USB_OTG_REG_BASE, (u32)addr, value) 28 29 #define HAL_OTG_MODIFY32(addr, clrmsk, setmsk) HAL_WRITE32(USB_OTG_REG_BASE,(u32)addr,\ 30 ((HAL_READ32(USB_OTG_REG_BASE, (u32)addr) & (~clrmsk)) | setmsk)) 31 32 #define DWC_READ_REG32(_reg_) HAL_OTG_READ32((u32)_reg_) 33 #define DWC_WRITE_REG32(_reg_, _val_) HAL_OTG_WRITE32((u32)_reg_,_val_) 34 #define DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_) HAL_OTG_MODIFY32((u32)_reg_,_cmsk_,_smsk_) 35 36 // USB OTG addon register 37 #define REG_OTG_PWCSEQ_IP_OFF 0x30004 //This is in OTG IP 38 #define REG_OTG_PS_INTR_STS 0x30008 //This is in OTG IP 39 #define REG_OTG_PS_INTR_MSK 0x3000C //This is in OTG IP 40 41 /* #define REG_OTG_PWCSEQ_IP_OFF 0x30004 */ 42 #define BIT_UPLL_CKRDY BIT(5) /* R/W 0 1: USB PHY clock ready */ 43 #define BIT_USBOTG_EN BIT(8) /* R/W 0 1: Enable USB OTG */ 44 #define BIT_USBPHY_EN BIT(9) /* R/W 0 1: Enable USB PHY */ 45 #endif 46