1 /*
2  * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef APUPWR_CLKCTL_H
8 #define APUPWR_CLKCTL_H
9 
10 #include <arch_helpers.h>
11 #include <apupwr_clkctl_def.h>
12 
13 int32_t apupwr_smc_acc_init_all(void);
14 void apupwr_smc_acc_top(bool enable);
15 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
16 int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);
17 int32_t apupwr_smc_bulk_pll(bool enable);
18 void apupwr_smc_bus_prot_cg_on(void);
19 
20 int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en);
21 int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
22 			  enum pll_set_rate_mode mode, int32_t freq);
23 #endif /* APUPWR_CLKCTL_H */
24