1 /* This file is lisenced under LGPL. 2 * Copyright (C) 2002-2003, George Thanos <george.thanos@gdt.gr> 3 * Yannis Mitsos <yannis.mitsos@gdt.gr> 4 */ 5 #ifndef _BITS_UNISTD_H_ 6 #define _BITS_UNISTD_H_ 7 8 #include <bits/proto.h> 9 #include <errno.h> 10 11 #define __E1_COFF_GCC__ 12 13 /* The following macros have been provided by C.Baumhof 14 * They can be inlined in contrast to the previous ones*/ 15 #define _syscall0(type, name) \ 16 type name(void) \ 17 { \ 18 register int par1 __asm__("L15"); \ 19 register int par2 __asm__("L14"); \ 20 par1 = -1; \ 21 par2 = __NR_##name; \ 22 __asm__ __volatile__( \ 23 "trap 47" \ 24 :"=l"(par1) \ 25 :"0"(par1), "l"(par2) \ 26 :"memory","L14","L15"); \ 27 \ 28 if( par1 < 0 ) { \ 29 __set_errno( -par1 ); \ 30 return -1; \ 31 } else \ 32 return (type)(par1); \ 33 } 34 35 #define _syscall1(type, name,atype, a) \ 36 type name(atype a) \ 37 { \ 38 register int par1 __asm__("L15"); \ 39 register int par2 __asm__("L14"); \ 40 register int par3 __asm__("L13"); \ 41 par1 = -1; \ 42 par2 = __NR_##name; \ 43 par3 = (int)a; \ 44 __asm__ __volatile__( \ 45 "trap 47" \ 46 :"=l"(par1) \ 47 :"0"(par1), "l"(par2), "l"(par3) \ 48 :"memory","L13","L14","L15"); \ 49 \ 50 if( par1 < 0 ) { \ 51 __set_errno( -par1 ); \ 52 return -1; \ 53 } else \ 54 return (type)(par1); \ 55 } 56 57 #define _syscall2(type, name,atype, a, btype, b) \ 58 type name(atype a, btype b) \ 59 { \ 60 register int par1 __asm__("L15"); \ 61 register int par2 __asm__("L14"); \ 62 register int par3 __asm__("L13"); \ 63 register int par4 __asm__("L12"); \ 64 par1 = -1; \ 65 par2 = __NR_##name; \ 66 par3 = (int)a; \ 67 par4 = (int)b; \ 68 __asm__ __volatile__( \ 69 "trap 47" \ 70 :"=l"(par1) \ 71 :"0"(par1), "l"(par2), "l"(par3), "l"(par4) \ 72 :"memory","L12","L13","L14","L15"); \ 73 \ 74 if( par1 < 0 ) { \ 75 __set_errno( -par1 ); \ 76 return -1; \ 77 } else \ 78 return (type)(par1); \ 79 } 80 81 #define _syscall3(type, name,atype, a, btype, b, ctype, c) \ 82 type name(atype a, btype b, ctype c) \ 83 { \ 84 register int par1 __asm__("L15"); \ 85 register int par2 __asm__("L14"); \ 86 register int par3 __asm__("L13"); \ 87 register int par4 __asm__("L12"); \ 88 register int par5 __asm__("L11"); \ 89 par1 = -1; \ 90 par2 = __NR_##name; \ 91 par3 = (int)a; \ 92 par4 = (int)b; \ 93 par5 = (int)c; \ 94 __asm__ __volatile__( \ 95 "trap 47" \ 96 :"=l"(par1) \ 97 :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \ 98 :"memory","L11","L12","L13","L14","L15"); \ 99 \ 100 if( par1 < 0 ) { \ 101 __set_errno( -par1 ); \ 102 return -1; \ 103 } else \ 104 return (type)(par1); \ 105 } 106 107 #define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \ 108 type name(atype a, btype b, ctype c,dtype d) \ 109 { \ 110 register int par1 __asm__("L15"); \ 111 register int par2 __asm__("L14"); \ 112 register int par3 __asm__("L13"); \ 113 register int par4 __asm__("L12"); \ 114 register int par5 __asm__("L11"); \ 115 register int par6 __asm__("L10"); \ 116 par1 = -1; \ 117 par2 = __NR_##name; \ 118 par3 = (int)a; \ 119 par4 = (int)b; \ 120 par5 = (int)c; \ 121 par6 = (int)d; \ 122 __asm__ __volatile__( \ 123 "trap 47" \ 124 :"=l"(par1) \ 125 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \ 126 :"memory","L10","L11","L12","L13","L14","L15"); \ 127 \ 128 if( par1 < 0 ) { \ 129 __set_errno( -par1 ); \ 130 return -1; \ 131 } else \ 132 return (type)(par1); \ 133 } 134 135 #define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \ 136 type name(atype a, btype b, ctype c,dtype d, etype e) \ 137 { \ 138 register int par1 __asm__("L15"); \ 139 register int par2 __asm__("L14"); \ 140 register int par3 __asm__("L13"); \ 141 register int par4 __asm__("L12"); \ 142 register int par5 __asm__("L11"); \ 143 register int par6 __asm__("L10"); \ 144 register int par7 __asm__("L9"); \ 145 par1 = -1; \ 146 par2 = __NR_##name; \ 147 par3 = (int)a; \ 148 par4 = (int)b; \ 149 par5 = (int)c; \ 150 par6 = (int)d; \ 151 par7 = (int)e; \ 152 __asm__ __volatile__( \ 153 "trap 47" \ 154 :"=l"(par1) \ 155 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \ 156 :"memory","L9","L10","L11","L12","L13","L14","L15"); \ 157 \ 158 if( par1 < 0 ) { \ 159 __set_errno( -par1 ); \ 160 return -1; \ 161 } else \ 162 return (type)(par1); \ 163 return (type)(par1); \ 164 } 165 166 #define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \ 167 type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \ 168 { \ 169 register int par1 __asm__("L15"); \ 170 register int par2 __asm__("L14"); \ 171 register int par3 __asm__("L13"); \ 172 register int par4 __asm__("L12"); \ 173 register int par5 __asm__("L11"); \ 174 register int par6 __asm__("L10"); \ 175 register int par7 __asm__("L9"); \ 176 register int par8 __asm__("L8"); \ 177 int sys_retval; \ 178 par1 = -1; \ 179 par2 = __NR_##name; \ 180 par3 = (int)a; \ 181 par4 = (int)b; \ 182 par5 = (int)c; \ 183 par6 = (int)d; \ 184 par7 = (int)e; \ 185 par7 = (int)f; \ 186 __asm__ __volatile__( \ 187 "trap 47" \ 188 :"=l"(par1) \ 189 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \ 190 :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \ 191 \ 192 if( par1 < 0 ) { \ 193 __set_errno( -par1 ); \ 194 return -1; \ 195 } else \ 196 return (type)(par1); \ 197 } 198 199 #define __syscall0(type, name) \ 200 type name(...) \ 201 { \ 202 register int par1 __asm__("L15"); \ 203 register int par2 __asm__("L14"); \ 204 par1 = -1; \ 205 par2 = __NR_##name; \ 206 __asm__ __volatile__( \ 207 "trap 47" \ 208 :"=l"(par1) \ 209 :"0"(par1), "l"(par2)\ 210 :"memory","L14","L15"); \ 211 \ 212 if( par1 < 0 ) { \ 213 __set_errno( -par1 ); \ 214 return -1; \ 215 } else \ 216 return (type)(par1); \ 217 } 218 219 #define __syscall1(type, name, atype, a) \ 220 type name(atype a, ...) \ 221 { \ 222 register int par1 __asm__("L15"); \ 223 register int par2 __asm__("L14"); \ 224 register int par3 __asm__("L13"); \ 225 par1 = -1; \ 226 par2 = __NR_##name; \ 227 par3 = (int)a; \ 228 __asm__ __volatile__( \ 229 "trap 47" \ 230 :"=l"(par1) \ 231 :"0"(par1), "l"(par2), "l"(par3)\ 232 :"memory","L13","L14","L15"); \ 233 \ 234 if( par1 < 0 ) { \ 235 __set_errno( -par1 ); \ 236 return -1; \ 237 } else \ 238 return (type)(par1); \ 239 } 240 241 #define __syscall2(type, name,atype, a, btype, b) \ 242 type name(atype a, btype b, ...) \ 243 { \ 244 register int par1 __asm__("L15"); \ 245 register int par2 __asm__("L14"); \ 246 register int par3 __asm__("L13"); \ 247 register int par4 __asm__("L12"); \ 248 par1 = -1; \ 249 par2 = __NR_##name; \ 250 par3 = (int)a; \ 251 par4 = (int)b; \ 252 __asm__ __volatile__( \ 253 "trap 47" \ 254 :"=l"(par1) \ 255 :"0"(par1), "l"(par2), "l"(par3), "l"(par4)\ 256 :"memory","L12","L13","L14","L15"); \ 257 \ 258 if( par1 < 0 ) { \ 259 __set_errno( -par1 ); \ 260 return -1; \ 261 } else \ 262 return (type)(par1); \ 263 } 264 265 #define __syscall3(type, name,atype, a, btype, b, ctype, c) \ 266 type name(atype a, btype b, ctype c, ...) \ 267 { \ 268 register int par1 __asm__("L15"); \ 269 register int par2 __asm__("L14"); \ 270 register int par3 __asm__("L13"); \ 271 register int par4 __asm__("L12"); \ 272 register int par5 __asm__("L11"); \ 273 par1 = -1; \ 274 par2 = __NR_##name; \ 275 par3 = (int)a; \ 276 par4 = (int)b; \ 277 par5 = (int)c; \ 278 __asm__ __volatile__( \ 279 "trap 47" \ 280 :"=l"(par1) \ 281 :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \ 282 :"memory","L11","L12","L13","L14","L15"); \ 283 \ 284 if( par1 < 0 ) { \ 285 __set_errno( -par1 ); \ 286 return -1; \ 287 } else \ 288 return (type)(par1); \ 289 } 290 291 #define __syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \ 292 type name(atype a, btype b, ctype c,dtype d, ...) \ 293 { \ 294 register int par1 __asm__("L15"); \ 295 register int par2 __asm__("L14"); \ 296 register int par3 __asm__("L13"); \ 297 register int par4 __asm__("L12"); \ 298 register int par5 __asm__("L11"); \ 299 register int par6 __asm__("L10"); \ 300 par1 = -1; \ 301 par2 = __NR_##name; \ 302 par3 = (int)a; \ 303 par4 = (int)b; \ 304 par5 = (int)c; \ 305 par6 = (int)d; \ 306 __asm__ __volatile__( \ 307 "trap 47" \ 308 :"=l"(par1) \ 309 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \ 310 :"memory","L10","L11","L12","L13","L14","L15"); \ 311 \ 312 if( par1 < 0 ) { \ 313 __set_errno( -par1 ); \ 314 return -1; \ 315 } else \ 316 return (type)(par1); \ 317 } 318 319 #define __syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \ 320 type name(atype a, btype b, ctype c,dtype d, etype e, ...) \ 321 { \ 322 register int par1 __asm__("L15"); \ 323 register int par2 __asm__("L14"); \ 324 register int par3 __asm__("L13"); \ 325 register int par4 __asm__("L12"); \ 326 register int par5 __asm__("L11"); \ 327 register int par6 __asm__("L10"); \ 328 register int par7 __asm__("L9"); \ 329 par1 = -1; \ 330 par2 = __NR_##name; \ 331 par3 = (int)a; \ 332 par4 = (int)b; \ 333 par5 = (int)c; \ 334 par6 = (int)d; \ 335 par7 = (int)e; \ 336 __asm__ __volatile__( \ 337 "trap 47" \ 338 :"=l"(par1) \ 339 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \ 340 :"memory","L9","L10","L11","L12","L13","L14","L15"); \ 341 \ 342 if( par1 < 0 ) { \ 343 __set_errno( -par1 ); \ 344 return -1; \ 345 } else \ 346 return (type)(par1); \ 347 } 348 349 #define __syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \ 350 type name(atype a, btype b, ctype c,dtype d, etype e, ftype f, ...) \ 351 { \ 352 register int par1 __asm__("L15"); \ 353 register int par2 __asm__("L14"); \ 354 register int par3 __asm__("L13"); \ 355 register int par4 __asm__("L12"); \ 356 register int par5 __asm__("L11"); \ 357 register int par6 __asm__("L10"); \ 358 register int par7 __asm__("L9"); \ 359 register int par8 __asm__("L8"); \ 360 par1 = -1; \ 361 par2 = __NR_##name; \ 362 par3 = (int)a; \ 363 par4 = (int)b; \ 364 par5 = (int)c; \ 365 par6 = (int)d; \ 366 par7 = (int)e; \ 367 par7 = (int)f; \ 368 __asm__ __volatile__( \ 369 "trap 47" \ 370 :"=l"(par1) \ 371 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \ 372 :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \ 373 \ 374 if( par1 < 0 ) { \ 375 __set_errno( -par1 ); \ 376 return -1; \ 377 } else \ 378 return (type)(par1); \ 379 } 380 381 #if 0 382 #define _syscall3(type, name,atype, a , btype, b, ctype, c) \ 383 type name(atype a, btype b, ctype c,) \ 384 { \ 385 __asm__ __volatile__( \ 386 "movi L9, -1\n\t" \ 387 "movi L8, %0\n\t" \ 388 "ldw.d G3, L7, 0\n\t" \ 389 "ldw.d G3, L6, 4\n\t" \ 390 "ldw.d G3, L5, 8\n\t" \ 391 :/* no output */ \ 392 :"i"(__NR_##name) \ 393 :"cc","memory","%L5","L6","L7","L8","L9");\ 394 __asm__ __volatile__( \ 395 "trap 47\n\t" \ 396 "mov L2, L9\n\t"); \ 397 } 398 399 #define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \ 400 type name(atype a, btype b, ctype c,dtype d) \ 401 { \ 402 __asm__ __volatile__( \ 403 "movi L11, -1\n\t" \ 404 "movi L10, %0\n\t" \ 405 "ldw.d G3, L9, 0\n\t" \ 406 "ldw.d G3, L8, 4\n\t" \ 407 "ldw.d G3, L7, 8\n\t" \ 408 "ldw.d G3, L6, 12\n\t" \ 409 :/* no output */ \ 410 :"i"(__NR_##name) \ 411 :"cc","memory","L6","L7","L8","L9","L10","L11");\ 412 __asm__ __volatile__( \ 413 "trap 47\n\t" \ 414 "mov L2, L11\n\t"); \ 415 } 416 417 #define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \ 418 type name(atype a, btype b, ctype c,dtype d, etype e) \ 419 { \ 420 __asm__ __volatile__( \ 421 "movi L13, -1\n\t" \ 422 "movi L12, %0\n\t" \ 423 "ldw.d G3, L11, 0\n\t" \ 424 "ldw.d G3, L10, 4\n\t" \ 425 "ldw.d G3, L9, 8\n\t" \ 426 "ldw.d G3, L8, 12\n\t" \ 427 "ldw.d G3, L7, 16\n\t" \ 428 :/* no output */ \ 429 :"i"(__NR_##name) \ 430 :"cc","memory","L7","L8","L9","L10","L11","L12","L13");\ 431 __asm__ __volatile__( \ 432 "trap 47\n\t" \ 433 "mov L2, L13\n\t"); \ 434 } 435 436 #define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \ 437 type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \ 438 { \ 439 __asm__ __volatile__( \ 440 "movi L15, -1\n\t" \ 441 "movi L14, %0\n\t" \ 442 "ldw.d G3, L13, 0\n\t" \ 443 "ldw.d G3, L12, 4\n\t" \ 444 "ldw.d G3, L11, 8\n\t" \ 445 "ldw.d G3, L10, 12\n\t" \ 446 "ldw.d G3, L9, 16\n\t" \ 447 "ldw.d G3, L8, 20\n\t" \ 448 :/* no output */ \ 449 :"i"(__NR_##name) \ 450 :"cc","memory","L8","L9","L10","L11","L12","L13","L14","L15");\ 451 __asm__ __volatile__( \ 452 "trap 47\n\t" \ 453 "mov L2, L15\n\t"); \ 454 } 455 #endif 456 457 #endif /* !_HYPERSTONE_NOMMU_UNISTD_H_ */ 458