1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 6 #ifndef _CONFIG_IMX6SL_H 7 #define _CONFIG_IMX6SL_H 8 9 /* 10 * PL310 TAG RAM Control Register 11 * 12 * bit[10:8]:1 - 2 cycle of write accesses latency 13 * bit[6:4]:3 - 4 cycle of read accesses latency 14 * bit[2:0]:2 - 3 cycle of setup latency 15 */ 16 #ifndef PL310_TAG_RAM_CTRL_INIT 17 #define PL310_TAG_RAM_CTRL_INIT 0x00000132 18 #endif 19 20 /* 21 * PL310 DATA RAM Control Register 22 * 23 * bit[10:8]:1 - 2 cycle of write accesses latency 24 * bit[6:4]:3 - 4 cycle of read accesses latency 25 * bit[2:0]:2 - 3 cycle of setup latency 26 */ 27 #ifndef PL310_DATA_RAM_CTRL_INIT 28 #define PL310_DATA_RAM_CTRL_INIT 0x00000132 29 #endif 30 31 /* 32 * PL310 Auxiliary Control Register 33 * 34 * Early BRESP enabled (bit30=1) 35 * I/Dcache prefetch enabled (bit29:28=2b11) 36 * NS can access interrupts (bit27=1) 37 * NS can lockown cache lines (bit26=1) 38 * Pseudo-random replacement policy (bit25=1) 39 * Force write allocated (default) (bit24:23=00) 40 * Shared attribute internally ignored (bit22=1, bit13=0) 41 * Parity disabled (bit21=0) 42 * Event monitor disabled (bit20=0) 43 * 16kb way size (bit19:17=3b001) 44 * 16-way associativity (bit16=1) 45 * Store buffer device limitation enabled (bit11=0) 46 * Cacheable accesses have high prio (bit10=0) 47 * Full Line Zero (FLZ) enabled (bit0=1) 48 */ 49 #ifndef PL310_AUX_CTRL_INIT 50 #define PL310_AUX_CTRL_INIT 0x7E430001 51 #endif 52 53 /* 54 * PL310 Prefetch Control Register 55 * 56 * Double linefill enabled (bit30=1) 57 * I/D prefetch enabled (bit29:28=2b11) 58 * Prefetch drop disabled (bit24=0) 59 * Incr double linefill disable (bit23=0) 60 * Prefetch offset = 0xF (bit4:0) 61 */ 62 #define PL310_PREFETCH_CTRL_INIT 0x7000000F 63 64 /* 65 * PL310 Power Register 66 * 67 * Dynamic clock gating enabled 68 * Standby mode enabled 69 */ 70 #define PL310_POWER_CTRL_INIT 0x00000003 71 72 /* 73 * SCU Invalidate Register 74 * 75 * Invalidate all registers 76 */ 77 #define SCU_INV_CTRL_INIT 0xFFFFFFFF 78 79 /* 80 * SCU Access Register 81 * - both secure CPU access SCU 82 */ 83 #define SCU_SAC_CTRL_INIT 0x0000000F 84 85 /* 86 * SCU NonSecure Access Register 87 * - both nonsec cpu access SCU, private and global timer 88 */ 89 #define SCU_NSAC_CTRL_INIT 0x00000FFF 90 91 #endif 92