1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "config_clock.h"
9 #include "n1sdp_scp_mmap.h"
10 #include "n1sdp_system_clock.h"
11
12 #include <mod_n1sdp_pll.h>
13
14 #include <fwk_element.h>
15 #include <fwk_id.h>
16 #include <fwk_macros.h>
17 #include <fwk_module.h>
18
19 static const struct fwk_element n1sdp_pll_element_table[] = {
20 [CLOCK_PLL_IDX_CPU0] = {
21 .name = "CPU_PLL_0",
22 .data = &((struct mod_n1sdp_pll_dev_config) {
23 .control_reg0 = (void *)SCP_PLL_CPU0_CTRL,
24 .control_reg1 = (void *)SCP_PLL_CPU0_STAT,
25 .initial_rate = N1SDP_PLL_RATE_CPU_PLL0,
26 .ref_rate = CLOCK_RATE_REFCLK,
27 }),
28 },
29 [CLOCK_PLL_IDX_CPU1] = {
30 .name = "CPU_PLL_1",
31 .data = &((struct mod_n1sdp_pll_dev_config) {
32 .control_reg0 = (void *)SCP_PLL_CPU1_CTRL,
33 .control_reg1 = (void *)SCP_PLL_CPU1_STAT,
34 .initial_rate = N1SDP_PLL_RATE_CPU_PLL1,
35 .ref_rate = CLOCK_RATE_REFCLK,
36 }),
37 },
38 [CLOCK_PLL_IDX_CLUS] = {
39 .name = "CLUSTER_PLL",
40 .data = &((struct mod_n1sdp_pll_dev_config) {
41 .control_reg0 = (void *)SCP_PLL_CLUS_CTRL,
42 .control_reg1 = (void *)SCP_PLL_CLUS_STAT,
43 .initial_rate = N1SDP_PLL_RATE_CLUSTER_PLL,
44 .ref_rate = CLOCK_RATE_REFCLK,
45 }),
46 },
47 [CLOCK_PLL_IDX_INTERCONNECT] = {
48 .name = "INT_PLL",
49 .data = &((struct mod_n1sdp_pll_dev_config) {
50 .control_reg0 = (void *)SCP_PLL_INTERCONNECT_CTRL,
51 .control_reg1 = (void *)SCP_PLL_INTERCONNECT_STAT,
52 .initial_rate = N1SDP_PLL_RATE_INTERCONNECT_PLL,
53 .ref_rate = CLOCK_RATE_REFCLK,
54 }),
55 },
56 [CLOCK_PLL_IDX_SYS] = {
57 .name = "SYS_PLL",
58 .data = &((struct mod_n1sdp_pll_dev_config) {
59 .control_reg0 = (void *)SCP_PLL_SYSPLL_CTRL,
60 .control_reg1 = (void *)SCP_PLL_SYSPLL_STAT,
61 .initial_rate = N1SDP_PLL_RATE_SYSTEM_PLL,
62 .ref_rate = CLOCK_RATE_REFCLK,
63 }),
64 },
65 [CLOCK_PLL_IDX_DMC] = {
66 .name = "DMC_PLL",
67 .data = &((struct mod_n1sdp_pll_dev_config) {
68 .control_reg0 = (void *)SCP_PLL_DMC_CTRL,
69 .control_reg1 = (void *)SCP_PLL_DMC_STAT,
70 .initial_rate = N1SDP_PLL_RATE_DMC_PLL,
71 .ref_rate = CLOCK_RATE_REFCLK,
72 }),
73 },
74 [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */
75 };
76
n1sdp_pll_get_element_table(fwk_id_t module_id)77 static const struct fwk_element *n1sdp_pll_get_element_table
78 (fwk_id_t module_id)
79 {
80 return n1sdp_pll_element_table;
81 }
82
83 const struct fwk_module_config config_n1sdp_pll = {
84 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(n1sdp_pll_get_element_table),
85 };
86