1 /*
2  * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A15_H
8 #define CORTEX_A15_H
9 
10 #include <lib/utils_def.h>
11 
12 /*******************************************************************************
13  * Auxiliary Control Register 2 specific definitions.
14  ******************************************************************************/
15 #define CORTEX_A15_ACTLR2			p15, 1, c15, c0, 4
16 
17 #define CORTEX_A15_ACTLR2_INV_DCC_BIT		(U(1) << 0)
18 
19 /*******************************************************************************
20  * Cortex-A15 midr with version/revision set to 0
21  ******************************************************************************/
22 #define CORTEX_A15_MIDR			U(0x410FC0F0)
23 
24 /*******************************************************************************
25  * CPU Auxiliary Control register specific definitions.
26  ******************************************************************************/
27 #define CORTEX_A15_ACTLR_INV_BTB_BIT	(U(1) << 0)
28 #define CORTEX_A15_ACTLR_SMP_BIT	(U(1) << 6)
29 
30 #endif /* CORTEX_A15_H */
31