1 /*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4
5
6 /******************************************************************************
7 * @file devices.c
8 * @brief source file for the devices
9 * @version V1.0
10 * @date 07. Mar 2019
11 ******************************************************************************/
12
13 #include <stdio.h>
14 #include <csi_config.h>
15 #include <soc.h>
16 #include <drv_usart.h>
17 #include <drv_timer.h>
18 #include <drv_gpio.h>
19 #include <pin_name.h>
20
21 extern void TIM0_IRQHandler(void);
22 extern void TIM1_IRQHandler(void);
23 extern void TIM2_IRQHandler(void);
24 extern void TIM3_IRQHandler(void);
25 extern void USART_IRQHandler(void);
26 extern void GPIO0_IRQHandler(void);
27 extern void GPIO1_IRQHandler(void);
28 extern void GPIO2_IRQHandler(void);
29 extern void GPIO3_IRQHandler(void);
30 extern void GPIO4_IRQHandler(void);
31 extern void GPIO5_IRQHandler(void);
32 extern void GPIO6_IRQHandler(void);
33 extern void GPIO7_IRQHandler(void);
34
35 struct {
36 uint64_t base;
37 uint32_t irq;
38 void *handler;
39 }
40 const sg_usart_config[CONFIG_USART_NUM] = {
41 {CSKY_UART_BASE, UART_IRQn, USART_IRQHandler},
42 };
43
target_usart_init(int32_t idx,uint64_t * base,uint32_t * irq,void ** handler)44 int32_t target_usart_init(int32_t idx, uint64_t *base, uint32_t *irq, void **handler)
45 {
46 if (idx >= CONFIG_USART_NUM) {
47 return -1;
48 }
49
50 if (base != NULL) {
51 *base = sg_usart_config[idx].base;
52 }
53
54 if (irq != NULL) {
55 *irq = sg_usart_config[idx].irq;
56 }
57
58 if (handler != NULL) {
59 *handler = sg_usart_config[idx].handler;
60 }
61
62 return idx;
63 }
64
65 struct {
66 uint64_t base;
67 uint32_t irq;
68 void *handler;
69 }
70 const sg_timer_config[CONFIG_TIMER_NUM] = {
71 {CSKY_TIMER0_BASE, TIM0_IRQn, TIM0_IRQHandler},
72 {CSKY_TIMER1_BASE, TIM1_IRQn, TIM1_IRQHandler},
73 {CSKY_TIMER2_BASE, TIM2_IRQn, TIM2_IRQHandler},
74 {CSKY_TIMER3_BASE, TIM3_IRQn, TIM3_IRQHandler},
75 };
76
target_get_timer_count(void)77 int32_t target_get_timer_count(void)
78 {
79 return CONFIG_TIMER_NUM;
80 }
81
target_get_timer(int32_t idx,uint64_t * base,uint32_t * irq,void ** handler)82 int32_t target_get_timer(int32_t idx, uint64_t *base, uint32_t *irq, void **handler)
83 {
84 if (idx >= target_get_timer_count()) {
85 return -1;
86 }
87
88 if (base != NULL) {
89 *base = sg_timer_config[idx].base;
90 }
91
92 if (irq != NULL) {
93 *irq = sg_timer_config[idx].irq;
94 }
95
96 if (handler != NULL) {
97 *handler = sg_timer_config[idx].handler;
98 }
99
100 return idx;
101 }
102
103 struct {
104 uint64_t base;
105 uint32_t irq;
106 uint32_t pin_num;
107 port_name_e port;
108 }
109 const sg_gpio_config[CONFIG_GPIO_NUM] = {
110 {CSKY_GPIOA_BASE, GPIO0_IRQn, 0, PORTA},
111 {CSKY_GPIOA_BASE, GPIO1_IRQn, 0, PORTB},
112 {CSKY_GPIOA_BASE, GPIO2_IRQn, 0, PORTC},
113 {CSKY_GPIOA_BASE, GPIO3_IRQn, 0, PORTD},
114 {CSKY_GPIOA_BASE, GPIO4_IRQn, 0, PORTE},
115 {CSKY_GPIOA_BASE, GPIO5_IRQn, 0, PORTF},
116 {CSKY_GPIOA_BASE, GPIO6_IRQn, 0, PORTG},
117 {CSKY_GPIOA_BASE, GPIO7_IRQn, 0, PORTH},
118 };
119
120 typedef struct {
121 int32_t gpio_pin;
122 uint32_t cfg_idx;
123 } gpio_pin_map_t;
124 const static gpio_pin_map_t s_gpio_pin_map[] = {
125 {PA0, 0},
126 {PA1, 1},
127 {PA2, 2},
128 {PA3, 3},
129 {PA4, 4},
130 {PA5, 5},
131 {PA6, 6},
132 {PA7, 7}
133 };
134
target_gpio_port_init(port_name_e port,uint64_t * base,uint32_t * irq,void ** handler,uint32_t * pin_num)135 int32_t target_gpio_port_init(port_name_e port, uint64_t *base, uint32_t *irq, void **handler, uint32_t *pin_num)
136 {
137 int i;
138
139 for (i = 0; i < CONFIG_GPIO_NUM; i++) {
140 if (sg_gpio_config[i].port == port) {
141 if (base != NULL) {
142 *base = sg_gpio_config[i].base;
143 }
144
145 if (irq != NULL) {
146 *irq = sg_gpio_config[i].irq;
147 }
148
149 if (pin_num != NULL) {
150 *pin_num = sg_gpio_config[i].pin_num;
151 }
152
153 if (handler != NULL) {
154 switch (i) {
155 case 0:
156 *handler = (void *)GPIO0_IRQHandler;
157 break;
158
159 case 1:
160 *handler = (void *)GPIO1_IRQHandler;
161 break;
162
163 case 2:
164 *handler = (void *)GPIO2_IRQHandler;
165 break;
166
167 case 3:
168 *handler = (void *)GPIO3_IRQHandler;
169 break;
170
171 case 4:
172 *handler = (void *)GPIO4_IRQHandler;
173 break;
174
175 case 5:
176 *handler = (void *)GPIO5_IRQHandler;
177 break;
178
179 case 6:
180 *handler = (void *)GPIO6_IRQHandler;
181 break;
182
183 case 7:
184 *handler = (void *)GPIO7_IRQHandler;
185 break;
186 }
187 }
188
189 return i;
190 }
191 }
192
193 return -1;
194 }
195
target_gpio_pin_init(int32_t gpio_pin,uint32_t * port_idx)196 int32_t target_gpio_pin_init(int32_t gpio_pin, uint32_t *port_idx)
197 {
198 uint32_t idx;
199
200 for (idx = 0; idx < sizeof(s_gpio_pin_map) / sizeof(gpio_pin_map_t); idx++) {
201 if (s_gpio_pin_map[idx].gpio_pin == gpio_pin) {
202 if (port_idx != NULL) {
203 *port_idx = s_gpio_pin_map[idx].cfg_idx;
204 }
205
206 return idx;
207 }
208 }
209
210 return -1;
211 }
212