1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3 * Copyright (c) 2022, Linaro Limited
4 *
5 * The definitions in this file are based on
6 * TCG PC Client Platform TPM Profile Specification for TPM 2.0
7 * v1.0.5 Revision 14
8 */
9
10 #ifndef __DRIVERS_TPM2_CHIP_H
11 #define __DRIVERS_TPM2_CHIP_H
12
13 #include <stdint.h>
14 #include <tee_api_types.h>
15 #include <types_ext.h>
16 #include <util.h>
17
18 /*
19 * TPM2 interface related and generic errors
20 */
21 enum tpm2_result {
22 TPM2_OK = 0,
23
24 TPM2_ERR_GENERIC,
25 TPM2_ERR_INVALID_ARG,
26 TPM2_ERR_ARG_LIST_TOO_LONG,
27 TPM2_ERR_BUSY,
28 TPM2_ERR_TIMEOUT,
29 TPM2_ERR_IO,
30 TPM2_ERR_NODEV,
31 TPM2_ERR_NO_ACTIVE_LOCALITY,
32 TPM2_ERR_SHORT_BUFFER,
33 TPM2_ERR_CMD,
34 };
35
36 /* TPM Command Duration in ms as defined in Table 17 of the spec */
37 enum tpm2_cmd_duration {
38 TPM2_CMD_DURATION_SHORT = 20,
39 TPM2_CMD_DURATION_MEDIUM = 750,
40 TPM2_CMD_DURATION_LONG = 2000,
41 /* Picked up from Linux TPM driver */
42 TPM2_CMD_DURATION_DEFAULT = 120000,
43 };
44
45 #define TPM2_TIMEOUT_RETRY_MS 5
46
47 /* TPM Interface timouts in ms as defined Table 18 of the spec */
48 enum tpm2_interface_timeouts {
49 TPM2_TIMEOUT_A = 750,
50 TPM2_TIMEOUT_B = 2000,
51 TPM2_TIMEOUT_C = 200,
52 TPM2_TIMEOUT_D = 30,
53 };
54
55 enum tpm2_interface {
56 TPM2_PTP_FIFO,
57 TPM2_PTP_CRB
58 };
59
60 struct tpm2_caps {
61 uint32_t num_pcrs; /* Number of PCRs chip supports */
62 uint32_t pcr_select_min; /* Min octets to represent PCR bitmap */
63 uint32_t num_banks; /* Number of banks/algs supported */
64 uint32_t num_active_banks; /* Number of active banks/algs */
65 uint32_t selection_mask; /* Bitmap of supported banks/algs */
66 uint32_t active_mask; /* Bitmap of active banks/algs */
67 };
68
69 struct tpm2_chip {
70 const struct tpm2_ptp_ops *ops;
71 const struct tpm2_ptp_phy_ops *phy_ops;
72 enum tpm2_interface ptp_type;
73 struct tpm2_caps capability;
74 int32_t locality;
75 uint32_t timeout_a;
76 uint32_t timeout_b;
77 uint32_t timeout_c;
78 uint32_t timeout_d;
79 };
80
81 struct tpm2_ptp_ops {
82 enum tpm2_result (*init)(struct tpm2_chip *chip);
83 enum tpm2_result (*end)(struct tpm2_chip *chip);
84 enum tpm2_result (*send)(struct tpm2_chip *chip, uint8_t *buf,
85 uint32_t len);
86 enum tpm2_result (*recv)(struct tpm2_chip *chip, uint8_t *buf,
87 uint32_t *len, uint32_t cmd_duration);
88 };
89
90 /* Physical interface for PTP */
91 struct tpm2_ptp_phy_ops {
92 enum tpm2_result (*rx32)(struct tpm2_chip *chip, uint32_t adr,
93 uint32_t *buf);
94 enum tpm2_result (*tx32)(struct tpm2_chip *chip, uint32_t adr,
95 uint32_t val);
96 enum tpm2_result (*rx8)(struct tpm2_chip *chip, uint32_t adr,
97 uint16_t len, uint8_t *buf);
98 enum tpm2_result (*tx8)(struct tpm2_chip *chip, uint32_t adr,
99 uint16_t len, uint8_t *buf);
100 };
101
102 enum tpm2_result tpm2_chip_register(struct tpm2_chip *chip);
103 enum tpm2_result tpm2_chip_unregister(struct tpm2_chip *chip);
104
105 enum tpm2_result tpm2_chip_send(uint8_t *buf, uint32_t len);
106 enum tpm2_result tpm2_chip_recv(uint8_t *buf, uint32_t *len,
107 uint32_t cmd_duration);
108
109 enum tpm2_result tpm2_chip_get_caps(struct tpm2_caps *capability);
110 bool tpm2_chip_is_active_bank(uint16_t alg);
111
112 #ifdef CFG_CORE_TCG_PROVIDER
113 TEE_Result tpm2_tcg_register(void);
114 #else
tpm2_tcg_register(void)115 static inline TEE_Result tpm2_tcg_register(void)
116 {
117 return TEE_ERROR_NOT_IMPLEMENTED;
118 }
119 #endif
120
121 #endif /* __DRIVERS_TPM2_CHIP_H */
122