1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9 #include <linux/gpio/driver.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/platform_data/gpio-davinci.h>
23 #include <linux/irqchip/chained_irq.h>
24 #include <linux/spinlock.h>
25 #include <linux/pm_runtime.h>
26
27 #include <asm-generic/gpio.h>
28
29 #define MAX_REGS_BANKS 5
30 #define MAX_INT_PER_BANK 32
31
32 struct davinci_gpio_regs {
33 u32 dir;
34 u32 out_data;
35 u32 set_data;
36 u32 clr_data;
37 u32 in_data;
38 u32 set_rising;
39 u32 clr_rising;
40 u32 set_falling;
41 u32 clr_falling;
42 u32 intstat;
43 };
44
45 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
46
47 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
48
49 static void __iomem *gpio_base;
50 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
51
52 struct davinci_gpio_irq_data {
53 void __iomem *regs;
54 struct davinci_gpio_controller *chip;
55 int bank_num;
56 };
57
58 struct davinci_gpio_controller {
59 struct gpio_chip chip;
60 struct irq_domain *irq_domain;
61 /* Serialize access to GPIO registers */
62 spinlock_t lock;
63 void __iomem *regs[MAX_REGS_BANKS];
64 int gpio_unbanked;
65 int irqs[MAX_INT_PER_BANK];
66 struct davinci_gpio_regs context[MAX_REGS_BANKS];
67 u32 binten_context;
68 };
69
__gpio_mask(unsigned gpio)70 static inline u32 __gpio_mask(unsigned gpio)
71 {
72 return 1 << (gpio % 32);
73 }
74
irq2regs(struct irq_data * d)75 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
76 {
77 struct davinci_gpio_regs __iomem *g;
78
79 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
80
81 return g;
82 }
83
84 static int davinci_gpio_irq_setup(struct platform_device *pdev);
85
86 /*--------------------------------------------------------------------------*/
87
88 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
__davinci_direction(struct gpio_chip * chip,unsigned offset,bool out,int value)89 static inline int __davinci_direction(struct gpio_chip *chip,
90 unsigned offset, bool out, int value)
91 {
92 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
93 struct davinci_gpio_regs __iomem *g;
94 unsigned long flags;
95 u32 temp;
96 int bank = offset / 32;
97 u32 mask = __gpio_mask(offset);
98
99 g = d->regs[bank];
100 spin_lock_irqsave(&d->lock, flags);
101 temp = readl_relaxed(&g->dir);
102 if (out) {
103 temp &= ~mask;
104 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
105 } else {
106 temp |= mask;
107 }
108 writel_relaxed(temp, &g->dir);
109 spin_unlock_irqrestore(&d->lock, flags);
110
111 return 0;
112 }
113
davinci_direction_in(struct gpio_chip * chip,unsigned offset)114 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
115 {
116 return __davinci_direction(chip, offset, false, 0);
117 }
118
119 static int
davinci_direction_out(struct gpio_chip * chip,unsigned offset,int value)120 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
121 {
122 return __davinci_direction(chip, offset, true, value);
123 }
124
125 /*
126 * Read the pin's value (works even if it's set up as output);
127 * returns zero/nonzero.
128 *
129 * Note that changes are synched to the GPIO clock, so reading values back
130 * right after you've set them may give old values.
131 */
davinci_gpio_get(struct gpio_chip * chip,unsigned offset)132 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
133 {
134 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
135 struct davinci_gpio_regs __iomem *g;
136 int bank = offset / 32;
137
138 g = d->regs[bank];
139
140 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
141 }
142
143 /*
144 * Assuming the pin is muxed as a gpio output, set its output value.
145 */
146 static void
davinci_gpio_set(struct gpio_chip * chip,unsigned offset,int value)147 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
148 {
149 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
150 struct davinci_gpio_regs __iomem *g;
151 int bank = offset / 32;
152
153 g = d->regs[bank];
154
155 writel_relaxed(__gpio_mask(offset),
156 value ? &g->set_data : &g->clr_data);
157 }
158
159 static struct davinci_gpio_platform_data *
davinci_gpio_get_pdata(struct platform_device * pdev)160 davinci_gpio_get_pdata(struct platform_device *pdev)
161 {
162 struct device_node *dn = pdev->dev.of_node;
163 struct davinci_gpio_platform_data *pdata;
164 int ret;
165 u32 val;
166
167 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
168 return dev_get_platdata(&pdev->dev);
169
170 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
171 if (!pdata)
172 return NULL;
173
174 ret = of_property_read_u32(dn, "ti,ngpio", &val);
175 if (ret)
176 goto of_err;
177
178 pdata->ngpio = val;
179
180 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
181 if (ret)
182 goto of_err;
183
184 pdata->gpio_unbanked = val;
185
186 return pdata;
187
188 of_err:
189 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
190 return NULL;
191 }
192
davinci_gpio_probe(struct platform_device * pdev)193 static int davinci_gpio_probe(struct platform_device *pdev)
194 {
195 int bank, i, ret = 0;
196 unsigned int ngpio, nbank, nirq;
197 struct davinci_gpio_controller *chips;
198 struct davinci_gpio_platform_data *pdata;
199 struct device *dev = &pdev->dev;
200
201 pdata = davinci_gpio_get_pdata(pdev);
202 if (!pdata) {
203 dev_err(dev, "No platform data found\n");
204 return -EINVAL;
205 }
206
207 dev->platform_data = pdata;
208
209 /*
210 * The gpio banks conceptually expose a segmented bitmap,
211 * and "ngpio" is one more than the largest zero-based
212 * bit index that's valid.
213 */
214 ngpio = pdata->ngpio;
215 if (ngpio == 0) {
216 dev_err(dev, "How many GPIOs?\n");
217 return -EINVAL;
218 }
219
220 /*
221 * If there are unbanked interrupts then the number of
222 * interrupts is equal to number of gpios else all are banked so
223 * number of interrupts is equal to number of banks(each with 16 gpios)
224 */
225 if (pdata->gpio_unbanked)
226 nirq = pdata->gpio_unbanked;
227 else
228 nirq = DIV_ROUND_UP(ngpio, 16);
229
230 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
231 if (!chips)
232 return -ENOMEM;
233
234 gpio_base = devm_platform_ioremap_resource(pdev, 0);
235 if (IS_ERR(gpio_base))
236 return PTR_ERR(gpio_base);
237
238 for (i = 0; i < nirq; i++) {
239 chips->irqs[i] = platform_get_irq(pdev, i);
240 if (chips->irqs[i] < 0)
241 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
242 }
243
244 chips->chip.label = dev_name(dev);
245
246 chips->chip.direction_input = davinci_direction_in;
247 chips->chip.get = davinci_gpio_get;
248 chips->chip.direction_output = davinci_direction_out;
249 chips->chip.set = davinci_gpio_set;
250
251 chips->chip.ngpio = ngpio;
252 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
253
254 #ifdef CONFIG_OF_GPIO
255 chips->chip.parent = dev;
256 chips->chip.request = gpiochip_generic_request;
257 chips->chip.free = gpiochip_generic_free;
258 #endif
259 spin_lock_init(&chips->lock);
260
261 nbank = DIV_ROUND_UP(ngpio, 32);
262 for (bank = 0; bank < nbank; bank++)
263 chips->regs[bank] = gpio_base + offset_array[bank];
264
265 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
266 if (ret)
267 return ret;
268
269 platform_set_drvdata(pdev, chips);
270 ret = davinci_gpio_irq_setup(pdev);
271 if (ret)
272 return ret;
273
274 return 0;
275 }
276
277 /*--------------------------------------------------------------------------*/
278 /*
279 * We expect irqs will normally be set up as input pins, but they can also be
280 * used as output pins ... which is convenient for testing.
281 *
282 * NOTE: The first few GPIOs also have direct INTC hookups in addition
283 * to their GPIOBNK0 irq, with a bit less overhead.
284 *
285 * All those INTC hookups (direct, plus several IRQ banks) can also
286 * serve as EDMA event triggers.
287 */
288
gpio_irq_disable(struct irq_data * d)289 static void gpio_irq_disable(struct irq_data *d)
290 {
291 struct davinci_gpio_regs __iomem *g = irq2regs(d);
292 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
293
294 writel_relaxed(mask, &g->clr_falling);
295 writel_relaxed(mask, &g->clr_rising);
296 }
297
gpio_irq_enable(struct irq_data * d)298 static void gpio_irq_enable(struct irq_data *d)
299 {
300 struct davinci_gpio_regs __iomem *g = irq2regs(d);
301 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
302 unsigned status = irqd_get_trigger_type(d);
303
304 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
305 if (!status)
306 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
307
308 if (status & IRQ_TYPE_EDGE_FALLING)
309 writel_relaxed(mask, &g->set_falling);
310 if (status & IRQ_TYPE_EDGE_RISING)
311 writel_relaxed(mask, &g->set_rising);
312 }
313
gpio_irq_type(struct irq_data * d,unsigned trigger)314 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
315 {
316 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
317 return -EINVAL;
318
319 return 0;
320 }
321
322 static struct irq_chip gpio_irqchip = {
323 .name = "GPIO",
324 .irq_enable = gpio_irq_enable,
325 .irq_disable = gpio_irq_disable,
326 .irq_set_type = gpio_irq_type,
327 .flags = IRQCHIP_SET_TYPE_MASKED,
328 };
329
gpio_irq_handler(struct irq_desc * desc)330 static void gpio_irq_handler(struct irq_desc *desc)
331 {
332 struct davinci_gpio_regs __iomem *g;
333 u32 mask = 0xffff;
334 int bank_num;
335 struct davinci_gpio_controller *d;
336 struct davinci_gpio_irq_data *irqdata;
337
338 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
339 bank_num = irqdata->bank_num;
340 g = irqdata->regs;
341 d = irqdata->chip;
342
343 /* we only care about one bank */
344 if ((bank_num % 2) == 1)
345 mask <<= 16;
346
347 /* temporarily mask (level sensitive) parent IRQ */
348 chained_irq_enter(irq_desc_get_chip(desc), desc);
349 while (1) {
350 u32 status;
351 int bit;
352 irq_hw_number_t hw_irq;
353
354 /* ack any irqs */
355 status = readl_relaxed(&g->intstat) & mask;
356 if (!status)
357 break;
358 writel_relaxed(status, &g->intstat);
359
360 /* now demux them to the right lowlevel handler */
361
362 while (status) {
363 bit = __ffs(status);
364 status &= ~BIT(bit);
365 /* Max number of gpios per controller is 144 so
366 * hw_irq will be in [0..143]
367 */
368 hw_irq = (bank_num / 2) * 32 + bit;
369
370 generic_handle_domain_irq(d->irq_domain, hw_irq);
371 }
372 }
373 chained_irq_exit(irq_desc_get_chip(desc), desc);
374 /* now it may re-trigger */
375 }
376
gpio_to_irq_banked(struct gpio_chip * chip,unsigned offset)377 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
378 {
379 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
380
381 if (d->irq_domain)
382 return irq_create_mapping(d->irq_domain, offset);
383 else
384 return -ENXIO;
385 }
386
gpio_to_irq_unbanked(struct gpio_chip * chip,unsigned offset)387 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
388 {
389 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
390
391 /*
392 * NOTE: we assume for now that only irqs in the first gpio_chip
393 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
394 */
395 if (offset < d->gpio_unbanked)
396 return d->irqs[offset];
397 else
398 return -ENODEV;
399 }
400
gpio_irq_type_unbanked(struct irq_data * data,unsigned trigger)401 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
402 {
403 struct davinci_gpio_controller *d;
404 struct davinci_gpio_regs __iomem *g;
405 u32 mask, i;
406
407 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
408 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
409 for (i = 0; i < MAX_INT_PER_BANK; i++)
410 if (data->irq == d->irqs[i])
411 break;
412
413 if (i == MAX_INT_PER_BANK)
414 return -EINVAL;
415
416 mask = __gpio_mask(i);
417
418 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
419 return -EINVAL;
420
421 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
422 ? &g->set_falling : &g->clr_falling);
423 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
424 ? &g->set_rising : &g->clr_rising);
425
426 return 0;
427 }
428
429 static int
davinci_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)430 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
431 irq_hw_number_t hw)
432 {
433 struct davinci_gpio_controller *chips =
434 (struct davinci_gpio_controller *)d->host_data;
435 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
436
437 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
438 "davinci_gpio");
439 irq_set_irq_type(irq, IRQ_TYPE_NONE);
440 irq_set_chip_data(irq, (__force void *)g);
441 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
442
443 return 0;
444 }
445
446 static const struct irq_domain_ops davinci_gpio_irq_ops = {
447 .map = davinci_gpio_irq_map,
448 .xlate = irq_domain_xlate_onetwocell,
449 };
450
davinci_gpio_get_irq_chip(unsigned int irq)451 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
452 {
453 static struct irq_chip_type gpio_unbanked;
454
455 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
456
457 return &gpio_unbanked.chip;
458 };
459
keystone_gpio_get_irq_chip(unsigned int irq)460 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
461 {
462 static struct irq_chip gpio_unbanked;
463
464 gpio_unbanked = *irq_get_chip(irq);
465 return &gpio_unbanked;
466 };
467
468 static const struct of_device_id davinci_gpio_ids[];
469
470 /*
471 * NOTE: for suspend/resume, probably best to make a platform_device with
472 * suspend_late/resume_resume calls hooking into results of the set_wake()
473 * calls ... so if no gpios are wakeup events the clock can be disabled,
474 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
475 * (dm6446) can be set appropriately for GPIOV33 pins.
476 */
477
davinci_gpio_irq_setup(struct platform_device * pdev)478 static int davinci_gpio_irq_setup(struct platform_device *pdev)
479 {
480 unsigned gpio, bank;
481 int irq;
482 int ret;
483 struct clk *clk;
484 u32 binten = 0;
485 unsigned ngpio;
486 struct device *dev = &pdev->dev;
487 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
488 struct davinci_gpio_platform_data *pdata = dev->platform_data;
489 struct davinci_gpio_regs __iomem *g;
490 struct irq_domain *irq_domain = NULL;
491 const struct of_device_id *match;
492 struct irq_chip *irq_chip;
493 struct davinci_gpio_irq_data *irqdata;
494 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
495
496 /*
497 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
498 */
499 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
500 match = of_match_device(of_match_ptr(davinci_gpio_ids),
501 dev);
502 if (match)
503 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
504
505 ngpio = pdata->ngpio;
506
507 clk = devm_clk_get(dev, "gpio");
508 if (IS_ERR(clk)) {
509 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
510 return PTR_ERR(clk);
511 }
512
513 ret = clk_prepare_enable(clk);
514 if (ret)
515 return ret;
516
517 if (!pdata->gpio_unbanked) {
518 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
519 if (irq < 0) {
520 dev_err(dev, "Couldn't allocate IRQ numbers\n");
521 clk_disable_unprepare(clk);
522 return irq;
523 }
524
525 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
526 &davinci_gpio_irq_ops,
527 chips);
528 if (!irq_domain) {
529 dev_err(dev, "Couldn't register an IRQ domain\n");
530 clk_disable_unprepare(clk);
531 return -ENODEV;
532 }
533 }
534
535 /*
536 * Arrange gpiod_to_irq() support, handling either direct IRQs or
537 * banked IRQs. Having GPIOs in the first GPIO bank use direct
538 * IRQs, while the others use banked IRQs, would need some setup
539 * tweaks to recognize hardware which can do that.
540 */
541 chips->chip.to_irq = gpio_to_irq_banked;
542 chips->irq_domain = irq_domain;
543
544 /*
545 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
546 * controller only handling trigger modes. We currently assume no
547 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
548 */
549 if (pdata->gpio_unbanked) {
550 /* pass "bank 0" GPIO IRQs to AINTC */
551 chips->chip.to_irq = gpio_to_irq_unbanked;
552 chips->gpio_unbanked = pdata->gpio_unbanked;
553 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
554
555 /* AINTC handles mask/unmask; GPIO handles triggering */
556 irq = chips->irqs[0];
557 irq_chip = gpio_get_irq_chip(irq);
558 irq_chip->name = "GPIO-AINTC";
559 irq_chip->irq_set_type = gpio_irq_type_unbanked;
560
561 /* default trigger: both edges */
562 g = chips->regs[0];
563 writel_relaxed(~0, &g->set_falling);
564 writel_relaxed(~0, &g->set_rising);
565
566 /* set the direct IRQs up to use that irqchip */
567 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
568 irq_set_chip(chips->irqs[gpio], irq_chip);
569 irq_set_handler_data(chips->irqs[gpio], chips);
570 irq_set_status_flags(chips->irqs[gpio],
571 IRQ_TYPE_EDGE_BOTH);
572 }
573
574 goto done;
575 }
576
577 /*
578 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
579 * then chain through our own handler.
580 */
581 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
582 /* disabled by default, enabled only as needed
583 * There are register sets for 32 GPIOs. 2 banks of 16
584 * GPIOs are covered by each set of registers hence divide by 2
585 */
586 g = chips->regs[bank / 2];
587 writel_relaxed(~0, &g->clr_falling);
588 writel_relaxed(~0, &g->clr_rising);
589
590 /*
591 * Each chip handles 32 gpios, and each irq bank consists of 16
592 * gpio irqs. Pass the irq bank's corresponding controller to
593 * the chained irq handler.
594 */
595 irqdata = devm_kzalloc(&pdev->dev,
596 sizeof(struct
597 davinci_gpio_irq_data),
598 GFP_KERNEL);
599 if (!irqdata) {
600 clk_disable_unprepare(clk);
601 return -ENOMEM;
602 }
603
604 irqdata->regs = g;
605 irqdata->bank_num = bank;
606 irqdata->chip = chips;
607
608 irq_set_chained_handler_and_data(chips->irqs[bank],
609 gpio_irq_handler, irqdata);
610
611 binten |= BIT(bank);
612 }
613
614 done:
615 /*
616 * BINTEN -- per-bank interrupt enable. genirq would also let these
617 * bits be set/cleared dynamically.
618 */
619 writel_relaxed(binten, gpio_base + BINTEN);
620
621 return 0;
622 }
623
davinci_gpio_save_context(struct davinci_gpio_controller * chips,u32 nbank)624 static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
625 u32 nbank)
626 {
627 struct davinci_gpio_regs __iomem *g;
628 struct davinci_gpio_regs *context;
629 u32 bank;
630 void __iomem *base;
631
632 base = chips->regs[0] - offset_array[0];
633 chips->binten_context = readl_relaxed(base + BINTEN);
634
635 for (bank = 0; bank < nbank; bank++) {
636 g = chips->regs[bank];
637 context = &chips->context[bank];
638 context->dir = readl_relaxed(&g->dir);
639 context->set_data = readl_relaxed(&g->set_data);
640 context->set_rising = readl_relaxed(&g->set_rising);
641 context->set_falling = readl_relaxed(&g->set_falling);
642 }
643
644 /* Clear Bank interrupt enable bit */
645 writel_relaxed(0, base + BINTEN);
646
647 /* Clear all interrupt status registers */
648 writel_relaxed(GENMASK(31, 0), &g->intstat);
649 }
650
davinci_gpio_restore_context(struct davinci_gpio_controller * chips,u32 nbank)651 static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
652 u32 nbank)
653 {
654 struct davinci_gpio_regs __iomem *g;
655 struct davinci_gpio_regs *context;
656 u32 bank;
657 void __iomem *base;
658
659 base = chips->regs[0] - offset_array[0];
660
661 if (readl_relaxed(base + BINTEN) != chips->binten_context)
662 writel_relaxed(chips->binten_context, base + BINTEN);
663
664 for (bank = 0; bank < nbank; bank++) {
665 g = chips->regs[bank];
666 context = &chips->context[bank];
667 if (readl_relaxed(&g->dir) != context->dir)
668 writel_relaxed(context->dir, &g->dir);
669 if (readl_relaxed(&g->set_data) != context->set_data)
670 writel_relaxed(context->set_data, &g->set_data);
671 if (readl_relaxed(&g->set_rising) != context->set_rising)
672 writel_relaxed(context->set_rising, &g->set_rising);
673 if (readl_relaxed(&g->set_falling) != context->set_falling)
674 writel_relaxed(context->set_falling, &g->set_falling);
675 }
676 }
677
davinci_gpio_suspend(struct device * dev)678 static int davinci_gpio_suspend(struct device *dev)
679 {
680 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
681 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
682 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
683
684 davinci_gpio_save_context(chips, nbank);
685
686 return 0;
687 }
688
davinci_gpio_resume(struct device * dev)689 static int davinci_gpio_resume(struct device *dev)
690 {
691 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
692 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
693 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
694
695 davinci_gpio_restore_context(chips, nbank);
696
697 return 0;
698 }
699
700 DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
701 davinci_gpio_resume);
702
703 static const struct of_device_id davinci_gpio_ids[] = {
704 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
705 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
706 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
707 { /* sentinel */ },
708 };
709 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
710
711 static struct platform_driver davinci_gpio_driver = {
712 .probe = davinci_gpio_probe,
713 .driver = {
714 .name = "davinci_gpio",
715 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
716 .of_match_table = of_match_ptr(davinci_gpio_ids),
717 },
718 };
719
720 /**
721 * GPIO driver registration needs to be done before machine_init functions
722 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
723 */
davinci_gpio_drv_reg(void)724 static int __init davinci_gpio_drv_reg(void)
725 {
726 return platform_driver_register(&davinci_gpio_driver);
727 }
728 postcore_initcall(davinci_gpio_drv_reg);
729
davinci_gpio_exit(void)730 static void __exit davinci_gpio_exit(void)
731 {
732 platform_driver_unregister(&davinci_gpio_driver);
733 }
734 module_exit(davinci_gpio_exit);
735
736 MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
737 MODULE_DESCRIPTION("DAVINCI GPIO driver");
738 MODULE_LICENSE("GPL");
739 MODULE_ALIAS("platform:gpio-davinci");
740