1 #ifndef __HAL_SDIO_H__ 2 #define __HAL_SDIO_H__ 3 4 #define SDIO_MAX_FUNCTIONS 4 5 6 /* SDIO commands type argument response */ 7 #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */ 8 #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */ 9 #define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */ 10 11 /* CMD52 arguments */ 12 #define SDIO_ARG_CMD52_READ (0<<31) 13 #define SDIO_ARG_CMD52_WRITE (1u<<31) 14 #define SDIO_ARG_CMD52_FUNC_SHIFT 28 15 #define SDIO_ARG_CMD52_FUNC_MASK 0x7 16 #define SDIO_ARG_CMD52_RAW_FLAG (1u<<27) 17 #define SDIO_ARG_CMD52_REG_SHIFT 9 18 #define SDIO_ARG_CMD52_REG_MASK 0x1ffff 19 #define SDIO_ARG_CMD52_DATA_SHIFT 0 20 #define SDIO_ARG_CMD52_DATA_MASK 0xff 21 #define SDIO_R5_DATA(resp) ((resp)[0] & 0xff) 22 23 /* CMD53 arguments */ 24 #define SDIO_ARG_CMD53_READ (0<<31) 25 #define SDIO_ARG_CMD53_WRITE (1u<<31) 26 #define SDIO_ARG_CMD53_FUNC_SHIFT 28 27 #define SDIO_ARG_CMD53_FUNC_MASK 0x7 28 #define SDIO_ARG_CMD53_BLOCK_MODE (1u<<27) 29 #define SDIO_ARG_CMD53_INCREMENT (1u<<26) 30 #define SDIO_ARG_CMD53_REG_SHIFT 9 31 #define SDIO_ARG_CMD53_REG_MASK 0x1ffff 32 #define SDIO_ARG_CMD53_LENGTH_SHIFT 0 33 #define SDIO_ARG_CMD53_LENGTH_MASK 0x1ff 34 #define SDIO_ARG_CMD53_LENGTH_MAX 511 35 36 /* R5 response bits */ 37 #define R5_COM_CRC_ERROR (1 << 15) 38 #define R5_ILLEGAL_COMMAND (1 << 14) 39 #define R5_ERROR (1 << 11) 40 #define R5_FUNCTION_NUMBER (1 << 9) 41 #define R5_OUT_OF_RANGE (1 << 8) 42 #define R5_STATUS(x) (x & 0xCB00) 43 #define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) 44 45 /* 46 * Card Common Control Registers (CCCR) 47 */ 48 49 #define SDIO_REG_CCCR_CCCR_REV 0x00 50 51 #define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */ 52 #define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */ 53 #define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */ 54 55 #define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */ 56 #define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */ 57 #define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */ 58 #define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */ 59 60 #define SDIO_REG_CCCR_SD_REV 0x01 61 62 #define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */ 63 #define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */ 64 #define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */ 65 66 #define SDIO_REG_CCCR_IO_EN 0x02 67 #define SDIO_REG_CCCR_IO_RDY 0x03 68 69 #define SDIO_REG_CCCR_INT_EN 0x04 /* Function/Master Interrupt Enable */ 70 #define SDIO_REG_CCCR_INT_PEND 0x05 /* Function Interrupt Pending */ 71 72 #define SDIO_REG_CCCR_IO_ABORT 0x06 /* function abort/card reset */ 73 74 #define SDIO_REG_CCCR_BUS_IF 0x07 /* bus interface controls */ 75 76 #define SDIO_BUS_WIDTH_1BIT 0x00 77 #define SDIO_BUS_WIDTH_4BIT 0x02 78 #define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */ 79 #define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */ 80 81 #define SDIO_BUS_ASYNC_INT 0x20 82 83 #define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */ 84 85 #define SDIO_REG_CCCR_CARD_CAPS 0x08 86 87 #define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */ 88 #define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */ 89 #define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */ 90 #define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */ 91 #define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */ 92 #define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */ 93 #define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */ 94 #define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */ 95 96 #define SDIO_REG_CCCR_CIS_PTR 0x09 /* common CIS pointer (3 bytes) */ 97 98 /* Following 4 regs are valid only if SBS is set */ 99 #define SDIO_REG_CCCR_BUS_SUSPEND 0x0c 100 #define SDIO_REG_CCCR_FUNC_SEL 0x0d 101 #define SDIO_REG_CCCR_EXEC_FLAG 0x0e 102 #define SDIO_REG_CCCR_READY_FLAG 0x0f 103 104 #define SDIO_REG_CCCR_FN0_BLKSIZE 0x10 /* 2bytes, 0x10~0x11 */ 105 106 #define SDIO_REG_CCCR_POWER_CTRL 0x12 107 108 #define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */ 109 #define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */ 110 111 #define SDIO_REG_CCCR_SPEED 0x13 112 113 #define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */ 114 #define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */ 115 116 /* 117 * Function Basic Registers (FBR) 118 */ 119 120 #define SDIO_REG_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */ 121 122 #define SDIO_REG_FBR_STD_FUNC_IF 0x00 123 124 #define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */ 125 #define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */ 126 127 #define SDIO_REG_FBR_STD_IF_EXT 0x01 128 129 #define SDIO_REG_FBR_POWER 0x02 130 131 #define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */ 132 #define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */ 133 134 #define SDIO_REG_FBR_CIS 0x09 /* CIS pointer (3 bytes) */ 135 136 137 #define SDIO_REG_FBR_CSA 0x0C /* CSA pointer (3 bytes) */ 138 139 #define SDIO_REG_FBR_CSA_DATA 0x0F 140 141 #define SDIO_REG_FBR_BLKSIZE 0x10 /* block size (2 bytes) */ 142 143 /* SDIO CIS Tuple code */ 144 #define CISTPL_NULL 0x00 145 #define CISTPL_CHECKSUM 0x10 146 #define CISTPL_VERS_1 0x15 147 #define CISTPL_ALTSTR 0x16 148 #define CISTPL_MANFID 0x20 149 #define CISTPL_FUNCID 0x21 150 #define CISTPL_FUNCE 0x22 151 #define CISTPL_SDIO_STD 0x91 152 #define CISTPL_SDIO_EXT 0x92 153 #define CISTPL_END 0xff 154 155 /* SDIO device id */ 156 #define SDIO_ANY_FUNC_ID 0xff 157 #define SDIO_ANY_MAN_ID 0xffff 158 #define SDIO_ANY_PROD_ID 0xffff 159 160 struct sdio_device_id 161 { 162 uint8_t func_code; 163 uint16_t manufacturer; 164 uint16_t product; 165 }; 166 167 struct sdio_cccr { 168 uint8_t sdio_version; 169 uint8_t sd_version; 170 uint8_t direct_cmd:1, /* Card Supports Direct Commands during data transfer 171 only SD mode, not used for SPI mode */ 172 multi_block:1, /* Card Supports Multi-Block */ 173 read_wait:1, /* Card Supports Read Wait 174 only SD mode, not used for SPI mode */ 175 suspend_resume:1, /* Card supports Suspend/Resume 176 only SD mode, not used for SPI mode */ 177 s4mi:1, /* generate interrupts during a 4-bit 178 multi-block data transfer */ 179 e4mi:1, /* Enable the multi-block IRQ during 180 4-bit transfer for the SDIO card */ 181 low_speed:1, /* Card is a Low-Speed card */ 182 low_speed_4:1; /* 4-bit support for Low-Speed cards */ 183 184 uint8_t bus_width:1, /* Support SDIO bus width, 1:4bit, 0:1bit */ 185 cd_disable:1, /* Connect[0]/Disconnect[1] the 10K-90K ohm pull-up 186 resistor on CD/DAT[3] (pin 1) of the card */ 187 power_ctrl:1, /* Support Master Power Control */ 188 high_speed:1; /* Support High-Speed */ 189 }; 190 191 struct sdio_cis { 192 uint16_t manufacturer; 193 uint16_t product; 194 uint16_t func0_blk_size; 195 uint32_t max_tran_speed; 196 }; 197 198 /* 199 * SDIO function CIS tuple (unknown to the core) 200 */ 201 struct sdio_function_tuple { 202 struct sdio_function_tuple *next; 203 uint8_t code; 204 uint8_t size; 205 uint8_t *data; 206 }; 207 struct sdio_function; 208 typedef void (*sdio_irq_handler_t)(struct sdio_function *); 209 210 struct mmc; 211 /* 212 * SDIO function devices 213 */ 214 struct sdio_function { 215 struct mmc *mmc; /* the card this device belongs to */ 216 void* dev; /* the device */ 217 sdio_irq_handler_t irq_handler; /* IRQ callback */ 218 uint8_t num; /* function number */ 219 220 uint8_t func_code; /* Standard SDIO Function interface code */ 221 uint16_t manufacturer; /* manufacturer id */ 222 uint16_t product; /* product id */ 223 224 uint32_t max_blk_size; /* maximum block size */ 225 uint32_t cur_blk_size; /* current block size */ 226 227 uint32_t enable_timeout_val; /* max enable timeout in msec */ 228 229 uint32_t buf_id_tx; 230 int buf_id_rx; /* byte */ 231 uint32_t hw_type; 232 uint32_t transq_pri; 233 uint8_t transq_irq_count; 234 uint8_t wsm_startup_done; 235 void* priv; 236 }; 237 #define sdio_func sdio_function 238 int32_t sdio_io_send_op_cond(struct mmc *mmc, uint32_t ocr, 239 uint32_t *cmd5_resp); 240 int32_t sdio_io_rw_direct(struct mmc *mmc, 241 int32_t rw, 242 uint32_t fn, 243 uint32_t reg_addr, 244 uint8_t *pdata, 245 uint8_t raw); 246 int32_t sdio_io_rw_extended(struct mmc *mmc, 247 int32_t rw, 248 uint32_t fn, 249 uint32_t addr, 250 int32_t op_code, 251 uint8_t *buf, 252 uint32_t blocks, 253 uint32_t blksize); 254 uint8_t sdio_io_readb(struct sdio_function *func, 255 uint32_t reg, 256 int32_t *err); 257 int32_t sdio_io_writeb(struct sdio_function *func, 258 uint32_t reg, 259 uint8_t data); 260 uint16_t sdio_io_readw(struct sdio_function *func, 261 uint32_t addr, 262 int32_t *err); 263 int32_t sdio_io_writew(struct sdio_function *func, 264 uint16_t data, 265 uint32_t addr); 266 uint32_t sdio_io_readl(struct sdio_function *func, 267 uint32_t addr, 268 int32_t *err); 269 int32_t sdio_io_writel(struct sdio_function *func, 270 uint32_t data, 271 uint32_t addr); 272 int32_t sdio_io_read_block(struct sdio_function *func, 273 uint32_t addr, 274 uint8_t *buf, 275 uint32_t len); 276 int32_t sdio_io_write_block(struct sdio_function *func, 277 uint32_t addr, 278 uint8_t *buf, 279 uint32_t len); 280 281 unsigned int sdio_align_size(struct sdio_function *func, unsigned int sz); 282 int32_t sdio_attach_irq(struct sdio_function *func, 283 sdio_irq_handler_t handler); 284 int32_t sdio_detach_irq(struct sdio_function *func); 285 int32_t sdio_enable_func(struct sdio_function *func); 286 int32_t sdio_disable_func(struct sdio_function *func); 287 int32_t sdio_set_block_size(struct sdio_function *func, 288 uint32_t blksize); 289 uint32_t mmc_detect_sdio(struct mmc *mmc); 290 void hal_sdio_enable_irq(struct sdio_function *func); 291 void hal_sdio_disable_irq(struct sdio_function *func); 292 void hal_sdio_check_irq(struct sdio_function *func); 293 #endif 294 295