1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9
10conn_subsys: bus@5b000000 {
11	compatible = "simple-bus";
12	#address-cells = <1>;
13	#size-cells = <1>;
14	ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
15
16	conn_axi_clk: clock-conn-axi {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		clock-frequency = <333333333>;
20		clock-output-names = "conn_axi_clk";
21	};
22
23	conn_ahb_clk: clock-conn-ahb {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		clock-frequency = <166666666>;
27		clock-output-names = "conn_ahb_clk";
28	};
29
30	conn_ipg_clk: clock-conn-ipg {
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <83333333>;
34		clock-output-names = "conn_ipg_clk";
35	};
36
37	usbotg1: usb@5b0d0000 {
38		compatible = "fsl,imx7ulp-usb";
39		reg = <0x5b0d0000 0x200>;
40		interrupt-parent = <&gic>;
41		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
42		fsl,usbphy = <&usbphy1>;
43		fsl,usbmisc = <&usbmisc1 0>;
44		clocks = <&usb2_lpcg 0>;
45		ahb-burst-config = <0x0>;
46		tx-burst-size-dword = <0x10>;
47		rx-burst-size-dword = <0x10>;
48		power-domains = <&pd IMX_SC_R_USB_0>;
49		status = "disabled";
50	};
51
52	usbmisc1: usbmisc@5b0d0200 {
53		#index-cells = <1>;
54		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
55		reg = <0x5b0d0200 0x200>;
56	};
57
58	usbphy1: usbphy@5b100000 {
59		compatible = "fsl,imx7ulp-usbphy";
60		reg = <0x5b100000 0x1000>;
61		clocks = <&usb2_lpcg 1>;
62		power-domains = <&pd IMX_SC_R_USB_0_PHY>;
63		status = "disabled";
64	};
65
66	usdhc1: mmc@5b010000 {
67		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
68		reg = <0x5b010000 0x10000>;
69		clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
70			 <&sdhc0_lpcg IMX_LPCG_CLK_0>,
71			 <&sdhc0_lpcg IMX_LPCG_CLK_5>;
72		clock-names = "ipg", "ahb", "per";
73		power-domains = <&pd IMX_SC_R_SDHC_0>;
74		status = "disabled";
75	};
76
77	usdhc2: mmc@5b020000 {
78		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
79		reg = <0x5b020000 0x10000>;
80		clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
81			 <&sdhc1_lpcg IMX_LPCG_CLK_0>,
82			 <&sdhc1_lpcg IMX_LPCG_CLK_5>;
83		clock-names = "ipg", "ahb", "per";
84		power-domains = <&pd IMX_SC_R_SDHC_1>;
85		fsl,tuning-start-tap = <20>;
86		fsl,tuning-step = <2>;
87		status = "disabled";
88	};
89
90	usdhc3: mmc@5b030000 {
91		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
92		reg = <0x5b030000 0x10000>;
93		clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
94			 <&sdhc2_lpcg IMX_LPCG_CLK_0>,
95			 <&sdhc2_lpcg IMX_LPCG_CLK_5>;
96		clock-names = "ipg", "ahb", "per";
97		power-domains = <&pd IMX_SC_R_SDHC_2>;
98		status = "disabled";
99	};
100
101	fec1: ethernet@5b040000 {
102		reg = <0x5b040000 0x10000>;
103		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
104			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
105			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
106			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
107		clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
108			 <&enet0_lpcg IMX_LPCG_CLK_2>,
109			 <&enet0_lpcg IMX_LPCG_CLK_3>,
110			 <&enet0_lpcg IMX_LPCG_CLK_0>;
111		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
112		assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
113				  <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
114		assigned-clock-rates = <250000000>, <125000000>;
115		fsl,num-tx-queues = <3>;
116		fsl,num-rx-queues = <3>;
117		power-domains = <&pd IMX_SC_R_ENET_0>;
118		status = "disabled";
119	};
120
121	fec2: ethernet@5b050000 {
122		reg = <0x5b050000 0x10000>;
123		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
124				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
125				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
126				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
127		clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
128			 <&enet1_lpcg IMX_LPCG_CLK_2>,
129			 <&enet1_lpcg IMX_LPCG_CLK_3>,
130			 <&enet1_lpcg IMX_LPCG_CLK_0>;
131		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
132		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
133				  <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
134		assigned-clock-rates = <250000000>, <125000000>;
135		fsl,num-tx-queues = <3>;
136		fsl,num-rx-queues = <3>;
137		power-domains = <&pd IMX_SC_R_ENET_1>;
138		status = "disabled";
139	};
140
141	/* LPCG clocks */
142	sdhc0_lpcg: clock-controller@5b200000 {
143		compatible = "fsl,imx8qxp-lpcg";
144		reg = <0x5b200000 0x10000>;
145		#clock-cells = <1>;
146		clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
147			 <&conn_ipg_clk>, <&conn_axi_clk>;
148		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
149				<IMX_LPCG_CLK_5>;
150		clock-output-names = "sdhc0_lpcg_per_clk",
151				     "sdhc0_lpcg_ipg_clk",
152				     "sdhc0_lpcg_ahb_clk";
153		power-domains = <&pd IMX_SC_R_SDHC_0>;
154	};
155
156	sdhc1_lpcg: clock-controller@5b210000 {
157		compatible = "fsl,imx8qxp-lpcg";
158		reg = <0x5b210000 0x10000>;
159		#clock-cells = <1>;
160		clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
161			 <&conn_ipg_clk>, <&conn_axi_clk>;
162		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
163				<IMX_LPCG_CLK_5>;
164		clock-output-names = "sdhc1_lpcg_per_clk",
165				     "sdhc1_lpcg_ipg_clk",
166				     "sdhc1_lpcg_ahb_clk";
167		power-domains = <&pd IMX_SC_R_SDHC_1>;
168	};
169
170	sdhc2_lpcg: clock-controller@5b220000 {
171		compatible = "fsl,imx8qxp-lpcg";
172		reg = <0x5b220000 0x10000>;
173		#clock-cells = <1>;
174		clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
175			 <&conn_ipg_clk>, <&conn_axi_clk>;
176		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
177				<IMX_LPCG_CLK_5>;
178		clock-output-names = "sdhc2_lpcg_per_clk",
179				     "sdhc2_lpcg_ipg_clk",
180				     "sdhc2_lpcg_ahb_clk";
181		power-domains = <&pd IMX_SC_R_SDHC_2>;
182	};
183
184	enet0_lpcg: clock-controller@5b230000 {
185		compatible = "fsl,imx8qxp-lpcg";
186		reg = <0x5b230000 0x10000>;
187		#clock-cells = <1>;
188		clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
189			 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
190			 <&conn_axi_clk>,
191			 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
192			 <&conn_ipg_clk>,
193			 <&conn_ipg_clk>;
194		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
195				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
196				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
197		clock-output-names = "enet0_lpcg_timer_clk",
198				     "enet0_lpcg_txc_sampling_clk",
199				     "enet0_lpcg_ahb_clk",
200				     "enet0_lpcg_rgmii_txc_clk",
201				     "enet0_lpcg_ipg_clk",
202				     "enet0_lpcg_ipg_s_clk";
203		power-domains = <&pd IMX_SC_R_ENET_0>;
204	};
205
206	enet1_lpcg: clock-controller@5b240000 {
207		compatible = "fsl,imx8qxp-lpcg";
208		reg = <0x5b240000 0x10000>;
209		#clock-cells = <1>;
210		clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
211			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
212			 <&conn_axi_clk>,
213			 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
214			 <&conn_ipg_clk>,
215			 <&conn_ipg_clk>;
216		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
217				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
218				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
219		clock-output-names = "enet1_lpcg_timer_clk",
220				     "enet1_lpcg_txc_sampling_clk",
221				     "enet1_lpcg_ahb_clk",
222				     "enet1_lpcg_rgmii_txc_clk",
223				     "enet1_lpcg_ipg_clk",
224				     "enet1_lpcg_ipg_s_clk";
225		power-domains = <&pd IMX_SC_R_ENET_1>;
226	};
227
228	usb2_lpcg: clock-controller@5b270000 {
229		compatible = "fsl,imx8qxp-lpcg";
230		reg = <0x5b270000 0x10000>;
231		#clock-cells = <1>;
232		clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
233		clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
234		clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
235		power-domains = <&pd IMX_SC_R_USB_0_PHY>;
236	};
237};
238