1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Memory map for the Juno product. 9 */ 10 11 #ifndef JUNO_MMAP_H 12 #define JUNO_MMAP_H 13 14 #include "system_mmap.h" 15 16 #include <stdint.h> 17 18 #define I2C_BASE (VENDOR_EXTENSION_BASE + 0x00000000) 19 #define PVT_AON_BASE (VENDOR_EXTENSION_BASE + 0x00001000) 20 #define SCC_BASE (VENDOR_EXTENSION_BASE + 0x1FEFF000) 21 22 #define V2M_SYS_REG_BASE (EXTERNAL_DEV_BASE + 0x1C010000) 23 #define SENSOR_CALIBRATION_BASE (EXTERNAL_DEV_BASE + 0x1C010130) 24 #define FPGA_UART1_BASE (EXTERNAL_DEV_BASE + 0x1C0A0000) 25 #define NIC400_GPV_CCI_PCIE_BASE (EXTERNAL_DEV_BASE + 0x2C091000) 26 #define NIC400_GPV_CCI_GPU_BASE (EXTERNAL_DEV_BASE + 0x2C093000) 27 #define NIC400_GPV_CCI_LITTLE_BASE (EXTERNAL_DEV_BASE + 0x2C094000) 28 #define NIC400_GPV_CCI_BIG_BASE (EXTERNAL_DEV_BASE + 0x2C095000) 29 #define NIC400_BASE (EXTERNAL_RAM_BASE + 0x3FD00000) 30 #define NIC400_GPV_HDLCD0_BASE (EXTERNAL_RAM_BASE + 0x3FD44000) 31 #define NIC400_GPV_HDLCD1_BASE (EXTERNAL_RAM_BASE + 0x3FD45000) 32 #define PVT_STDCELL_BASE (EXTERNAL_RAM_BASE + 0x3FE00000) 33 #define PVT_SOC_BASE (EXTERNAL_RAM_BASE + 0x3FE10000) 34 #define PVT_GPU_BASE (EXTERNAL_RAM_BASE + 0x3FE20000) 35 #define PVT_BIG_BASE (EXTERNAL_RAM_BASE + 0x3FE30000) 36 #define PVT_LITTLE_BASE (EXTERNAL_RAM_BASE + 0x3FE40000) 37 #define DDR_PHY1_BASE (EXTERNAL_RAM_BASE + 0x3FEE0000) 38 #define DDR_PHY0_BASE (EXTERNAL_RAM_BASE + 0x3FEF0000) 39 #define PCIE_CONTROLLER_BASE (EXTERNAL_RAM_BASE + 0x3FF20000) 40 #define PCIE_ROOT_PORT_BASE (EXTERNAL_RAM_BASE + 0x3FF30000) 41 #define UART1_BASE (EXTERNAL_RAM_BASE + 0x3FF70000) 42 #define SMC_BASE (EXTERNAL_RAM_BASE + 0x3FFD0000) 43 44 #define NOR_BASE (EXTERNAL_DEV_BASE + 0x08000000) 45 #define HDLCD_PRESET_TABLE_BASE (NOR_BASE + 0x025C0000) 46 47 #endif /* JUNO_MMAP_H */ 48