1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Juno System Configuration Controller (SCC) register definitions. 9 */ 10 11 #ifndef JUNO_SCC_H 12 #define JUNO_SCC_H 13 14 #include "juno_mmap.h" 15 16 #include <fwk_macros.h> 17 18 #include <stdint.h> 19 20 enum pll_idx { 21 PLL_IDX_BIG, 22 PLL_IDX_LITTLE, 23 PLL_IDX_GPU, 24 PLL_IDX_SYS, 25 PLL_IDX_HDLCD, 26 PLL_IDX_COUNT, 27 }; 28 29 struct pll_reg { 30 FWK_RW uint32_t REG0; 31 FWK_RW uint32_t REG1; 32 }; 33 34 #define PLL_REG0_HARD_BYPASS UINT32_C(0x00000001) 35 #define PLL_REG0_RST_TIMER_BYPASS UINT32_C(0x00000002) 36 #define PLL_REG0_FORCE_LOCK UINT32_C(0x00000010) 37 #define PLL_REG0_PWRDN UINT32_C(0x00000100) 38 #define PLL_REG0_BYPASS UINT32_C(0x00000200) 39 #define PLL_REG0_TEST UINT32_C(0x00000400) 40 #define PLL_REG0_FASTEN UINT32_C(0x00000800) 41 #define PLL_REG0_ENSAT UINT32_C(0x00001000) 42 #define PLL_REG0_CLKF UINT32_C(0x1FFF0000) 43 #define PLL_REG0_PLL_RESET UINT32_C(0x80000000) 44 #define PLL_REG0_ENSAT_POS 12 45 #define PLL_REG0_NF_POS 16 46 #define PLL_REG0_NF UINT32_C(0x1FFF0000) 47 48 #define PLL_REG1_NR_POS 0 49 #define PLL_REG1_OD_POS 8 50 #define PLL_REG1_NB_POS 12 51 #define PLL_REG1_NR UINT32_C(0x0000003F) 52 #define PLL_REG1_OD UINT32_C(0x00000F00) 53 #define PLL_REG1_NB UINT32_C(0x00FFF000) 54 #define PLL_REG1_CLKR UINT32_C(0x0000003F) 55 #define PLL_REG1_CLKOD UINT32_C(0x00000F00) 56 #define PLL_REG1_BWADJ UINT32_C(0x00FFF000) 57 #define PLL_REG1_LOCK_STATUS UINT32_C(0x80000000) 58 59 #define PLL_NF_MAX UINT16_C(4096) 60 #define PLL_NR_MAX UINT8_C(64) 61 #define PLL_OD_MAX UINT8_C(16) 62 63 enum pcsm_idx { 64 PCSM_IDX_BIG_0, 65 PCSM_IDX_BIG_1, 66 PCSM_IDX_BIG_SCU, 67 PCSM_IDX_LITTLE_0, 68 PCSM_IDX_LITTLE_1, 69 PCSM_IDX_LITTLE_2, 70 PCSM_IDX_LITTLE_3, 71 PCSM_IDX_LITTLE_SCU, 72 PCSM_IDX_COUNT, 73 }; 74 75 struct pcsm_reg { 76 uint32_t RESERVED1; 77 FWK_RW uint32_t TRICKLE_DELAY; 78 FWK_RW uint32_t HAMMER_DELAY; 79 FWK_RW uint32_t RAM_DELAY; 80 uint8_t RESERVED2[0x100 - 0x10]; 81 }; 82 83 struct scc_reg { 84 FWK_RW uint32_t FAXICLK; 85 FWK_RW uint32_t SAXICLK; 86 FWK_RW uint32_t HDLCDCLK; 87 FWK_RW uint32_t TMIF2XCLK; 88 FWK_RW uint32_t TSIF2XCLK; 89 FWK_RW uint32_t USBHCLK; 90 FWK_RW uint32_t PCIEACLK; 91 FWK_RW uint32_t PCIETLCLK; 92 FWK_RW uint32_t RESERVED1; 93 FWK_RW uint32_t PXLCLK; 94 uint8_t RESERVED2[0x30 - 0x28]; 95 FWK_RW uint32_t SYSTEM_CLK_FORCE; 96 FWK_RW uint32_t VSYS_MANUAL_RESET; 97 uint8_t RESERVED3[0x40 - 0x38]; 98 FWK_RW uint32_t SMC_MASK[4]; 99 FWK_RW uint32_t NIC400_TLX; 100 FWK_RW uint32_t DMA_CONTROL0; 101 uint8_t RESERVED4[0x68 - 0x58]; 102 FWK_RW uint32_t HDLCD0_CONTROL; 103 FWK_RW uint32_t HDLCD1_CONTROL; 104 uint8_t RESERVED5[0xF0 - 0x70]; 105 FWK_R uint32_t GPR0; 106 FWK_R uint32_t GPR1; 107 FWK_R uint32_t APP_ALT_BOOT; 108 FWK_R uint32_t SCP_ALT_BOOT; 109 struct pll_reg PLL[PLL_IDX_COUNT]; 110 FWK_RW uint32_t DDR_PHY0_PLL; 111 FWK_RW uint32_t DDR_PHY1_PLL; 112 uint8_t RESERVED6[0x200 - 0x130]; 113 struct pcsm_reg PCSM[PCSM_IDX_COUNT]; 114 uint8_t RESERVED7[0xA04 - 0xA00]; 115 FWK_RW uint32_t DDR_PHY0_RETNCTRL; 116 FWK_RW uint32_t DDR_PHY1_RETNCTRL; 117 uint8_t RESERVED8[0x1000 - 0xA0C]; 118 }; 119 120 #define SCC ((struct scc_reg *) SCC_BASE) 121 122 #define SCC_TLX_MST_ENABLE UINT32_C(0x00000001) 123 #define SCC_TLX_SLV_PWRDNREQ UINT32_C(0x00000002) 124 #define SCC_TLX_SLV_PWRDNACK UINT32_C(0x00000004) 125 #define SCC_TLX_MST_PWRDNREQ UINT32_C(0x00000008) 126 #define SCC_TLX_MST_PWRDNACK UINT32_C(0x00000010) 127 128 #define SCC_HDLCD_CONTROL_PXLCLK_SEL UINT32_C(0x00000001) 129 #define SCC_HDLCD_CONTROL_PXLCLK_SEL_PLL UINT32_C(0x00000000) 130 #define SCC_HDLCD_CONTROL_PXLCLK_SEL_CLKIN UINT32_C(0x00000001) 131 132 #define SCC_PXLCLK_CLKSEL_PLL UINT32_C(0x00000002) 133 134 #define SCC_GPR0_SKIP_TLX_CLK_SETTING UINT32_C(0x00400000) 135 #define SCC_GPR0_PCIE_AP_MANAGED UINT32_C(0x00800000) 136 #define SCC_GPR0_PLATFORM_ID_PLAT UINT32_C(0x0F000000) 137 #define SCC_GPR0_PLATFORM_ID_PLAT_POS 24 138 #define SCC_GPR0_DVFS_DISABLE UINT32_C(0x10000000) 139 #define SCC_GPR0_HIGH_PXLCLK_ENABLE UINT32_C(0x20000000) 140 #define SCC_GPR0_DDR_DISABLE UINT32_C(0x40000000) 141 #define SCC_GPR0_CALIBRATION_ENABLE UINT32_C(0x80000000) 142 #define SCC_GPR1_CRYPTO_DISABLE UINT32_C(0x00000001) 143 #define SCC_GPR1_CFGTE UINT32_C(0x00000002) 144 #define SCC_GPR1_CFGEE UINT32_C(0x00000004) 145 #define SCC_GPR1_BOOT_MAP_ENABLE UINT32_C(0x00000008) 146 #define SCC_GPR1_BOOT_MAP UINT32_C(0x00000FF0) 147 #define SCC_GPR1_BOOT_MAP_LITTLE UINT32_C(0x000000F0) 148 #define SCC_GPR1_BOOT_MAP_LITTLE_POS 4 149 #define SCC_GPR1_BOOT_MAP_LITTLE_0 UINT32_C(0x00000010) 150 #define SCC_GPR1_BOOT_MAP_LITTLE_1 UINT32_C(0x00000020) 151 #define SCC_GPR1_BOOT_MAP_LITTLE_2 UINT32_C(0x00000040) 152 #define SCC_GPR1_BOOT_MAP_LITTLE_3 UINT32_C(0x00000080) 153 #define SCC_GPR1_BOOT_MAP_BIG UINT32_C(0x00000300) 154 #define SCC_GPR1_BOOT_MAP_BIG_POS 8 155 #define SCC_GPR1_BOOT_MAP_BIG_0 UINT32_C(0x00000100) 156 #define SCC_GPR1_BOOT_MAP_BIG_1 UINT32_C(0x00000200) 157 #define SCC_GPR1_PRIMARY_CPU UINT32_C(0x0000F000) 158 #define SCC_GPR1_PRIMARY_CPU_POS 12 159 #define SCC_GPR1_RESET UINT32_C(0x00030000) 160 #define SCC_GPR1_RESET_POWERON UINT32_C(0x00000000) 161 #define SCC_GPR1_RESET_REBOOT UINT32_C(0x00010000) 162 #define SCC_GPR1_RESET_WDOG UINT32_C(0x00020000) 163 164 #define SCC_APP_ALT_BOOT_ADDR UINT32_C(0xFFFFFFFC) 165 166 #define SCC_DDR_PHY_RETNCTRL_ENABLE UINT32_C(0x00000001) 167 #define SCC_DDR_PHY_RETNCTRL_DISABLE UINT32_C(0x00000000) 168 169 #define SCC_DDR_PHY_PLL_BYPASS_EN UINT32_C(0x00000001) 170 #define SCC_DDR_PHY_PLL_RANGE UINT32_C(0x00000002) 171 #define SCC_DDR_PHY_PLL_REF_DIV UINT32_C(0x00000F00) 172 #define SCC_DDR_PHY_PLL_FBK_DIV UINT32_C(0x0000F000) 173 174 #define SCC_SYSTEM_CLK_FORCE_FAXICLK UINT32_C(0x00000001) 175 #define SCC_SYSTEM_CLK_FORCE_SAXICLK UINT32_C(0x00000002) 176 #define SCC_SYSTEM_CLK_FORCE_HDLCDCLK UINT32_C(0x00000004) 177 178 #define SCC_PCLKDBG_CONTROL_CLKDIV UINT32_C(0x0000000F) 179 180 #define SCC_SYSTEM_CLK_EN_FAXICLKEN UINT32_C(0x00000001) 181 #define SCC_SYSTEM_CLK_EN_SAXICLKEN UINT32_C(0x00000002) 182 #define SCC_SYSTEM_CLK_EN_HDLCDCLKEN UINT32_C(0x00000004) 183 #define SCC_SYSTEM_CLK_EN_TMIF2XCLKEN UINT32_C(0x00000008) 184 #define SCC_SYSTEM_CLK_EN_TSIF2XCLKEN UINT32_C(0x00000010) 185 #define SCC_SYSTEM_CLK_EN_USBHCLKEN UINT32_C(0x00000020) 186 #define SCC_SYSTEM_CLK_EN_PICEACCLKEN UINT32_C(0x00000040) 187 #define SCC_SYSTEM_CLK_EN_PICETLCLKEN UINT32_C(0x00000080) 188 #endif /* JUNO_SCC_H */ 189