1/* 2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18 /* -------------------------------------------------- 19 * Errata Workaround for Cortex A75 Errata #764081. 20 * This applies only to revision r0p0 of Cortex A75. 21 * Inputs: 22 * x0: variant[4:7] and revision[0:3] of current cpu. 23 * Shall clobber: x0-x17 24 * -------------------------------------------------- 25 */ 26func errata_a75_764081_wa 27 /* 28 * Compare x0 against revision r0p0 29 */ 30 mov x17, x30 31 bl check_errata_764081 32 cbz x0, 1f 33 mrs x1, sctlr_el3 34 orr x1, x1 ,#SCTLR_IESB_BIT 35 msr sctlr_el3, x1 36 isb 371: 38 ret x17 39endfunc errata_a75_764081_wa 40 41func check_errata_764081 42 mov x1, #0x00 43 b cpu_rev_var_ls 44endfunc check_errata_764081 45 46 /* -------------------------------------------------- 47 * Errata Workaround for Cortex A75 Errata #790748. 48 * This applies only to revision r0p0 of Cortex A75. 49 * Inputs: 50 * x0: variant[4:7] and revision[0:3] of current cpu. 51 * Shall clobber: x0-x17 52 * -------------------------------------------------- 53 */ 54func errata_a75_790748_wa 55 /* 56 * Compare x0 against revision r0p0 57 */ 58 mov x17, x30 59 bl check_errata_790748 60 cbz x0, 1f 61 mrs x1, CORTEX_A75_CPUACTLR_EL1 62 orr x1, x1 ,#(1 << 13) 63 msr CORTEX_A75_CPUACTLR_EL1, x1 64 isb 651: 66 ret x17 67endfunc errata_a75_790748_wa 68 69func check_errata_790748 70 mov x1, #0x00 71 b cpu_rev_var_ls 72endfunc check_errata_790748 73 74 /* ------------------------------------------------- 75 * The CPU Ops reset function for Cortex-A75. 76 * ------------------------------------------------- 77 */ 78func cortex_a75_reset_func 79 mov x19, x30 80 bl cpu_get_rev_var 81 mov x18, x0 82 83#if ERRATA_A75_764081 84 mov x0, x18 85 bl errata_a75_764081_wa 86#endif 87 88#if ERRATA_A75_790748 89 mov x0, x18 90 bl errata_a75_790748_wa 91#endif 92 93#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) 94 cpu_check_csv2 x0, 1f 95 adr x0, wa_cve_2017_5715_bpiall_vbar 96 msr vbar_el3, x0 97 isb 98 /* Skip installing vector table again for CVE_2022_23960 */ 99 b 2f 1001: 101#if WORKAROUND_CVE_2022_23960 102 adr x0, wa_cve_2017_5715_bpiall_vbar 103 msr vbar_el3, x0 104 isb 105#endif 1062: 107#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ 108 109#if WORKAROUND_CVE_2018_3639 110 mrs x0, CORTEX_A75_CPUACTLR_EL1 111 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 112 msr CORTEX_A75_CPUACTLR_EL1, x0 113 isb 114#endif 115 116#if ERRATA_DSU_798953 117 bl errata_dsu_798953_wa 118#endif 119 120#if ERRATA_DSU_936184 121 bl errata_dsu_936184_wa 122#endif 123 124#if ENABLE_AMU 125 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 126 mrs x0, actlr_el3 127 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 128 msr actlr_el3, x0 129 isb 130 131 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 132 mrs x0, actlr_el2 133 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 134 msr actlr_el2, x0 135 isb 136 137 /* Enable group0 counters */ 138 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 139 msr CPUAMCNTENSET_EL0, x0 140 isb 141 142 /* Enable group1 counters */ 143 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 144 msr CPUAMCNTENSET_EL0, x0 145 isb 146#endif 147 ret x19 148endfunc cortex_a75_reset_func 149 150func check_errata_cve_2017_5715 151 cpu_check_csv2 x0, 1f 152#if WORKAROUND_CVE_2017_5715 153 mov x0, #ERRATA_APPLIES 154#else 155 mov x0, #ERRATA_MISSING 156#endif 157 ret 1581: 159 mov x0, #ERRATA_NOT_APPLIES 160 ret 161endfunc check_errata_cve_2017_5715 162 163func check_errata_cve_2018_3639 164#if WORKAROUND_CVE_2018_3639 165 mov x0, #ERRATA_APPLIES 166#else 167 mov x0, #ERRATA_MISSING 168#endif 169 ret 170endfunc check_errata_cve_2018_3639 171 172func check_errata_cve_2022_23960 173#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 174 cpu_check_csv2 x0, 1f 175 mov x0, #ERRATA_APPLIES 176 ret 1771: 178# if WORKAROUND_CVE_2022_23960 179 mov x0, #ERRATA_APPLIES 180# else 181 mov x0, #ERRATA_MISSING 182# endif /* WORKAROUND_CVE_2022_23960 */ 183 ret 184#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 185 mov x0, #ERRATA_MISSING 186 ret 187endfunc check_errata_cve_2022_23960 188 189func check_smccc_arch_workaround_3 190 mov x0, #ERRATA_APPLIES 191 ret 192endfunc check_smccc_arch_workaround_3 193 194 /* --------------------------------------------- 195 * HW will do the cache maintenance while powering down 196 * --------------------------------------------- 197 */ 198func cortex_a75_core_pwr_dwn 199 /* --------------------------------------------- 200 * Enable CPU power down bit in power control register 201 * --------------------------------------------- 202 */ 203 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 204 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 205 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 206 isb 207 ret 208endfunc cortex_a75_core_pwr_dwn 209 210#if REPORT_ERRATA 211/* 212 * Errata printing function for Cortex A75. Must follow AAPCS. 213 */ 214func cortex_a75_errata_report 215 stp x8, x30, [sp, #-16]! 216 217 bl cpu_get_rev_var 218 mov x8, x0 219 220 /* 221 * Report all errata. The revision-variant information is passed to 222 * checking functions of each errata. 223 */ 224 report_errata ERRATA_A75_764081, cortex_a75, 764081 225 report_errata ERRATA_A75_790748, cortex_a75, 790748 226 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 227 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 228 report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953 229 report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 230 report_errata WORKAROUND_CVE_2022_23960, cortex_a75, cve_2022_23960 231 232 ldp x8, x30, [sp], #16 233 ret 234endfunc cortex_a75_errata_report 235#endif 236 237 /* --------------------------------------------- 238 * This function provides cortex_a75 specific 239 * register information for crash reporting. 240 * It needs to return with x6 pointing to 241 * a list of register names in ascii and 242 * x8 - x15 having values of registers to be 243 * reported. 244 * --------------------------------------------- 245 */ 246.section .rodata.cortex_a75_regs, "aS" 247cortex_a75_regs: /* The ascii list of register names to be reported */ 248 .asciz "cpuectlr_el1", "" 249 250func cortex_a75_cpu_reg_dump 251 adr x6, cortex_a75_regs 252 mrs x8, CORTEX_A75_CPUECTLR_EL1 253 ret 254endfunc cortex_a75_cpu_reg_dump 255 256declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 257 cortex_a75_reset_func, \ 258 check_errata_cve_2017_5715, \ 259 CPU_NO_EXTRA2_FUNC, \ 260 check_smccc_arch_workaround_3, \ 261 cortex_a75_core_pwr_dwn 262