1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef MOD_N1SDP_PCIE_H
9 #define MOD_N1SDP_PCIE_H
10 
11 #include <fwk_id.h>
12 
13 #include <stdbool.h>
14 #include <stdint.h>
15 
16 /*!
17  * \addtogroup GroupN1SDPModule N1SDP Product Modules
18  * \{
19  */
20 
21 /*!
22  * \defgroup GroupModuleN1SDPPcie N1SDP PCIe Driver
23  *
24  * \brief Driver support for N1SDP PCIe Root Complex & End Point devices.
25  *
26  * \details This module provides driver support for enabling and configuring
27  *      the PCIe peripheral either in root complex mode or in end point mode.
28  *
29  * \{
30  */
31 
32 /*!
33  * \brief N1SDP PCIe instance configuration
34  */
35 struct n1sdp_pcie_dev_config {
36     /*!
37      * Base address of the PCIe Controller. This includes the PHY configuration
38      * and PCIe IP level configuration registers.
39      */
40     uintptr_t ctrl_base;
41 
42     /*!
43      * Base address of the PCIe functional configuration registers. This
44      * region includes registers for configuring the IP in both RC and
45      * EP modes.
46      */
47     uintptr_t global_config_base;
48 
49     /*! Base address of the PCIe message registers. */
50     uintptr_t msg_base;
51 
52     /*!
53      * Base address of the PCIe AXI subordinate memory region (within 32-bit
54      * address space). This region holds the ECAM space, MMIO32 & IO space.
55      */
56     uint32_t axi_subordinate_base32;
57 
58     /*!
59      * Base address of the PCIe AXI subordinate memory region (in 64-bit address
60      * space). This region holds the MMIO64 space.
61      */
62     uint64_t axi_subordinate_base64;
63 
64     /*! Identifier to indicate if the PCIe controller is CCIX capable */
65     bool ccix_capable;
66 };
67 
68 /*!
69  * \brief Module API indices
70  */
71 enum n1sdp_pcie_api_idx {
72     /*! Index of the PCIe initialization API */
73     N1SDP_PCIE_API_IDX_PCIE_INIT,
74 
75     /*! Index of the CCIX config API */
76     N1SDP_PCIE_API_IDX_CCIX_CONFIG,
77 
78     /*! Number of APIs */
79     N1SDP_PCIE_API_COUNT
80 };
81 
82 /*!
83  * \brief N1SDP PCIe initialization api
84  */
85 struct n1sdp_pcie_init_api {
86     /*!
87      * \brief API to power ON the PCIe controller
88      *
89      * \param id Identifier of the PCIe instance
90      *
91      * \retval ::FWK_SUCCESS The operation succeeded.
92      * \return One of the standard error codes.
93      */
94     int (*power_on)(fwk_id_t id);
95 
96     /*!
97      * \brief API to initialize the PHY layer
98      *
99      * \param id Identifier of the PCIe instance
100      *
101      * \retval ::FWK_SUCCESS The operation succeeded.
102      * \return One of the standard error codes.
103      */
104     int (*phy_init)(fwk_id_t id);
105 
106     /*!
107      * \brief API to initialize the PCIe controller
108      *
109      * \param id Identifier of the PCIe instance
110      * \param ep_mode Identifier to configure the controller
111      *      in root port or endpoint mode
112      *
113      * \retval ::FWK_SUCCESS The operation succeeded.
114      * \return One of the standard error codes.
115      */
116     int (*controller_init)(fwk_id_t id, bool ep_mode);
117 
118     /*!
119      * \brief API to perform the link training process
120      *
121      * \param id Identifier of the PCIe instance
122      *
123      * \retval ::FWK_SUCCESS The operation succeeded.
124      * \return One of the standard error codes.
125      */
126     int (*link_training)(fwk_id_t id, bool ep_mode);
127 
128     /*!
129      * \brief API to setup the root complex
130      *
131      * \param id Identifier of the PCIe instance
132      *
133      * \retval ::FWK_SUCCESS The operation succeeded.
134      * \return One of the standard error codes.
135      */
136     int (*rc_setup)(fwk_id_t id);
137 
138     /*!
139      * \brief API to enable Virtual Channel 1 and map to
140      *      specified Traffic class. This API is used in multichip mode.
141      *
142      * \param id Identifier of the PCIe instance
143      * \param vc1_tc Traffic class to be mapped to VC1
144      *
145      * \retval ::FWK_SUCCESS The operation succeeded.
146      * \return One of the standard error codes.
147      */
148     int (*vc1_setup)(fwk_id_t id, uint8_t vc1_tc);
149 };
150 
151 /*!
152  * \brief N1SDP PCIe ccix configuration api
153  */
154 struct n1sdp_pcie_ccix_config_api {
155     /*!
156      * \brief Enable the optimized tlp (Transaction Layer Packet)
157      *      for the ccix root complex
158      *
159      * \param enable Enable optimized tlp (true) or disable it (false)
160      *      and thus enable pcie compatible header
161      *
162      * \retval ::FWK_SUCCESS The operation succeeded.
163      * \return One of the standard error codes.
164      */
165     int (*enable_opt_tlp)(bool enable);
166 };
167 
168 /*!
169  * \}
170  */
171 
172 /*!
173  * \}
174  */
175 
176 #endif /* MOD_N1SDP_PCIE_H */
177