1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *     SGM775 DDR-PHY500 module
9  */
10 #ifndef MOD_SGM775_DDR_PHY500_H
11 #define MOD_SGM775_DDR_PHY500_H
12 
13 #include <fwk_macros.h>
14 #include <fwk_module.h>
15 
16 #include <stdint.h>
17 
18 /*!
19  * \addtogroup GroupSGM775Module SGM775 Product Modules
20  * \{
21  */
22 
23 /*!
24  * \addtogroup GroupSGM775_DDR SGM775 DDR PHY500 Driver
25  * \{
26  */
27 
28 /*!
29  * \brief DDR PHY500 register definitions.
30  */
31 struct mod_sgm775_ddr_phy500_reg {
32     /*!
33      * \cond
34      */
35     FWK_RW  uint32_t INIT_COMPLETE;
36     FWK_RW  uint32_t MEMORY_WIDTH;
37     FWK_RW  uint32_t READ_DELAY;
38     FWK_RW  uint32_t CAPTURE_MASK;
39     FWK_RW  uint32_t CAS_LATENCY;
40     FWK_RW  uint32_t T_CTRL_DELAY;
41     FWK_RW  uint32_t T_WRLAT;
42     FWK_RW  uint32_t T_RDDATA_EN;
43     FWK_RW  uint32_t T_RDLAT;
44     FWK_RW  uint32_t DFI_PHYUPD_REQ;
45     FWK_R   uint32_t DFI_PHYUPD_ACK;
46     FWK_R   uint32_t DFI_LP_REQ;
47     FWK_RW  uint32_t DFI_LP_ACK;
48     FWK_RW  uint32_t DFI_RDLVL_REQ;
49     FWK_R   uint32_t DFI_RDLVL_EN;
50     FWK_RW  uint32_t DFI_WRLVL_REQ;
51     FWK_R   uint32_t DFI_WRLVL_EN;
52     FWK_RW  uint32_t DFI_PHYMSTR_REQ;
53     FWK_RW  uint32_t DFI_PHYMSTR_ACK;
54     FWK_RW  uint32_t DFI_WR_PREMBL;
55             uint8_t  RESERVED[0x820 - 0x50];
56     FWK_RW  uint32_t DELAY_SEL;
57     FWK_RW  uint32_t REF_EN;
58     FWK_RW  uint32_t T_CTRL_UPD_MIN;
59     /*!
60      * \endcond
61      */
62 };
63 
64 /*!
65  * \brief Element configuration.
66  */
67 struct mod_sgm775_ddr_phy500_element_config {
68     /*! Base address of a device configuration register. */
69     uintptr_t ddr;
70 };
71 
72 /*!
73  * \}
74  */
75 
76 /*!
77  * \}
78  */
79 
80 #endif /* MOD_SGM775_DDR_PHY500_H */
81