1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * SP805 Watchdog Driver 9 */ 10 11 #ifndef MOD_SP805_H 12 #define MOD_SP805_H 13 14 #include <fwk_id.h> 15 16 /*! 17 * Macros to enable/disable write access to SP805 registers. Writing the value 18 * 0x1ACCE551 to WdogLock register enables write access to all other registers. 19 * Writing any other value disables write access. 20 */ 21 #define ENABLE_WR_ACCESS 0x1ACCE551 22 #define DISABLE_WR_ACCESS 0xFFFFFFFF 23 24 /*! 25 * Macros for enabling SP805 module reset output and interrupt event. 26 */ 27 #define RESET_EN (1 << 1) 28 #define INT_EN (1 << 0) 29 30 /*! 31 * \brief Represent SP805 WDT module register definitions. 32 */ 33 struct sp805_reg { 34 /*! 35 * Load Register, contains the value from which the counter is to decrement 36 */ 37 FWK_RW uint32_t LOAD; 38 39 /*! Value Register, gives the current value of the decrementing counter */ 40 FWK_R uint32_t VALUE; 41 42 /*! Control register, enables the software to control the Watchdog module */ 43 FWK_RW uint32_t CONTROL; 44 45 /*! 46 * Interrupt Clear Register, A write of any value to this location clears 47 * the Watchdog module interrupt, and reloads the counter from the value in 48 * the WdogLoad Register 49 */ 50 FWK_W uint32_t INTCLR; 51 52 /*! 53 * Raw Interrupt Status Register, indicates the raw interrupt status from 54 * the counter 55 */ 56 FWK_R uint32_t RIS; 57 58 /*! 59 * Masked Interrupt Status Register,indicates the masked interrupt status 60 * from the counter 61 */ 62 FWK_R uint32_t MIS; 63 64 /*! Reserved region 1*/ 65 uint8_t RESERVED1[0xC00 - 0x18]; 66 67 /*! Lock Register, allows write-access to all other registers */ 68 FWK_RW uint32_t LOCK; 69 70 /*! Reserved region 2*/ 71 uint8_t RESERVED2[0xF00 - 0xC04]; 72 73 /*! 74 * Integration Test Control Register, use to enable integration test mode 75 */ 76 FWK_RW uint32_t ITCR; 77 78 /*! 79 * Integration Test Output Set Register, When in integration test mode, the 80 * enabled interrupt output and reset output are driven directly from the 81 * values in this register 82 */ 83 FWK_W uint32_t ITOP; 84 85 /*! Reserved region 3*/ 86 uint8_t RESERVED3[0xFE0 - 0xF08]; 87 88 /*! Peripheral identification register 0 */ 89 FWK_R uint32_t PERIPHID0; 90 91 /*! Peripheral identification register 1 */ 92 FWK_R uint32_t PERIPHID1; 93 94 /*! Peripheral identification register 2 */ 95 FWK_R uint32_t PERIPHID2; 96 97 /*! Peripheral identification register 3 */ 98 FWK_R uint32_t PERIPHID3; 99 100 /*! PrimeCell Identification Register 0 */ 101 FWK_R uint32_t PCELLID0; 102 103 /*! PrimeCell Identification Register 1 */ 104 FWK_R uint32_t PCELLID1; 105 106 /*! PrimeCell Identification Register 2 */ 107 FWK_R uint32_t PCELLID2; 108 109 /*! PrimeCell Identification Register 3 */ 110 FWK_R uint32_t PCELLID3; 111 }; 112 113 /*! 114 * \brief Configuration data for a SP805 WatchDog device. 115 */ 116 struct mod_sp805_config { 117 /*! Base address of the device registers */ 118 const uintptr_t reg_base; 119 120 /*! Watchdog Timer value to be loaded in the timer register */ 121 const unsigned int wdt_load_value; 122 123 /*! 124 * Identifier of the clock that this device depends on. If the device is not 125 * dependent on any clock, FWK_ID_NONE_INIT should be assigned for this 126 * configuration value. 127 */ 128 fwk_id_t driver_id; 129 130 /*! 131 * Watch Dog device IRQ number 132 * 133 * Please note that sp805 driver is expecting a valid interrupt number in 134 * sp805_irq. If FWK_INTERRUPT_NONE is assigned, the SP805 controller is not 135 * enabled. 136 */ 137 const unsigned int sp805_irq; 138 }; 139 140 #endif /* MOD_SP805_H */ 141