1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef MORELLO_MCP_SYSTEM_MMAP_H 9 #define MORELLO_MCP_SYSTEM_MMAP_H 10 11 /* 12 * External QSPI flash memory - mapped address 13 */ 14 #define MCP_QSPI_FLASH_BASE_ADDR 0x30000000 15 #define MCP_QSPI_FLASH_BASE_ADDR_ALT 0x00840000 16 #define MCP_QSPI_FLASH_SIZE 0x02000000 17 18 /* 19 * Internal MCP's ROM/RAM base address 20 */ 21 #define MCP_ROM_BASE 0x00000000 22 #define MCP_RAM0_BASE 0x00800000 23 #define MCP_RAM1_BASE 0x20000000 24 25 /* 26 * Internal MCP's ROM/RAM sizes 27 */ 28 #define MCP_ROM_SIZE (128 * 1024) 29 #define MCP_RAM0_SIZE (512 * 1024) 30 #define MCP_RAM1_SIZE (256 * 1024) 31 32 /* 33 * MCP_BACKUP_DDR3 memory area where the MCP ROM 34 * bypass firmware should be placed. The MCP would 35 * be programmed to boot at this address by programming 36 * it in the MCP_BOOT_ADR SCC register. 37 */ 38 #define MCP_BACKUP_DDR3_BASE 0x16000000 39 #define MCP_BACKUP_DDR3_SIZE (32 * 1024 * 1024) 40 41 #endif /* MORELLO_MCP_SYSTEM_MMAP_H */ 42