1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef MORELLO_SCP_MMAP_H
9 #define MORELLO_SCP_MMAP_H
10 
11 #include <stdint.h>
12 
13 /*
14  * Top-level base addresses
15  */
16 #define SCP_EXPANSION1_BASE UINT32_C(0x01000000)
17 #define SCP_EXPANSION2_BASE UINT32_C(0x21000000)
18 #define SCP_SCC_BASE UINT32_C(0x3FFFF000)
19 #define SCP_EXPANSION3_BASE UINT32_C(0x40000000)
20 #define SCP_PERIPHERAL_BASE UINT32_C(0x44000000)
21 #define SCP_MEMORY_CONTROLLER UINT32_C(0x4E000000)
22 #define SCP_POWER_PERIPHERAL_BASE UINT32_C(0x50000000)
23 #define SCP_NOC_GPV_BASE UINT32_C(0x51000000)
24 #define SCP_SYS0_BASE UINT32_C(0x60000000)
25 #define SCP_SYS1_BASE UINT32_C(0xA0000000)
26 #define SCP_PPB_BASE_INTERNAL UINT32_C(0xE0000000)
27 #define SCP_PPB_BASE_EXTERNAL UINT32_C(0xE0040000)
28 
29 /*
30  * Peripherals - Timer/Counter
31  */
32 #define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000)
33 #define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000)
34 #define SCP_WDOG_BASE (SCP_PERIPHERAL_BASE + 0x6000)
35 
36 /*
37  * Timer Synchronization Module base
38  */
39 #define SCP_TIMER_SYNC_BASE UINT32_C(0x47000000)
40 
41 /*
42  * CoreSight control base
43  */
44 #define SCP_CS_CNTCONTROL_BASE (SCP_PERIPHERAL_BASE + 0xA000)
45 
46 /*
47  * Peripherals - Serial communication
48  */
49 #define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000)
50 #define DIMM_SPD_I2C_BASE (0xBC040000)
51 #define SCP_I2C0_BASE (0x3FFFA000)
52 #define SCP_I2C1_BASE (0x3FFFB000)
53 #define SCP_I2C2_BASE (0x3FFFC000)
54 
55 /*
56  * Peripherals - Mailbox communication
57  */
58 #define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE + 0x1000000)
59 #define SCP_MHU_MCP_BASE (SCP_PERIPHERAL_BASE + 0x1600000)
60 
61 /*
62  * Power control peripherals
63  */
64 #define SCP_PIK_SCP_BASE (SCP_POWER_PERIPHERAL_BASE + 0x00000)
65 #define SCP_PIK_DEBUG_BASE (SCP_POWER_PERIPHERAL_BASE + 0x20000)
66 #define SCP_SCP_SENSOR_DEBUG_BASE (SCP_POWER_PERIPHERAL_BASE + 0x30000)
67 #define SCP_PIK_SYSTEM_BASE (SCP_POWER_PERIPHERAL_BASE + 0x40000)
68 #define SCP_SENSOR_SYSTEM_BASE (SCP_POWER_PERIPHERAL_BASE + 0x50000)
69 #define SCP_SENSOR_CLUS0_BASE (SCP_POWER_PERIPHERAL_BASE + 0x60000)
70 #define SCP_SENSOR_CLUS1_BASE (SCP_POWER_PERIPHERAL_BASE + 0x80000)
71 #define SCP_PIK_CLUSTER_BASE(n) \
72     ((SCP_POWER_PERIPHERAL_BASE + 0x60000) + ((n)*0x20000))
73 #define SCP_PIK_DEBUG_CHAIN_BASE (SCP_POWER_PERIPHERAL_BASE + 0x500000)
74 #define SCP_PIK_DPU_BASE (SCP_POWER_PERIPHERAL_BASE + 0x620000)
75 #define SCP_PIK_GPU_BASE (SCP_POWER_PERIPHERAL_BASE + 0x630000)
76 
77 /*
78  * PPU base address
79  */
80 #define SCP_PPU_SCP_BASE (SCP_PIK_SCP_BASE + 0x1000)
81 #define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000)
82 #define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000)
83 #define SCP_PPU_DEBUG_BASE (SCP_PIK_DEBUG_BASE + 0x1000)
84 #define SCP_PPU_DPU_BASE (SCP_PIK_DPU_BASE + 0x1000)
85 #define SCP_PPU_GPU_BASE (SCP_PIK_GPU_BASE + 0x1000)
86 #define SCP_PPU_CLUSTER_BASE(n) (SCP_PIK_CLUSTER_BASE((n)) + 0x1000)
87 #define SCP_PPU_CORE_BASE(n, m) (SCP_PPU_CLUSTER_BASE((n)) + ((m) + 1) * 0x1000)
88 
89 /*
90  * PCIe & CCIX Peripherals
91  *
92  * SCP memory for PCIe and CCIX APB and AXI Access
93  * (0x6000_0000 - 0x9FFF_FFFF) maps AP memory address
94  * space (0x4000_0000 - 0x7FFF_FFFF)
95  */
96 
97 /*
98  * APB Registers
99  */
100 #define PCIE_RC_CFG_REG_SCP_BASE UINT32_C(0xC0000000)
101 #define PCIE_IP_CFG_REG_SCP_BASE UINT32_C(0xC0800000)
102 #define PCIE_MSG_CFG_REG_SCP_BASE UINT32_C(0xC0850000)
103 
104 #define CCIX_RC_CFG_REG_SCP_BASE UINT32_C(0xC1000000)
105 #define CCIX_IP_CFG_REG_SCP_BASE UINT32_C(0xC1800000)
106 #define CCIX_MSG_CFG_REG_SCP_BASE UINT32_C(0xC1850000)
107 
108 /*
109  * PCIe and CCIX Subordinate AXI space visible to SCP
110  */
111 #define PCIE_AXI_SUBORDINATE_SCP_BASE UINT32_C(0x80000000)
112 #define CCIX_AXI_SUBORDINATE_SCP_BASE UINT32_C(0x90000000)
113 
114 /*
115  * PCIe and CCIX Subordinate AXI space visible to AP
116  */
117 #define PCIE_AXI32_SUBORDINATE_AP_BASE UINT32_C(0x60000000)
118 #define CCIX_AXI32_SUBORDINATE_AP_BASE UINT32_C(0x70000000)
119 
120 /*
121  * PCIe and CCIX Subordinate AXI in 64-bit space visible to AP
122  */
123 #define PCIE_AXI64_SUBORDINATE_AP_BASE UINT64_C(0x900000000)
124 #define CCIX_AXI64_SUBORDINATE_AP_BASE UINT64_C(0x3000000000)
125 
126 /*
127  * 1MB window into AP memory space
128  * This region enables SCP to access AP's memory region
129  * in terms of 1MB windows.
130  */
131 #define SCP_AP_1MB_WINDOW_OFFSET 0x2B000000
132 #define SCP_AP_1MB_WINDOW_BASE (SCP_SYS1_BASE + SCP_AP_1MB_WINDOW_OFFSET)
133 #define SCP_AP_1MB_WINDOW_SIZE 0x100000
134 #define SCP_AP_1MB_WINDOW_ADDR_MASK 0xFFFFF
135 #define SCP_AP_1MB_WINDOW_SHIFT 20
136 
137 /*
138  * GIC600 Registers
139  */
140 #define GIC600_GICC_BASE (SCP_SYS1_BASE + 0x2C000000)
141 #define GIC600_GICH_BASE (SCP_SYS1_BASE + 0x2C010000)
142 #define GIC600_GICV_BASE (SCP_SYS1_BASE + 0x2C020000)
143 
144 #define GIC600_GICD_BASE (SCP_SYS1_BASE + 0x30000000)
145 #define GIC600_GICA_BASE (SCP_SYS1_BASE + 0x30010000)
146 #define GIC600_GICP_BASE (SCP_SYS1_BASE + 0x30030000)
147 #define GIC600_GITS_BASE (SCP_SYS1_BASE + 0x30040000)
148 
149 /*
150  * System access port 0
151  */
152 #define SCP_CMN_SKEENA_BASE (SCP_SYS0_BASE + 0x10000000)
153 #define CMN_SKEENA_ROOT_NODE_OFFSET 0xD00000
154 #define CMN_SKEENA_ROOTNODE_BASE \
155     (SCP_CMN_SKEENA_BASE + CMN_SKEENA_ROOT_NODE_OFFSET)
156 
157 #define SCP_AP_SHARED_SECURE_RAM (SCP_SYS0_BASE + 0x05400000)
158 #define SCP_AP_SHARED_NONSECURE_RAM (SCP_SYS0_BASE + 0x05200000)
159 #define SCP_MCP_SHARED_SECURE_RAM (SCP_PERIPHERAL_BASE + 0x01620000)
160 #define SCP_MCP_SHARED_NONSECURE_RAM (SCP_PERIPHERAL_BASE + 0x01610000)
161 
162 /*
163  * System access port 1
164  */
165 #define SCP_TRUSTED_RAM_BASE (SCP_SYS1_BASE + 0x04000000)
166 #define SCP_NONTRUSTED_RAM_BASE (SCP_SYS1_BASE + 0x06000000)
167 #define SCP_SSC_BASE (SCP_SYS1_BASE + 0x2A420000)
168 #define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYS1_BASE + 0x2A430000)
169 
170 /* Base address of AP-SCP mailbox for non-secure access */
171 #define SCP_AP_BASE_NS_MAILBOX_SRAM (SCP_NONTRUSTED_RAM_BASE)
172 /*
173  * Base addresses of MHU devices
174  */
175 #define MHU_SCP_TO_AP_NS(cluster) \
176     ((SCP_MHU_AP_BASE + (0x00010000 * cluster) + 0x00000020))
177 #define MHU_AP_TO_SCP_NS(cluster) \
178     ((SCP_MHU_AP_BASE + (0x00010000 * cluster) + 0x00000120))
179 #define MHU_SCP_TO_AP_S(cluster) \
180     ((SCP_MHU_AP_BASE + (0x00010000 * cluster) + 0x00000200))
181 #define MHU_AP_TO_SCP_S(cluster) \
182     ((SCP_MHU_AP_BASE + (0x00010000 * cluster) + 0x00000300))
183 
184 #define MHU_SCP_TO_MCP_NS (SCP_MHU_MCP_BASE + 0x00000020)
185 #define MHU_MCP_TO_SCP_NS (SCP_MHU_MCP_BASE + 0x00000120)
186 #define MHU_SCP_TO_MCP_S (SCP_MHU_MCP_BASE + 0x00000200)
187 #define MHU_MCP_TO_SCP_S (SCP_MHU_MCP_BASE + 0x00000300)
188 
189 /*
190  * MORELLO PLL address space
191  */
192 #define SCP_PLL_CPU0_CTRL (SCP_SCC_BASE + 0x00000100)
193 #define SCP_PLL_CPU0_STAT (SCP_SCC_BASE + 0x00000104)
194 #define SCP_PLL_CPU1_CTRL (SCP_SCC_BASE + 0x00000108)
195 #define SCP_PLL_CPU1_STAT (SCP_SCC_BASE + 0x0000010C)
196 #define SCP_PLL_CLUS_CTRL (SCP_SCC_BASE + 0x00000110)
197 #define SCP_PLL_CLUS_STAT (SCP_SCC_BASE + 0x00000114)
198 #define SCP_PLL_SYSPLL_CTRL (SCP_SCC_BASE + 0x00000118)
199 #define SCP_PLL_SYSPLL_STAT (SCP_SCC_BASE + 0x0000011C)
200 #define SCP_PLL_DMC_CTRL (SCP_SCC_BASE + 0x00000120)
201 #define SCP_PLL_DMC_STAT (SCP_SCC_BASE + 0x00000124)
202 #define SCP_PLL_INTERCONNECT_CTRL (SCP_SCC_BASE + 0x00000128)
203 #define SCP_PLL_INTERCONNECT_STAT (SCP_SCC_BASE + 0x0000012C)
204 #define SCP_PLL_GPU_CTRL (SCP_SCC_BASE + 0x00000130)
205 #define SCP_PLL_GPU_STAT (SCP_SCC_BASE + 0x00000134)
206 #define SCP_PLL_DPU_CTRL (SCP_SCC_BASE + 0x00000138)
207 #define SCP_PLL_DPU_STAT (SCP_SCC_BASE + 0x0000013C)
208 #define SCP_PLL_PIXEL_CTRL (SCP_SCC_BASE + 0x00000140)
209 #define SCP_PLL_PIXEL_STAT (SCP_SCC_BASE + 0x00000144)
210 
211 /*
212  * DDR PHY base address
213  */
214 #define SCP_DDR_PHY0 (0x50604000)
215 #define SCP_DDR_PHY1 (0x50614000)
216 
217 /*
218  * DMC-620 controller base address
219  */
220 #define SCP_DMC0 (SCP_MEMORY_CONTROLLER + 0x00000000)
221 #define SCP_DMC1 (SCP_MEMORY_CONTROLLER + 0x00100000)
222 
223 /*
224  * SoC temperature register address
225  */
226 #define SCP_PLAT_BASE (SCP_SYS0_BASE + 0x3FFE0000)
227 #define SCP_SENSOR_SOC_TEMP (SCP_PLAT_BASE + 0x00000080)
228 
229 #endif /* MORELLO_SCP_MMAP_H */
230