1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 * Author: Sam.Shih <sam.shih@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mt7986-clk.h> 10#include <dt-bindings/reset/mt7986-resets.h> 11#include <dt-bindings/phy/phy.h> 12 13/ { 14 compatible = "mediatek,mt7986a"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clk40m: oscillator-40m { 20 compatible = "fixed-clock"; 21 clock-frequency = <40000000>; 22 #clock-cells = <0>; 23 clock-output-names = "clkxtal"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 #cooling-cells = <2>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 reg = <0x1>; 42 #cooling-cells = <2>; 43 }; 44 45 cpu2: cpu@2 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 enable-method = "psci"; 49 reg = <0x2>; 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 enable-method = "psci"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x3>; 58 #cooling-cells = <2>; 59 }; 60 }; 61 62 psci { 63 compatible = "arm,psci-0.2"; 64 method = "smc"; 65 }; 66 67 reserved-memory { 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 72 secmon_reserved: secmon@43000000 { 73 reg = <0 0x43000000 0 0x30000>; 74 no-map; 75 }; 76 77 wmcpu_emi: wmcpu-reserved@4fc00000 { 78 no-map; 79 reg = <0 0x4fc00000 0 0x00100000>; 80 }; 81 82 wo_emi0: wo-emi@4fd00000 { 83 reg = <0 0x4fd00000 0 0x40000>; 84 no-map; 85 }; 86 87 wo_emi1: wo-emi@4fd40000 { 88 reg = <0 0x4fd40000 0 0x40000>; 89 no-map; 90 }; 91 92 wo_ilm0: wo-ilm@151e0000 { 93 reg = <0 0x151e0000 0 0x8000>; 94 no-map; 95 }; 96 97 wo_ilm1: wo-ilm@151f0000 { 98 reg = <0 0x151f0000 0 0x8000>; 99 no-map; 100 }; 101 102 wo_data: wo-data@4fd80000 { 103 reg = <0 0x4fd80000 0 0x240000>; 104 no-map; 105 }; 106 107 wo_dlm0: wo-dlm@151e8000 { 108 reg = <0 0x151e8000 0 0x2000>; 109 no-map; 110 }; 111 112 wo_dlm1: wo-dlm@151f8000 { 113 reg = <0 0x151f8000 0 0x2000>; 114 no-map; 115 }; 116 117 wo_boot: wo-boot@15194000 { 118 reg = <0 0x15194000 0 0x1000>; 119 no-map; 120 }; 121 122 }; 123 124 timer { 125 compatible = "arm,armv8-timer"; 126 interrupt-parent = <&gic>; 127 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 128 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 129 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 130 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 131 }; 132 133 soc { 134 #address-cells = <2>; 135 #size-cells = <2>; 136 compatible = "simple-bus"; 137 ranges; 138 139 gic: interrupt-controller@c000000 { 140 compatible = "arm,gic-v3"; 141 #interrupt-cells = <3>; 142 interrupt-parent = <&gic>; 143 interrupt-controller; 144 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 145 <0 0x0c080000 0 0x80000>, /* GICR */ 146 <0 0x0c400000 0 0x2000>, /* GICC */ 147 <0 0x0c410000 0 0x1000>, /* GICH */ 148 <0 0x0c420000 0 0x2000>; /* GICV */ 149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 infracfg: infracfg@10001000 { 153 compatible = "mediatek,mt7986-infracfg", "syscon"; 154 reg = <0 0x10001000 0 0x1000>; 155 #clock-cells = <1>; 156 }; 157 158 wed_pcie: wed-pcie@10003000 { 159 compatible = "mediatek,mt7986-wed-pcie", 160 "syscon"; 161 reg = <0 0x10003000 0 0x10>; 162 }; 163 164 topckgen: topckgen@1001b000 { 165 compatible = "mediatek,mt7986-topckgen", "syscon"; 166 reg = <0 0x1001B000 0 0x1000>; 167 #clock-cells = <1>; 168 }; 169 170 watchdog: watchdog@1001c000 { 171 compatible = "mediatek,mt7986-wdt"; 172 reg = <0 0x1001c000 0 0x1000>; 173 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 174 #reset-cells = <1>; 175 status = "disabled"; 176 }; 177 178 apmixedsys: apmixedsys@1001e000 { 179 compatible = "mediatek,mt7986-apmixedsys"; 180 reg = <0 0x1001E000 0 0x1000>; 181 #clock-cells = <1>; 182 }; 183 184 pio: pinctrl@1001f000 { 185 compatible = "mediatek,mt7986a-pinctrl"; 186 reg = <0 0x1001f000 0 0x1000>, 187 <0 0x11c30000 0 0x1000>, 188 <0 0x11c40000 0 0x1000>, 189 <0 0x11e20000 0 0x1000>, 190 <0 0x11e30000 0 0x1000>, 191 <0 0x11f00000 0 0x1000>, 192 <0 0x11f10000 0 0x1000>, 193 <0 0x1000b000 0 0x1000>; 194 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", 195 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; 196 gpio-controller; 197 #gpio-cells = <2>; 198 gpio-ranges = <&pio 0 0 100>; 199 interrupt-controller; 200 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-parent = <&gic>; 202 #interrupt-cells = <2>; 203 }; 204 205 sgmiisys0: syscon@10060000 { 206 compatible = "mediatek,mt7986-sgmiisys_0", 207 "syscon"; 208 reg = <0 0x10060000 0 0x1000>; 209 #clock-cells = <1>; 210 }; 211 212 sgmiisys1: syscon@10070000 { 213 compatible = "mediatek,mt7986-sgmiisys_1", 214 "syscon"; 215 reg = <0 0x10070000 0 0x1000>; 216 #clock-cells = <1>; 217 }; 218 219 trng: rng@1020f000 { 220 compatible = "mediatek,mt7986-rng", 221 "mediatek,mt7623-rng"; 222 reg = <0 0x1020f000 0 0x100>; 223 clocks = <&infracfg CLK_INFRA_TRNG_CK>; 224 clock-names = "rng"; 225 status = "disabled"; 226 }; 227 228 crypto: crypto@10320000 { 229 compatible = "inside-secure,safexcel-eip97"; 230 reg = <0 0x10320000 0 0x40000>; 231 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "ring0", "ring1", "ring2", "ring3"; 236 clocks = <&infracfg CLK_INFRA_EIP97_CK>; 237 clock-names = "infra_eip97_ck"; 238 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; 239 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; 240 status = "disabled"; 241 }; 242 243 uart0: serial@11002000 { 244 compatible = "mediatek,mt7986-uart", 245 "mediatek,mt6577-uart"; 246 reg = <0 0x11002000 0 0x400>; 247 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&infracfg CLK_INFRA_UART0_SEL>, 249 <&infracfg CLK_INFRA_UART0_CK>; 250 clock-names = "baud", "bus"; 251 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, 252 <&infracfg CLK_INFRA_UART0_SEL>; 253 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, 254 <&topckgen CLK_TOP_UART_SEL>; 255 status = "disabled"; 256 }; 257 258 uart1: serial@11003000 { 259 compatible = "mediatek,mt7986-uart", 260 "mediatek,mt6577-uart"; 261 reg = <0 0x11003000 0 0x400>; 262 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&infracfg CLK_INFRA_UART1_SEL>, 264 <&infracfg CLK_INFRA_UART1_CK>; 265 clock-names = "baud", "bus"; 266 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; 267 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 268 status = "disabled"; 269 }; 270 271 uart2: serial@11004000 { 272 compatible = "mediatek,mt7986-uart", 273 "mediatek,mt6577-uart"; 274 reg = <0 0x11004000 0 0x400>; 275 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&infracfg CLK_INFRA_UART2_SEL>, 277 <&infracfg CLK_INFRA_UART2_CK>; 278 clock-names = "baud", "bus"; 279 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; 280 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 281 status = "disabled"; 282 }; 283 284 i2c0: i2c@11008000 { 285 compatible = "mediatek,mt7986-i2c"; 286 reg = <0 0x11008000 0 0x90>, 287 <0 0x10217080 0 0x80>; 288 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 289 clock-div = <5>; 290 clocks = <&infracfg CLK_INFRA_I2C0_CK>, 291 <&infracfg CLK_INFRA_AP_DMA_CK>; 292 clock-names = "main", "dma"; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 status = "disabled"; 296 }; 297 298 spi0: spi@1100a000 { 299 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 reg = <0 0x1100a000 0 0x100>; 303 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&topckgen CLK_TOP_MPLL_D2>, 305 <&topckgen CLK_TOP_SPI_SEL>, 306 <&infracfg CLK_INFRA_SPI0_CK>, 307 <&infracfg CLK_INFRA_SPI0_HCK_CK>; 308 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 309 status = "disabled"; 310 }; 311 312 spi1: spi@1100b000 { 313 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 reg = <0 0x1100b000 0 0x100>; 317 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&topckgen CLK_TOP_MPLL_D2>, 319 <&topckgen CLK_TOP_SPIM_MST_SEL>, 320 <&infracfg CLK_INFRA_SPI1_CK>, 321 <&infracfg CLK_INFRA_SPI1_HCK_CK>; 322 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; 323 status = "disabled"; 324 }; 325 326 ssusb: usb@11200000 { 327 compatible = "mediatek,mt7986-xhci", 328 "mediatek,mtk-xhci"; 329 reg = <0 0x11200000 0 0x2e00>, 330 <0 0x11203e00 0 0x0100>; 331 reg-names = "mac", "ippc"; 332 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, 334 <&infracfg CLK_INFRA_IUSB_CK>, 335 <&infracfg CLK_INFRA_IUSB_133_CK>, 336 <&infracfg CLK_INFRA_IUSB_66M_CK>, 337 <&topckgen CLK_TOP_U2U3_XHCI_SEL>; 338 clock-names = "sys_ck", 339 "ref_ck", 340 "mcu_ck", 341 "dma_ck", 342 "xhci_ck"; 343 phys = <&u2port0 PHY_TYPE_USB2>, 344 <&u3port0 PHY_TYPE_USB3>, 345 <&u2port1 PHY_TYPE_USB2>; 346 status = "disabled"; 347 }; 348 349 mmc0: mmc@11230000 { 350 compatible = "mediatek,mt7986-mmc"; 351 reg = <0 0x11230000 0 0x1000>, 352 <0 0x11c20000 0 0x1000>; 353 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, 355 <&infracfg CLK_INFRA_MSDC_HCK_CK>, 356 <&infracfg CLK_INFRA_MSDC_CK>, 357 <&infracfg CLK_INFRA_MSDC_133M_CK>, 358 <&infracfg CLK_INFRA_MSDC_66M_CK>; 359 clock-names = "source", "hclk", "source_cg", "bus_clk", 360 "sys_cg"; 361 status = "disabled"; 362 }; 363 364 pcie: pcie@11280000 { 365 compatible = "mediatek,mt7986-pcie", 366 "mediatek,mt8192-pcie"; 367 device_type = "pci"; 368 #address-cells = <3>; 369 #size-cells = <2>; 370 reg = <0x00 0x11280000 0x00 0x4000>; 371 reg-names = "pcie-mac"; 372 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 373 bus-range = <0x00 0xff>; 374 ranges = <0x82000000 0x00 0x20000000 0x00 375 0x20000000 0x00 0x10000000>; 376 clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, 377 <&infracfg CLK_INFRA_IPCIE_CK>, 378 <&infracfg CLK_INFRA_IPCIER_CK>, 379 <&infracfg CLK_INFRA_IPCIEB_CK>; 380 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; 381 status = "disabled"; 382 383 phys = <&pcie_port PHY_TYPE_PCIE>; 384 phy-names = "pcie-phy"; 385 386 #interrupt-cells = <1>; 387 interrupt-map-mask = <0 0 0 0x7>; 388 interrupt-map = <0 0 0 1 &pcie_intc 0>, 389 <0 0 0 2 &pcie_intc 1>, 390 <0 0 0 3 &pcie_intc 2>, 391 <0 0 0 4 &pcie_intc 3>; 392 pcie_intc: interrupt-controller { 393 #address-cells = <0>; 394 #interrupt-cells = <1>; 395 interrupt-controller; 396 }; 397 }; 398 399 pcie_phy: t-phy@11c00000 { 400 compatible = "mediatek,mt7986-tphy", 401 "mediatek,generic-tphy-v2"; 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges; 405 status = "disabled"; 406 407 pcie_port: pcie-phy@11c00000 { 408 reg = <0 0x11c00000 0 0x20000>; 409 clocks = <&clk40m>; 410 clock-names = "ref"; 411 #phy-cells = <1>; 412 }; 413 }; 414 415 usb_phy: t-phy@11e10000 { 416 compatible = "mediatek,mt7986-tphy", 417 "mediatek,generic-tphy-v2"; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges = <0 0 0x11e10000 0x1700>; 421 status = "disabled"; 422 423 u2port0: usb-phy@0 { 424 reg = <0x0 0x700>; 425 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, 426 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; 427 clock-names = "ref", "da_ref"; 428 #phy-cells = <1>; 429 }; 430 431 u3port0: usb-phy@700 { 432 reg = <0x700 0x900>; 433 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; 434 clock-names = "ref"; 435 #phy-cells = <1>; 436 }; 437 438 u2port1: usb-phy@1000 { 439 reg = <0x1000 0x700>; 440 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, 441 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; 442 clock-names = "ref", "da_ref"; 443 #phy-cells = <1>; 444 }; 445 }; 446 447 ethsys: syscon@15000000 { 448 #address-cells = <1>; 449 #size-cells = <1>; 450 compatible = "mediatek,mt7986-ethsys", 451 "syscon"; 452 reg = <0 0x15000000 0 0x1000>; 453 #clock-cells = <1>; 454 #reset-cells = <1>; 455 }; 456 457 wed0: wed@15010000 { 458 compatible = "mediatek,mt7986-wed", 459 "syscon"; 460 reg = <0 0x15010000 0 0x1000>; 461 interrupt-parent = <&gic>; 462 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 463 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, 464 <&wo_data>, <&wo_boot>; 465 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 466 "wo-data", "wo-boot"; 467 mediatek,wo-ccif = <&wo_ccif0>; 468 }; 469 470 wed1: wed@15011000 { 471 compatible = "mediatek,mt7986-wed", 472 "syscon"; 473 reg = <0 0x15011000 0 0x1000>; 474 interrupt-parent = <&gic>; 475 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 476 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, 477 <&wo_data>, <&wo_boot>; 478 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", 479 "wo-data", "wo-boot"; 480 mediatek,wo-ccif = <&wo_ccif1>; 481 }; 482 483 wo_ccif0: syscon@151a5000 { 484 compatible = "mediatek,mt7986-wo-ccif", "syscon"; 485 reg = <0 0x151a5000 0 0x1000>; 486 interrupt-parent = <&gic>; 487 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 488 }; 489 490 wo_ccif1: syscon@151ad000 { 491 compatible = "mediatek,mt7986-wo-ccif", "syscon"; 492 reg = <0 0x151ad000 0 0x1000>; 493 interrupt-parent = <&gic>; 494 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 495 }; 496 497 eth: ethernet@15100000 { 498 compatible = "mediatek,mt7986-eth"; 499 reg = <0 0x15100000 0 0x80000>; 500 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <ðsys CLK_ETH_FE_EN>, 505 <ðsys CLK_ETH_GP2_EN>, 506 <ðsys CLK_ETH_GP1_EN>, 507 <ðsys CLK_ETH_WOCPU1_EN>, 508 <ðsys CLK_ETH_WOCPU0_EN>, 509 <&sgmiisys0 CLK_SGMII0_TX250M_EN>, 510 <&sgmiisys0 CLK_SGMII0_RX250M_EN>, 511 <&sgmiisys0 CLK_SGMII0_CDR_REF>, 512 <&sgmiisys0 CLK_SGMII0_CDR_FB>, 513 <&sgmiisys1 CLK_SGMII1_TX250M_EN>, 514 <&sgmiisys1 CLK_SGMII1_RX250M_EN>, 515 <&sgmiisys1 CLK_SGMII1_CDR_REF>, 516 <&sgmiisys1 CLK_SGMII1_CDR_FB>, 517 <&topckgen CLK_TOP_NETSYS_SEL>, 518 <&topckgen CLK_TOP_NETSYS_500M_SEL>; 519 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", 520 "sgmii_tx250m", "sgmii_rx250m", 521 "sgmii_cdr_ref", "sgmii_cdr_fb", 522 "sgmii2_tx250m", "sgmii2_rx250m", 523 "sgmii2_cdr_ref", "sgmii2_cdr_fb", 524 "netsys0", "netsys1"; 525 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 526 <&topckgen CLK_TOP_SGM_325M_SEL>; 527 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, 528 <&apmixedsys CLK_APMIXED_SGMPLL>; 529 mediatek,ethsys = <ðsys>; 530 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; 531 mediatek,wed-pcie = <&wed_pcie>; 532 mediatek,wed = <&wed0>, <&wed1>; 533 #reset-cells = <1>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 }; 538 539 wifi: wifi@18000000 { 540 compatible = "mediatek,mt7986-wmac"; 541 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; 542 reset-names = "consys"; 543 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, 544 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; 545 clock-names = "mcu", "ap2conn"; 546 reg = <0 0x18000000 0 0x1000000>, 547 <0 0x10003000 0 0x1000>, 548 <0 0x11d10000 0 0x1000>; 549 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 553 memory-region = <&wmcpu_emi>; 554 }; 555 }; 556 557}; 558