1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8192-clk.h> 9#include <dt-bindings/gce/mt8192-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8192-larb-port.h> 13#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mt8192-power.h> 16#include <dt-bindings/reset/mt8192-resets.h> 17 18/ { 19 compatible = "mediatek,mt8192"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl-2l0 = &ovl_2l0; 27 ovl-2l2 = &ovl_2l2; 28 rdma0 = &rdma0; 29 rdma4 = &rdma4; 30 }; 31 32 clk13m: fixed-factor-clock-13m { 33 compatible = "fixed-factor-clock"; 34 #clock-cells = <0>; 35 clocks = <&clk26m>; 36 clock-div = <2>; 37 clock-mult = <1>; 38 clock-output-names = "clk13m"; 39 }; 40 41 clk26m: oscillator0 { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <26000000>; 45 clock-output-names = "clk26m"; 46 }; 47 48 clk32k: oscillator1 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <32768>; 52 clock-output-names = "clk32k"; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x000>; 63 enable-method = "psci"; 64 clock-frequency = <1701000000>; 65 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_0>; 73 capacity-dmips-mhz = <530>; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x100>; 80 enable-method = "psci"; 81 clock-frequency = <1701000000>; 82 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 83 i-cache-size = <32768>; 84 i-cache-line-size = <64>; 85 i-cache-sets = <128>; 86 d-cache-size = <32768>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 next-level-cache = <&l2_0>; 90 capacity-dmips-mhz = <530>; 91 }; 92 93 cpu2: cpu@200 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x200>; 97 enable-method = "psci"; 98 clock-frequency = <1701000000>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 capacity-dmips-mhz = <530>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 clock-frequency = <1701000000>; 116 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 117 i-cache-size = <32768>; 118 i-cache-line-size = <64>; 119 i-cache-sets = <128>; 120 d-cache-size = <32768>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 next-level-cache = <&l2_0>; 124 capacity-dmips-mhz = <530>; 125 }; 126 127 cpu4: cpu@400 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a76"; 130 reg = <0x400>; 131 enable-method = "psci"; 132 clock-frequency = <2171000000>; 133 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 134 i-cache-size = <65536>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; 137 d-cache-size = <65536>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <256>; 140 next-level-cache = <&l2_1>; 141 capacity-dmips-mhz = <1024>; 142 }; 143 144 cpu5: cpu@500 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a76"; 147 reg = <0x500>; 148 enable-method = "psci"; 149 clock-frequency = <2171000000>; 150 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 151 i-cache-size = <65536>; 152 i-cache-line-size = <64>; 153 i-cache-sets = <256>; 154 d-cache-size = <65536>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <256>; 157 next-level-cache = <&l2_1>; 158 capacity-dmips-mhz = <1024>; 159 }; 160 161 cpu6: cpu@600 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a76"; 164 reg = <0x600>; 165 enable-method = "psci"; 166 clock-frequency = <2171000000>; 167 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 168 i-cache-size = <65536>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <256>; 171 d-cache-size = <65536>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <256>; 174 next-level-cache = <&l2_1>; 175 capacity-dmips-mhz = <1024>; 176 }; 177 178 cpu7: cpu@700 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a76"; 181 reg = <0x700>; 182 enable-method = "psci"; 183 clock-frequency = <2171000000>; 184 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 185 i-cache-size = <65536>; 186 i-cache-line-size = <64>; 187 i-cache-sets = <256>; 188 d-cache-size = <65536>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <256>; 191 next-level-cache = <&l2_1>; 192 capacity-dmips-mhz = <1024>; 193 }; 194 195 cpu-map { 196 cluster0 { 197 core0 { 198 cpu = <&cpu0>; 199 }; 200 core1 { 201 cpu = <&cpu1>; 202 }; 203 core2 { 204 cpu = <&cpu2>; 205 }; 206 core3 { 207 cpu = <&cpu3>; 208 }; 209 core4 { 210 cpu = <&cpu4>; 211 }; 212 core5 { 213 cpu = <&cpu5>; 214 }; 215 core6 { 216 cpu = <&cpu6>; 217 }; 218 core7 { 219 cpu = <&cpu7>; 220 }; 221 }; 222 }; 223 224 l2_0: l2-cache0 { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-size = <131072>; 228 cache-line-size = <64>; 229 cache-sets = <512>; 230 next-level-cache = <&l3_0>; 231 }; 232 233 l2_1: l2-cache1 { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-size = <262144>; 237 cache-line-size = <64>; 238 cache-sets = <512>; 239 next-level-cache = <&l3_0>; 240 }; 241 242 l3_0: l3-cache { 243 compatible = "cache"; 244 cache-level = <3>; 245 cache-size = <2097152>; 246 cache-line-size = <64>; 247 cache-sets = <2048>; 248 cache-unified; 249 }; 250 251 idle-states { 252 entry-method = "psci"; 253 cpu_ret_l: cpu-retention-l { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <55>; 258 exit-latency-us = <140>; 259 min-residency-us = <780>; 260 }; 261 cpu_ret_b: cpu-retention-b { 262 compatible = "arm,idle-state"; 263 arm,psci-suspend-param = <0x00010001>; 264 local-timer-stop; 265 entry-latency-us = <35>; 266 exit-latency-us = <145>; 267 min-residency-us = <720>; 268 }; 269 cpu_off_l: cpu-off-l { 270 compatible = "arm,idle-state"; 271 arm,psci-suspend-param = <0x01010002>; 272 local-timer-stop; 273 entry-latency-us = <60>; 274 exit-latency-us = <155>; 275 min-residency-us = <860>; 276 }; 277 cpu_off_b: cpu-off-b { 278 compatible = "arm,idle-state"; 279 arm,psci-suspend-param = <0x01010002>; 280 local-timer-stop; 281 entry-latency-us = <40>; 282 exit-latency-us = <155>; 283 min-residency-us = <780>; 284 }; 285 }; 286 }; 287 288 pmu-a55 { 289 compatible = "arm,cortex-a55-pmu"; 290 interrupt-parent = <&gic>; 291 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 292 }; 293 294 pmu-a76 { 295 compatible = "arm,cortex-a76-pmu"; 296 interrupt-parent = <&gic>; 297 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 298 }; 299 300 psci { 301 compatible = "arm,psci-1.0"; 302 method = "smc"; 303 }; 304 305 timer: timer { 306 compatible = "arm,armv8-timer"; 307 interrupt-parent = <&gic>; 308 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 309 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 310 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 311 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 312 clock-frequency = <13000000>; 313 }; 314 315 soc { 316 #address-cells = <2>; 317 #size-cells = <2>; 318 compatible = "simple-bus"; 319 ranges; 320 321 gic: interrupt-controller@c000000 { 322 compatible = "arm,gic-v3"; 323 #interrupt-cells = <4>; 324 #redistributor-regions = <1>; 325 interrupt-parent = <&gic>; 326 interrupt-controller; 327 reg = <0 0x0c000000 0 0x40000>, 328 <0 0x0c040000 0 0x200000>; 329 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 330 331 ppi-partitions { 332 ppi_cluster0: interrupt-partition-0 { 333 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 334 }; 335 ppi_cluster1: interrupt-partition-1 { 336 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 337 }; 338 }; 339 }; 340 341 topckgen: syscon@10000000 { 342 compatible = "mediatek,mt8192-topckgen", "syscon"; 343 reg = <0 0x10000000 0 0x1000>; 344 #clock-cells = <1>; 345 }; 346 347 infracfg: syscon@10001000 { 348 compatible = "mediatek,mt8192-infracfg", "syscon"; 349 reg = <0 0x10001000 0 0x1000>; 350 #clock-cells = <1>; 351 #reset-cells = <1>; 352 }; 353 354 pericfg: syscon@10003000 { 355 compatible = "mediatek,mt8192-pericfg", "syscon"; 356 reg = <0 0x10003000 0 0x1000>; 357 #clock-cells = <1>; 358 }; 359 360 pio: pinctrl@10005000 { 361 compatible = "mediatek,mt8192-pinctrl"; 362 reg = <0 0x10005000 0 0x1000>, 363 <0 0x11c20000 0 0x1000>, 364 <0 0x11d10000 0 0x1000>, 365 <0 0x11d30000 0 0x1000>, 366 <0 0x11d40000 0 0x1000>, 367 <0 0x11e20000 0 0x1000>, 368 <0 0x11e70000 0 0x1000>, 369 <0 0x11ea0000 0 0x1000>, 370 <0 0x11f20000 0 0x1000>, 371 <0 0x11f30000 0 0x1000>, 372 <0 0x1000b000 0 0x1000>; 373 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 374 "iocfg_bl", "iocfg_br", "iocfg_lm", 375 "iocfg_lb", "iocfg_rt", "iocfg_lt", 376 "iocfg_tl", "eint"; 377 gpio-controller; 378 #gpio-cells = <2>; 379 gpio-ranges = <&pio 0 0 220>; 380 interrupt-controller; 381 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 382 #interrupt-cells = <2>; 383 }; 384 385 scpsys: syscon@10006000 { 386 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 387 reg = <0 0x10006000 0 0x1000>; 388 389 /* System Power Manager */ 390 spm: power-controller { 391 compatible = "mediatek,mt8192-power-controller"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 #power-domain-cells = <1>; 395 396 /* power domain of the SoC */ 397 power-domain@MT8192_POWER_DOMAIN_AUDIO { 398 reg = <MT8192_POWER_DOMAIN_AUDIO>; 399 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 400 <&infracfg CLK_INFRA_AUDIO_26M_B>, 401 <&infracfg CLK_INFRA_AUDIO>; 402 clock-names = "audio", "audio1", "audio2"; 403 mediatek,infracfg = <&infracfg>; 404 #power-domain-cells = <0>; 405 }; 406 407 power-domain@MT8192_POWER_DOMAIN_CONN { 408 reg = <MT8192_POWER_DOMAIN_CONN>; 409 clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 410 clock-names = "conn"; 411 mediatek,infracfg = <&infracfg>; 412 #power-domain-cells = <0>; 413 }; 414 415 power-domain@MT8192_POWER_DOMAIN_MFG0 { 416 reg = <MT8192_POWER_DOMAIN_MFG0>; 417 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 418 clock-names = "mfg"; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 #power-domain-cells = <1>; 422 423 power-domain@MT8192_POWER_DOMAIN_MFG1 { 424 reg = <MT8192_POWER_DOMAIN_MFG1>; 425 mediatek,infracfg = <&infracfg>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 #power-domain-cells = <1>; 429 430 power-domain@MT8192_POWER_DOMAIN_MFG2 { 431 reg = <MT8192_POWER_DOMAIN_MFG2>; 432 #power-domain-cells = <0>; 433 }; 434 435 power-domain@MT8192_POWER_DOMAIN_MFG3 { 436 reg = <MT8192_POWER_DOMAIN_MFG3>; 437 #power-domain-cells = <0>; 438 }; 439 440 power-domain@MT8192_POWER_DOMAIN_MFG4 { 441 reg = <MT8192_POWER_DOMAIN_MFG4>; 442 #power-domain-cells = <0>; 443 }; 444 445 power-domain@MT8192_POWER_DOMAIN_MFG5 { 446 reg = <MT8192_POWER_DOMAIN_MFG5>; 447 #power-domain-cells = <0>; 448 }; 449 450 power-domain@MT8192_POWER_DOMAIN_MFG6 { 451 reg = <MT8192_POWER_DOMAIN_MFG6>; 452 #power-domain-cells = <0>; 453 }; 454 }; 455 }; 456 457 power-domain@MT8192_POWER_DOMAIN_DISP { 458 reg = <MT8192_POWER_DOMAIN_DISP>; 459 clocks = <&topckgen CLK_TOP_DISP_SEL>, 460 <&mmsys CLK_MM_SMI_INFRA>, 461 <&mmsys CLK_MM_SMI_COMMON>, 462 <&mmsys CLK_MM_SMI_GALS>, 463 <&mmsys CLK_MM_SMI_IOMMU>; 464 clock-names = "disp", "disp-0", "disp-1", "disp-2", 465 "disp-3"; 466 mediatek,infracfg = <&infracfg>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 #power-domain-cells = <1>; 470 471 power-domain@MT8192_POWER_DOMAIN_IPE { 472 reg = <MT8192_POWER_DOMAIN_IPE>; 473 clocks = <&topckgen CLK_TOP_IPE_SEL>, 474 <&ipesys CLK_IPE_LARB19>, 475 <&ipesys CLK_IPE_LARB20>, 476 <&ipesys CLK_IPE_SMI_SUBCOM>, 477 <&ipesys CLK_IPE_GALS>; 478 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 479 "ipe-3"; 480 mediatek,infracfg = <&infracfg>; 481 #power-domain-cells = <0>; 482 }; 483 484 power-domain@MT8192_POWER_DOMAIN_ISP { 485 reg = <MT8192_POWER_DOMAIN_ISP>; 486 clocks = <&topckgen CLK_TOP_IMG1_SEL>, 487 <&imgsys CLK_IMG_LARB9>, 488 <&imgsys CLK_IMG_GALS>; 489 clock-names = "isp", "isp-0", "isp-1"; 490 mediatek,infracfg = <&infracfg>; 491 #power-domain-cells = <0>; 492 }; 493 494 power-domain@MT8192_POWER_DOMAIN_ISP2 { 495 reg = <MT8192_POWER_DOMAIN_ISP2>; 496 clocks = <&topckgen CLK_TOP_IMG2_SEL>, 497 <&imgsys2 CLK_IMG2_LARB11>, 498 <&imgsys2 CLK_IMG2_GALS>; 499 clock-names = "isp2", "isp2-0", "isp2-1"; 500 mediatek,infracfg = <&infracfg>; 501 #power-domain-cells = <0>; 502 }; 503 504 power-domain@MT8192_POWER_DOMAIN_MDP { 505 reg = <MT8192_POWER_DOMAIN_MDP>; 506 clocks = <&topckgen CLK_TOP_MDP_SEL>, 507 <&mdpsys CLK_MDP_SMI0>; 508 clock-names = "mdp", "mdp-0"; 509 mediatek,infracfg = <&infracfg>; 510 #power-domain-cells = <0>; 511 }; 512 513 power-domain@MT8192_POWER_DOMAIN_VENC { 514 reg = <MT8192_POWER_DOMAIN_VENC>; 515 clocks = <&topckgen CLK_TOP_VENC_SEL>, 516 <&vencsys CLK_VENC_SET1_VENC>; 517 clock-names = "venc", "venc-0"; 518 mediatek,infracfg = <&infracfg>; 519 #power-domain-cells = <0>; 520 }; 521 522 power-domain@MT8192_POWER_DOMAIN_VDEC { 523 reg = <MT8192_POWER_DOMAIN_VDEC>; 524 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 525 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 526 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 527 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 528 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 529 mediatek,infracfg = <&infracfg>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 power-domain@MT8192_POWER_DOMAIN_VDEC2 { 535 reg = <MT8192_POWER_DOMAIN_VDEC2>; 536 clocks = <&vdecsys CLK_VDEC_VDEC>, 537 <&vdecsys CLK_VDEC_LAT>, 538 <&vdecsys CLK_VDEC_LARB1>; 539 clock-names = "vdec2-0", "vdec2-1", 540 "vdec2-2"; 541 #power-domain-cells = <0>; 542 }; 543 }; 544 545 power-domain@MT8192_POWER_DOMAIN_CAM { 546 reg = <MT8192_POWER_DOMAIN_CAM>; 547 clocks = <&topckgen CLK_TOP_CAM_SEL>, 548 <&camsys CLK_CAM_LARB13>, 549 <&camsys CLK_CAM_LARB14>, 550 <&camsys CLK_CAM_CCU_GALS>, 551 <&camsys CLK_CAM_CAM2MM_GALS>; 552 clock-names = "cam", "cam-0", "cam-1", "cam-2", 553 "cam-3"; 554 mediatek,infracfg = <&infracfg>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 #power-domain-cells = <1>; 558 559 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 560 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 561 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 562 clock-names = "cam_rawa-0"; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 567 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 568 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 569 clock-names = "cam_rawb-0"; 570 #power-domain-cells = <0>; 571 }; 572 573 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 574 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 575 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 576 clock-names = "cam_rawc-0"; 577 #power-domain-cells = <0>; 578 }; 579 }; 580 }; 581 }; 582 }; 583 584 watchdog: watchdog@10007000 { 585 compatible = "mediatek,mt8192-wdt"; 586 reg = <0 0x10007000 0 0x100>; 587 #reset-cells = <1>; 588 }; 589 590 apmixedsys: syscon@1000c000 { 591 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 592 reg = <0 0x1000c000 0 0x1000>; 593 #clock-cells = <1>; 594 }; 595 596 systimer: timer@10017000 { 597 compatible = "mediatek,mt8192-timer", 598 "mediatek,mt6765-timer"; 599 reg = <0 0x10017000 0 0x1000>; 600 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 601 clocks = <&clk13m>; 602 }; 603 604 pwrap: pwrap@10026000 { 605 compatible = "mediatek,mt6873-pwrap"; 606 reg = <0 0x10026000 0 0x1000>; 607 reg-names = "pwrap"; 608 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 609 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 610 <&infracfg CLK_INFRA_PMIC_TMR>; 611 clock-names = "spi", "wrap"; 612 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 613 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 614 }; 615 616 spmi: spmi@10027000 { 617 compatible = "mediatek,mt6873-spmi"; 618 reg = <0 0x10027000 0 0x000e00>, 619 <0 0x10029000 0 0x000100>; 620 reg-names = "pmif", "spmimst"; 621 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 622 <&infracfg CLK_INFRA_PMIC_TMR>, 623 <&topckgen CLK_TOP_SPMI_MST_SEL>; 624 clock-names = "pmif_sys_ck", 625 "pmif_tmr_ck", 626 "spmimst_clk_mux"; 627 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 628 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 629 }; 630 631 gce: mailbox@10228000 { 632 compatible = "mediatek,mt8192-gce"; 633 reg = <0 0x10228000 0 0x4000>; 634 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 635 #mbox-cells = <2>; 636 clocks = <&infracfg CLK_INFRA_GCE>; 637 clock-names = "gce"; 638 }; 639 640 scp_adsp: clock-controller@10720000 { 641 compatible = "mediatek,mt8192-scp_adsp"; 642 reg = <0 0x10720000 0 0x1000>; 643 #clock-cells = <1>; 644 /* power domain dependency not upstreamed */ 645 status = "fail"; 646 }; 647 648 uart0: serial@11002000 { 649 compatible = "mediatek,mt8192-uart", 650 "mediatek,mt6577-uart"; 651 reg = <0 0x11002000 0 0x1000>; 652 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 653 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 654 clock-names = "baud", "bus"; 655 status = "disabled"; 656 }; 657 658 uart1: serial@11003000 { 659 compatible = "mediatek,mt8192-uart", 660 "mediatek,mt6577-uart"; 661 reg = <0 0x11003000 0 0x1000>; 662 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 663 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 664 clock-names = "baud", "bus"; 665 status = "disabled"; 666 }; 667 668 imp_iic_wrap_c: clock-controller@11007000 { 669 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 670 reg = <0 0x11007000 0 0x1000>; 671 #clock-cells = <1>; 672 }; 673 674 spi0: spi@1100a000 { 675 compatible = "mediatek,mt8192-spi", 676 "mediatek,mt6765-spi"; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 reg = <0 0x1100a000 0 0x1000>; 680 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 681 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 682 <&topckgen CLK_TOP_SPI_SEL>, 683 <&infracfg CLK_INFRA_SPI0>; 684 clock-names = "parent-clk", "sel-clk", "spi-clk"; 685 status = "disabled"; 686 }; 687 688 pwm0: pwm@1100e000 { 689 compatible = "mediatek,mt8183-disp-pwm"; 690 reg = <0 0x1100e000 0 0x1000>; 691 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 692 #pwm-cells = <2>; 693 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 694 <&infracfg CLK_INFRA_DISP_PWM>; 695 clock-names = "main", "mm"; 696 status = "disabled"; 697 }; 698 699 spi1: spi@11010000 { 700 compatible = "mediatek,mt8192-spi", 701 "mediatek,mt6765-spi"; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 reg = <0 0x11010000 0 0x1000>; 705 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 706 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 707 <&topckgen CLK_TOP_SPI_SEL>, 708 <&infracfg CLK_INFRA_SPI1>; 709 clock-names = "parent-clk", "sel-clk", "spi-clk"; 710 status = "disabled"; 711 }; 712 713 spi2: spi@11012000 { 714 compatible = "mediatek,mt8192-spi", 715 "mediatek,mt6765-spi"; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 reg = <0 0x11012000 0 0x1000>; 719 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 720 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 721 <&topckgen CLK_TOP_SPI_SEL>, 722 <&infracfg CLK_INFRA_SPI2>; 723 clock-names = "parent-clk", "sel-clk", "spi-clk"; 724 status = "disabled"; 725 }; 726 727 spi3: spi@11013000 { 728 compatible = "mediatek,mt8192-spi", 729 "mediatek,mt6765-spi"; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 reg = <0 0x11013000 0 0x1000>; 733 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 734 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 735 <&topckgen CLK_TOP_SPI_SEL>, 736 <&infracfg CLK_INFRA_SPI3>; 737 clock-names = "parent-clk", "sel-clk", "spi-clk"; 738 status = "disabled"; 739 }; 740 741 spi4: spi@11018000 { 742 compatible = "mediatek,mt8192-spi", 743 "mediatek,mt6765-spi"; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 reg = <0 0x11018000 0 0x1000>; 747 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 748 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 749 <&topckgen CLK_TOP_SPI_SEL>, 750 <&infracfg CLK_INFRA_SPI4>; 751 clock-names = "parent-clk", "sel-clk", "spi-clk"; 752 status = "disabled"; 753 }; 754 755 spi5: spi@11019000 { 756 compatible = "mediatek,mt8192-spi", 757 "mediatek,mt6765-spi"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 reg = <0 0x11019000 0 0x1000>; 761 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 762 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 763 <&topckgen CLK_TOP_SPI_SEL>, 764 <&infracfg CLK_INFRA_SPI5>; 765 clock-names = "parent-clk", "sel-clk", "spi-clk"; 766 status = "disabled"; 767 }; 768 769 spi6: spi@1101d000 { 770 compatible = "mediatek,mt8192-spi", 771 "mediatek,mt6765-spi"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 reg = <0 0x1101d000 0 0x1000>; 775 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 776 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 777 <&topckgen CLK_TOP_SPI_SEL>, 778 <&infracfg CLK_INFRA_SPI6>; 779 clock-names = "parent-clk", "sel-clk", "spi-clk"; 780 status = "disabled"; 781 }; 782 783 spi7: spi@1101e000 { 784 compatible = "mediatek,mt8192-spi", 785 "mediatek,mt6765-spi"; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 reg = <0 0x1101e000 0 0x1000>; 789 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 790 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 791 <&topckgen CLK_TOP_SPI_SEL>, 792 <&infracfg CLK_INFRA_SPI7>; 793 clock-names = "parent-clk", "sel-clk", "spi-clk"; 794 status = "disabled"; 795 }; 796 797 scp: scp@10500000 { 798 compatible = "mediatek,mt8192-scp"; 799 reg = <0 0x10500000 0 0x100000>, 800 <0 0x10720000 0 0xe0000>, 801 <0 0x10700000 0 0x8000>; 802 reg-names = "sram", "cfg", "l1tcm"; 803 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 804 clocks = <&infracfg CLK_INFRA_SCPSYS>; 805 clock-names = "main"; 806 status = "disabled"; 807 }; 808 809 xhci: usb@11200000 { 810 compatible = "mediatek,mt8192-xhci", 811 "mediatek,mtk-xhci"; 812 reg = <0 0x11200000 0 0x1000>, 813 <0 0x11203e00 0 0x0100>; 814 reg-names = "mac", "ippc"; 815 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 816 interrupt-names = "host"; 817 phys = <&u2port0 PHY_TYPE_USB2>, 818 <&u3port0 PHY_TYPE_USB3>; 819 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 820 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 821 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 822 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 823 clocks = <&infracfg CLK_INFRA_SSUSB>, 824 <&apmixedsys CLK_APMIXED_USBPLL>, 825 <&clk26m>, 826 <&clk26m>, 827 <&infracfg CLK_INFRA_SSUSB_XHCI>; 828 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 829 "xhci_ck"; 830 wakeup-source; 831 mediatek,syscon-wakeup = <&pericfg 0x420 102>; 832 status = "disabled"; 833 }; 834 835 audsys: syscon@11210000 { 836 compatible = "mediatek,mt8192-audsys", "syscon"; 837 reg = <0 0x11210000 0 0x2000>; 838 #clock-cells = <1>; 839 840 afe: mt8192-afe-pcm { 841 compatible = "mediatek,mt8192-audio"; 842 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 843 resets = <&watchdog 17>; 844 reset-names = "audiosys"; 845 mediatek,apmixedsys = <&apmixedsys>; 846 mediatek,infracfg = <&infracfg>; 847 mediatek,topckgen = <&topckgen>; 848 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 849 clocks = <&audsys CLK_AUD_AFE>, 850 <&audsys CLK_AUD_DAC>, 851 <&audsys CLK_AUD_DAC_PREDIS>, 852 <&audsys CLK_AUD_ADC>, 853 <&audsys CLK_AUD_ADDA6_ADC>, 854 <&audsys CLK_AUD_22M>, 855 <&audsys CLK_AUD_24M>, 856 <&audsys CLK_AUD_APLL_TUNER>, 857 <&audsys CLK_AUD_APLL2_TUNER>, 858 <&audsys CLK_AUD_TDM>, 859 <&audsys CLK_AUD_TML>, 860 <&audsys CLK_AUD_NLE>, 861 <&audsys CLK_AUD_DAC_HIRES>, 862 <&audsys CLK_AUD_ADC_HIRES>, 863 <&audsys CLK_AUD_ADC_HIRES_TML>, 864 <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 865 <&audsys CLK_AUD_3RD_DAC>, 866 <&audsys CLK_AUD_3RD_DAC_PREDIS>, 867 <&audsys CLK_AUD_3RD_DAC_TML>, 868 <&audsys CLK_AUD_3RD_DAC_HIRES>, 869 <&infracfg CLK_INFRA_AUDIO>, 870 <&infracfg CLK_INFRA_AUDIO_26M_B>, 871 <&topckgen CLK_TOP_AUDIO_SEL>, 872 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 873 <&topckgen CLK_TOP_MAINPLL_D4_D4>, 874 <&topckgen CLK_TOP_AUD_1_SEL>, 875 <&topckgen CLK_TOP_APLL1>, 876 <&topckgen CLK_TOP_AUD_2_SEL>, 877 <&topckgen CLK_TOP_APLL2>, 878 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 879 <&topckgen CLK_TOP_APLL1_D4>, 880 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 881 <&topckgen CLK_TOP_APLL2_D4>, 882 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 883 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 884 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 885 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 886 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 887 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 888 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 889 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 890 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 891 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 892 <&topckgen CLK_TOP_APLL12_DIV0>, 893 <&topckgen CLK_TOP_APLL12_DIV1>, 894 <&topckgen CLK_TOP_APLL12_DIV2>, 895 <&topckgen CLK_TOP_APLL12_DIV3>, 896 <&topckgen CLK_TOP_APLL12_DIV4>, 897 <&topckgen CLK_TOP_APLL12_DIVB>, 898 <&topckgen CLK_TOP_APLL12_DIV5>, 899 <&topckgen CLK_TOP_APLL12_DIV6>, 900 <&topckgen CLK_TOP_APLL12_DIV7>, 901 <&topckgen CLK_TOP_APLL12_DIV8>, 902 <&topckgen CLK_TOP_APLL12_DIV9>, 903 <&topckgen CLK_TOP_AUDIO_H_SEL>, 904 <&clk26m>; 905 clock-names = "aud_afe_clk", 906 "aud_dac_clk", 907 "aud_dac_predis_clk", 908 "aud_adc_clk", 909 "aud_adda6_adc_clk", 910 "aud_apll22m_clk", 911 "aud_apll24m_clk", 912 "aud_apll1_tuner_clk", 913 "aud_apll2_tuner_clk", 914 "aud_tdm_clk", 915 "aud_tml_clk", 916 "aud_nle", 917 "aud_dac_hires_clk", 918 "aud_adc_hires_clk", 919 "aud_adc_hires_tml", 920 "aud_adda6_adc_hires_clk", 921 "aud_3rd_dac_clk", 922 "aud_3rd_dac_predis_clk", 923 "aud_3rd_dac_tml", 924 "aud_3rd_dac_hires_clk", 925 "aud_infra_clk", 926 "aud_infra_26m_clk", 927 "top_mux_audio", 928 "top_mux_audio_int", 929 "top_mainpll_d4_d4", 930 "top_mux_aud_1", 931 "top_apll1_ck", 932 "top_mux_aud_2", 933 "top_apll2_ck", 934 "top_mux_aud_eng1", 935 "top_apll1_d4", 936 "top_mux_aud_eng2", 937 "top_apll2_d4", 938 "top_i2s0_m_sel", 939 "top_i2s1_m_sel", 940 "top_i2s2_m_sel", 941 "top_i2s3_m_sel", 942 "top_i2s4_m_sel", 943 "top_i2s5_m_sel", 944 "top_i2s6_m_sel", 945 "top_i2s7_m_sel", 946 "top_i2s8_m_sel", 947 "top_i2s9_m_sel", 948 "top_apll12_div0", 949 "top_apll12_div1", 950 "top_apll12_div2", 951 "top_apll12_div3", 952 "top_apll12_div4", 953 "top_apll12_divb", 954 "top_apll12_div5", 955 "top_apll12_div6", 956 "top_apll12_div7", 957 "top_apll12_div8", 958 "top_apll12_div9", 959 "top_mux_audio_h", 960 "top_clk26m_clk"; 961 }; 962 }; 963 964 pcie: pcie@11230000 { 965 compatible = "mediatek,mt8192-pcie"; 966 device_type = "pci"; 967 reg = <0 0x11230000 0 0x2000>; 968 reg-names = "pcie-mac"; 969 #address-cells = <3>; 970 #size-cells = <2>; 971 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 972 <&infracfg CLK_INFRA_PCIE_TL_26M>, 973 <&infracfg CLK_INFRA_PCIE_TL_96M>, 974 <&infracfg CLK_INFRA_PCIE_TL_32K>, 975 <&infracfg CLK_INFRA_PCIE_PERI_26M>, 976 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 977 clock-names = "pl_250m", "tl_26m", "tl_96m", 978 "tl_32k", "peri_26m", "top_133m"; 979 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 980 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 981 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 982 bus-range = <0x00 0xff>; 983 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 984 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 985 #interrupt-cells = <1>; 986 interrupt-map-mask = <0 0 0 7>; 987 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 988 <0 0 0 2 &pcie_intc0 1>, 989 <0 0 0 3 &pcie_intc0 2>, 990 <0 0 0 4 &pcie_intc0 3>; 991 992 pcie_intc0: interrupt-controller { 993 interrupt-controller; 994 #address-cells = <0>; 995 #interrupt-cells = <1>; 996 }; 997 }; 998 999 nor_flash: spi@11234000 { 1000 compatible = "mediatek,mt8192-nor"; 1001 reg = <0 0x11234000 0 0xe0>; 1002 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 1003 clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 1004 <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 1005 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 1006 clock-names = "spi", "sf", "axi"; 1007 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 1008 assigned-clock-parents = <&clk26m>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 status = "disabled"; 1012 }; 1013 1014 efuse: efuse@11c10000 { 1015 compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 1016 reg = <0 0x11c10000 0 0x1000>; 1017 #address-cells = <1>; 1018 #size-cells = <1>; 1019 1020 lvts_e_data1: data1@1c0 { 1021 reg = <0x1c0 0x58>; 1022 }; 1023 1024 svs_calibration: calib@580 { 1025 reg = <0x580 0x68>; 1026 }; 1027 }; 1028 1029 i2c3: i2c@11cb0000 { 1030 compatible = "mediatek,mt8192-i2c"; 1031 reg = <0 0x11cb0000 0 0x1000>, 1032 <0 0x10217300 0 0x80>; 1033 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1034 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 1035 <&infracfg CLK_INFRA_AP_DMA>; 1036 clock-names = "main", "dma"; 1037 clock-div = <1>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 status = "disabled"; 1041 }; 1042 1043 imp_iic_wrap_e: clock-controller@11cb1000 { 1044 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 1045 reg = <0 0x11cb1000 0 0x1000>; 1046 #clock-cells = <1>; 1047 }; 1048 1049 i2c7: i2c@11d00000 { 1050 compatible = "mediatek,mt8192-i2c"; 1051 reg = <0 0x11d00000 0 0x1000>, 1052 <0 0x10217600 0 0x180>; 1053 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1054 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1055 <&infracfg CLK_INFRA_AP_DMA>; 1056 clock-names = "main", "dma"; 1057 clock-div = <1>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 i2c8: i2c@11d01000 { 1064 compatible = "mediatek,mt8192-i2c"; 1065 reg = <0 0x11d01000 0 0x1000>, 1066 <0 0x10217780 0 0x180>; 1067 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1068 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 1069 <&infracfg CLK_INFRA_AP_DMA>; 1070 clock-names = "main", "dma"; 1071 clock-div = <1>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 1077 i2c9: i2c@11d02000 { 1078 compatible = "mediatek,mt8192-i2c"; 1079 reg = <0 0x11d02000 0 0x1000>, 1080 <0 0x10217900 0 0x180>; 1081 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1082 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 1083 <&infracfg CLK_INFRA_AP_DMA>; 1084 clock-names = "main", "dma"; 1085 clock-div = <1>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 1091 imp_iic_wrap_s: clock-controller@11d03000 { 1092 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 1093 reg = <0 0x11d03000 0 0x1000>; 1094 #clock-cells = <1>; 1095 }; 1096 1097 i2c1: i2c@11d20000 { 1098 compatible = "mediatek,mt8192-i2c"; 1099 reg = <0 0x11d20000 0 0x1000>, 1100 <0 0x10217100 0 0x80>; 1101 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1102 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 1103 <&infracfg CLK_INFRA_AP_DMA>; 1104 clock-names = "main", "dma"; 1105 clock-div = <1>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c2: i2c@11d21000 { 1112 compatible = "mediatek,mt8192-i2c"; 1113 reg = <0 0x11d21000 0 0x1000>, 1114 <0 0x10217180 0 0x180>; 1115 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 1116 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 1117 <&infracfg CLK_INFRA_AP_DMA>; 1118 clock-names = "main", "dma"; 1119 clock-div = <1>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 status = "disabled"; 1123 }; 1124 1125 i2c4: i2c@11d22000 { 1126 compatible = "mediatek,mt8192-i2c"; 1127 reg = <0 0x11d22000 0 0x1000>, 1128 <0 0x10217380 0 0x180>; 1129 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1130 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 1131 <&infracfg CLK_INFRA_AP_DMA>; 1132 clock-names = "main", "dma"; 1133 clock-div = <1>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 imp_iic_wrap_ws: clock-controller@11d23000 { 1140 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 1141 reg = <0 0x11d23000 0 0x1000>; 1142 #clock-cells = <1>; 1143 }; 1144 1145 i2c5: i2c@11e00000 { 1146 compatible = "mediatek,mt8192-i2c"; 1147 reg = <0 0x11e00000 0 0x1000>, 1148 <0 0x10217500 0 0x80>; 1149 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1150 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 1151 <&infracfg CLK_INFRA_AP_DMA>; 1152 clock-names = "main", "dma"; 1153 clock-div = <1>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 imp_iic_wrap_w: clock-controller@11e01000 { 1160 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 1161 reg = <0 0x11e01000 0 0x1000>; 1162 #clock-cells = <1>; 1163 }; 1164 1165 u3phy0: t-phy@11e40000 { 1166 compatible = "mediatek,mt8192-tphy", 1167 "mediatek,generic-tphy-v2"; 1168 #address-cells = <1>; 1169 #size-cells = <1>; 1170 ranges = <0x0 0x0 0x11e40000 0x1000>; 1171 1172 u2port0: usb-phy@0 { 1173 reg = <0x0 0x700>; 1174 clocks = <&clk26m>; 1175 clock-names = "ref"; 1176 #phy-cells = <1>; 1177 }; 1178 1179 u3port0: usb-phy@700 { 1180 reg = <0x700 0x900>; 1181 clocks = <&clk26m>; 1182 clock-names = "ref"; 1183 #phy-cells = <1>; 1184 }; 1185 }; 1186 1187 mipi_tx0: dsi-phy@11e50000 { 1188 compatible = "mediatek,mt8183-mipi-tx"; 1189 reg = <0 0x11e50000 0 0x1000>; 1190 clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 1191 #clock-cells = <0>; 1192 #phy-cells = <0>; 1193 clock-output-names = "mipi_tx0_pll"; 1194 status = "disabled"; 1195 }; 1196 1197 i2c0: i2c@11f00000 { 1198 compatible = "mediatek,mt8192-i2c"; 1199 reg = <0 0x11f00000 0 0x1000>, 1200 <0 0x10217080 0 0x80>; 1201 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1202 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 1203 <&infracfg CLK_INFRA_AP_DMA>; 1204 clock-names = "main", "dma"; 1205 clock-div = <1>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c6: i2c@11f01000 { 1212 compatible = "mediatek,mt8192-i2c"; 1213 reg = <0 0x11f01000 0 0x1000>, 1214 <0 0x10217580 0 0x80>; 1215 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1216 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 1217 <&infracfg CLK_INFRA_AP_DMA>; 1218 clock-names = "main", "dma"; 1219 clock-div = <1>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 imp_iic_wrap_n: clock-controller@11f02000 { 1226 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 1227 reg = <0 0x11f02000 0 0x1000>; 1228 #clock-cells = <1>; 1229 }; 1230 1231 msdc_top: clock-controller@11f10000 { 1232 compatible = "mediatek,mt8192-msdc_top"; 1233 reg = <0 0x11f10000 0 0x1000>; 1234 #clock-cells = <1>; 1235 }; 1236 1237 mmc0: mmc@11f60000 { 1238 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1239 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1240 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1241 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1242 <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1243 <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1244 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1245 <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1246 <&msdc_top CLK_MSDC_TOP_AXI>, 1247 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1248 clock-names = "source", "hclk", "source_cg", "sys_cg", 1249 "pclk_cg", "axi_cg", "ahb_cg"; 1250 status = "disabled"; 1251 }; 1252 1253 mmc1: mmc@11f70000 { 1254 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1255 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1256 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1257 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1258 <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1259 <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1260 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1261 <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1262 <&msdc_top CLK_MSDC_TOP_AXI>, 1263 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1264 clock-names = "source", "hclk", "source_cg", "sys_cg", 1265 "pclk_cg", "axi_cg", "ahb_cg"; 1266 status = "disabled"; 1267 }; 1268 1269 mfgcfg: clock-controller@13fbf000 { 1270 compatible = "mediatek,mt8192-mfgcfg"; 1271 reg = <0 0x13fbf000 0 0x1000>; 1272 #clock-cells = <1>; 1273 }; 1274 1275 mmsys: syscon@14000000 { 1276 compatible = "mediatek,mt8192-mmsys", "syscon"; 1277 reg = <0 0x14000000 0 0x1000>; 1278 #clock-cells = <1>; 1279 #reset-cells = <1>; 1280 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1281 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1282 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1283 }; 1284 1285 mutex: mutex@14001000 { 1286 compatible = "mediatek,mt8192-disp-mutex"; 1287 reg = <0 0x14001000 0 0x1000>; 1288 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1289 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1290 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1291 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1292 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1293 }; 1294 1295 smi_common: smi@14002000 { 1296 compatible = "mediatek,mt8192-smi-common"; 1297 reg = <0 0x14002000 0 0x1000>; 1298 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1299 <&mmsys CLK_MM_SMI_INFRA>, 1300 <&mmsys CLK_MM_SMI_GALS>, 1301 <&mmsys CLK_MM_SMI_GALS>; 1302 clock-names = "apb", "smi", "gals0", "gals1"; 1303 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1304 }; 1305 1306 larb0: larb@14003000 { 1307 compatible = "mediatek,mt8192-smi-larb"; 1308 reg = <0 0x14003000 0 0x1000>; 1309 mediatek,larb-id = <0>; 1310 mediatek,smi = <&smi_common>; 1311 clocks = <&clk26m>, <&clk26m>; 1312 clock-names = "apb", "smi"; 1313 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1314 }; 1315 1316 larb1: larb@14004000 { 1317 compatible = "mediatek,mt8192-smi-larb"; 1318 reg = <0 0x14004000 0 0x1000>; 1319 mediatek,larb-id = <1>; 1320 mediatek,smi = <&smi_common>; 1321 clocks = <&clk26m>, <&clk26m>; 1322 clock-names = "apb", "smi"; 1323 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1324 }; 1325 1326 ovl0: ovl@14005000 { 1327 compatible = "mediatek,mt8192-disp-ovl"; 1328 reg = <0 0x14005000 0 0x1000>; 1329 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1330 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1331 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1332 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1333 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1334 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1335 }; 1336 1337 ovl_2l0: ovl@14006000 { 1338 compatible = "mediatek,mt8192-disp-ovl-2l"; 1339 reg = <0 0x14006000 0 0x1000>; 1340 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1341 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1342 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1343 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1344 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1345 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1346 }; 1347 1348 rdma0: rdma@14007000 { 1349 compatible = "mediatek,mt8192-disp-rdma", 1350 "mediatek,mt8183-disp-rdma"; 1351 reg = <0 0x14007000 0 0x1000>; 1352 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1353 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1354 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1355 mediatek,rdma-fifo-size = <5120>; 1356 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1357 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1358 }; 1359 1360 color0: color@14009000 { 1361 compatible = "mediatek,mt8192-disp-color", 1362 "mediatek,mt8173-disp-color"; 1363 reg = <0 0x14009000 0 0x1000>; 1364 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1365 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1366 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1367 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1368 }; 1369 1370 ccorr0: ccorr@1400a000 { 1371 compatible = "mediatek,mt8192-disp-ccorr"; 1372 reg = <0 0x1400a000 0 0x1000>; 1373 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1374 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1375 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1376 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1377 }; 1378 1379 aal0: aal@1400b000 { 1380 compatible = "mediatek,mt8192-disp-aal", 1381 "mediatek,mt8183-disp-aal"; 1382 reg = <0 0x1400b000 0 0x1000>; 1383 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1384 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1385 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1386 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1387 }; 1388 1389 gamma0: gamma@1400c000 { 1390 compatible = "mediatek,mt8192-disp-gamma", 1391 "mediatek,mt8183-disp-gamma"; 1392 reg = <0 0x1400c000 0 0x1000>; 1393 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1394 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1395 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1396 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1397 }; 1398 1399 postmask0: postmask@1400d000 { 1400 compatible = "mediatek,mt8192-disp-postmask"; 1401 reg = <0 0x1400d000 0 0x1000>; 1402 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1403 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1404 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1405 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1406 }; 1407 1408 dither0: dither@1400e000 { 1409 compatible = "mediatek,mt8192-disp-dither", 1410 "mediatek,mt8183-disp-dither"; 1411 reg = <0 0x1400e000 0 0x1000>; 1412 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1413 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1414 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1415 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1416 }; 1417 1418 dsi0: dsi@14010000 { 1419 compatible = "mediatek,mt8183-dsi"; 1420 reg = <0 0x14010000 0 0x1000>; 1421 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1422 clocks = <&mmsys CLK_MM_DSI0>, 1423 <&mmsys CLK_MM_DSI_DSI0>, 1424 <&mipi_tx0>; 1425 clock-names = "engine", "digital", "hs"; 1426 phys = <&mipi_tx0>; 1427 phy-names = "dphy"; 1428 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1429 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 1430 status = "disabled"; 1431 1432 port { 1433 dsi_out: endpoint { }; 1434 }; 1435 }; 1436 1437 ovl_2l2: ovl@14014000 { 1438 compatible = "mediatek,mt8192-disp-ovl-2l"; 1439 reg = <0 0x14014000 0 0x1000>; 1440 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1441 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1442 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1443 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1444 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1445 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1446 }; 1447 1448 rdma4: rdma@14015000 { 1449 compatible = "mediatek,mt8192-disp-rdma", 1450 "mediatek,mt8183-disp-rdma"; 1451 reg = <0 0x14015000 0 0x1000>; 1452 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1453 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1454 clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1455 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1456 mediatek,rdma-fifo-size = <2048>; 1457 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1458 }; 1459 1460 dpi0: dpi@14016000 { 1461 compatible = "mediatek,mt8192-dpi"; 1462 reg = <0 0x14016000 0 0x1000>; 1463 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1464 clocks = <&mmsys CLK_MM_DPI_DPI0>, 1465 <&mmsys CLK_MM_DISP_DPI0>, 1466 <&apmixedsys CLK_APMIXED_TVDPLL>; 1467 clock-names = "pixel", "engine", "pll"; 1468 status = "disabled"; 1469 }; 1470 1471 iommu0: m4u@1401d000 { 1472 compatible = "mediatek,mt8192-m4u"; 1473 reg = <0 0x1401d000 0 0x1000>; 1474 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 1475 <&larb4>, <&larb5>, <&larb7>, 1476 <&larb9>, <&larb11>, <&larb13>, 1477 <&larb14>, <&larb16>, <&larb17>, 1478 <&larb18>, <&larb19>, <&larb20>; 1479 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1480 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1481 clock-names = "bclk"; 1482 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1483 #iommu-cells = <1>; 1484 }; 1485 1486 imgsys: clock-controller@15020000 { 1487 compatible = "mediatek,mt8192-imgsys"; 1488 reg = <0 0x15020000 0 0x1000>; 1489 #clock-cells = <1>; 1490 }; 1491 1492 larb9: larb@1502e000 { 1493 compatible = "mediatek,mt8192-smi-larb"; 1494 reg = <0 0x1502e000 0 0x1000>; 1495 mediatek,larb-id = <9>; 1496 mediatek,smi = <&smi_common>; 1497 clocks = <&imgsys CLK_IMG_LARB9>, 1498 <&imgsys CLK_IMG_LARB9>; 1499 clock-names = "apb", "smi"; 1500 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 1501 }; 1502 1503 imgsys2: clock-controller@15820000 { 1504 compatible = "mediatek,mt8192-imgsys2"; 1505 reg = <0 0x15820000 0 0x1000>; 1506 #clock-cells = <1>; 1507 }; 1508 1509 larb11: larb@1582e000 { 1510 compatible = "mediatek,mt8192-smi-larb"; 1511 reg = <0 0x1582e000 0 0x1000>; 1512 mediatek,larb-id = <11>; 1513 mediatek,smi = <&smi_common>; 1514 clocks = <&imgsys2 CLK_IMG2_LARB11>, 1515 <&imgsys2 CLK_IMG2_LARB11>; 1516 clock-names = "apb", "smi"; 1517 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 1518 }; 1519 1520 larb5: larb@1600d000 { 1521 compatible = "mediatek,mt8192-smi-larb"; 1522 reg = <0 0x1600d000 0 0x1000>; 1523 mediatek,larb-id = <5>; 1524 mediatek,smi = <&smi_common>; 1525 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1526 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1527 clock-names = "apb", "smi"; 1528 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1529 }; 1530 1531 vdecsys_soc: clock-controller@1600f000 { 1532 compatible = "mediatek,mt8192-vdecsys_soc"; 1533 reg = <0 0x1600f000 0 0x1000>; 1534 #clock-cells = <1>; 1535 }; 1536 1537 larb4: larb@1602e000 { 1538 compatible = "mediatek,mt8192-smi-larb"; 1539 reg = <0 0x1602e000 0 0x1000>; 1540 mediatek,larb-id = <4>; 1541 mediatek,smi = <&smi_common>; 1542 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 1543 <&vdecsys CLK_VDEC_SOC_LARB1>; 1544 clock-names = "apb", "smi"; 1545 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1546 }; 1547 1548 vdecsys: clock-controller@1602f000 { 1549 compatible = "mediatek,mt8192-vdecsys"; 1550 reg = <0 0x1602f000 0 0x1000>; 1551 #clock-cells = <1>; 1552 }; 1553 1554 vencsys: clock-controller@17000000 { 1555 compatible = "mediatek,mt8192-vencsys"; 1556 reg = <0 0x17000000 0 0x1000>; 1557 #clock-cells = <1>; 1558 }; 1559 1560 larb7: larb@17010000 { 1561 compatible = "mediatek,mt8192-smi-larb"; 1562 reg = <0 0x17010000 0 0x1000>; 1563 mediatek,larb-id = <7>; 1564 mediatek,smi = <&smi_common>; 1565 clocks = <&vencsys CLK_VENC_SET0_LARB>, 1566 <&vencsys CLK_VENC_SET1_VENC>; 1567 clock-names = "apb", "smi"; 1568 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1569 }; 1570 1571 vcodec_enc: vcodec@17020000 { 1572 compatible = "mediatek,mt8192-vcodec-enc"; 1573 reg = <0 0x17020000 0 0x2000>; 1574 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1575 <&iommu0 M4U_PORT_L7_VENC_REC>, 1576 <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1577 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1578 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1579 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1580 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1581 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1582 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1583 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1584 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1585 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1586 mediatek,scp = <&scp>; 1587 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1588 clocks = <&vencsys CLK_VENC_SET1_VENC>; 1589 clock-names = "venc-set1"; 1590 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1591 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1592 }; 1593 1594 camsys: clock-controller@1a000000 { 1595 compatible = "mediatek,mt8192-camsys"; 1596 reg = <0 0x1a000000 0 0x1000>; 1597 #clock-cells = <1>; 1598 }; 1599 1600 larb13: larb@1a001000 { 1601 compatible = "mediatek,mt8192-smi-larb"; 1602 reg = <0 0x1a001000 0 0x1000>; 1603 mediatek,larb-id = <13>; 1604 mediatek,smi = <&smi_common>; 1605 clocks = <&camsys CLK_CAM_CAM>, 1606 <&camsys CLK_CAM_LARB13>; 1607 clock-names = "apb", "smi"; 1608 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1609 }; 1610 1611 larb14: larb@1a002000 { 1612 compatible = "mediatek,mt8192-smi-larb"; 1613 reg = <0 0x1a002000 0 0x1000>; 1614 mediatek,larb-id = <14>; 1615 mediatek,smi = <&smi_common>; 1616 clocks = <&camsys CLK_CAM_CAM>, 1617 <&camsys CLK_CAM_LARB14>; 1618 clock-names = "apb", "smi"; 1619 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1620 }; 1621 1622 larb16: larb@1a00f000 { 1623 compatible = "mediatek,mt8192-smi-larb"; 1624 reg = <0 0x1a00f000 0 0x1000>; 1625 mediatek,larb-id = <16>; 1626 mediatek,smi = <&smi_common>; 1627 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 1628 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1629 clock-names = "apb", "smi"; 1630 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 1631 }; 1632 1633 larb17: larb@1a010000 { 1634 compatible = "mediatek,mt8192-smi-larb"; 1635 reg = <0 0x1a010000 0 0x1000>; 1636 mediatek,larb-id = <17>; 1637 mediatek,smi = <&smi_common>; 1638 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 1639 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1640 clock-names = "apb", "smi"; 1641 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 1642 }; 1643 1644 larb18: larb@1a011000 { 1645 compatible = "mediatek,mt8192-smi-larb"; 1646 reg = <0 0x1a011000 0 0x1000>; 1647 mediatek,larb-id = <18>; 1648 mediatek,smi = <&smi_common>; 1649 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 1650 <&camsys_rawc CLK_CAM_RAWC_CAM>; 1651 clock-names = "apb", "smi"; 1652 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 1653 }; 1654 1655 camsys_rawa: clock-controller@1a04f000 { 1656 compatible = "mediatek,mt8192-camsys_rawa"; 1657 reg = <0 0x1a04f000 0 0x1000>; 1658 #clock-cells = <1>; 1659 }; 1660 1661 camsys_rawb: clock-controller@1a06f000 { 1662 compatible = "mediatek,mt8192-camsys_rawb"; 1663 reg = <0 0x1a06f000 0 0x1000>; 1664 #clock-cells = <1>; 1665 }; 1666 1667 camsys_rawc: clock-controller@1a08f000 { 1668 compatible = "mediatek,mt8192-camsys_rawc"; 1669 reg = <0 0x1a08f000 0 0x1000>; 1670 #clock-cells = <1>; 1671 }; 1672 1673 ipesys: clock-controller@1b000000 { 1674 compatible = "mediatek,mt8192-ipesys"; 1675 reg = <0 0x1b000000 0 0x1000>; 1676 #clock-cells = <1>; 1677 }; 1678 1679 larb20: larb@1b00f000 { 1680 compatible = "mediatek,mt8192-smi-larb"; 1681 reg = <0 0x1b00f000 0 0x1000>; 1682 mediatek,larb-id = <20>; 1683 mediatek,smi = <&smi_common>; 1684 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1685 <&ipesys CLK_IPE_LARB20>; 1686 clock-names = "apb", "smi"; 1687 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1688 }; 1689 1690 larb19: larb@1b10f000 { 1691 compatible = "mediatek,mt8192-smi-larb"; 1692 reg = <0 0x1b10f000 0 0x1000>; 1693 mediatek,larb-id = <19>; 1694 mediatek,smi = <&smi_common>; 1695 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1696 <&ipesys CLK_IPE_LARB19>; 1697 clock-names = "apb", "smi"; 1698 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1699 }; 1700 1701 mdpsys: clock-controller@1f000000 { 1702 compatible = "mediatek,mt8192-mdpsys"; 1703 reg = <0 0x1f000000 0 0x1000>; 1704 #clock-cells = <1>; 1705 }; 1706 1707 larb2: larb@1f002000 { 1708 compatible = "mediatek,mt8192-smi-larb"; 1709 reg = <0 0x1f002000 0 0x1000>; 1710 mediatek,larb-id = <2>; 1711 mediatek,smi = <&smi_common>; 1712 clocks = <&mdpsys CLK_MDP_SMI0>, 1713 <&mdpsys CLK_MDP_SMI0>; 1714 clock-names = "apb", "smi"; 1715 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 1716 }; 1717 }; 1718}; 1719