1// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
2/*
3 * Copyright (c) 2019-2020, Arm Limited.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8/ {
9	interrupt-parent = <&gic>;
10	#address-cells = <2>;
11	#size-cells = <2>;
12
13	cpus {
14		#address-cells = <2>;
15		#size-cells = <0>;
16
17		cpu0@0 {
18			compatible = "arm,neoverse-n1";
19			reg = <0x0 0x0>;
20			device_type = "cpu";
21			enable-method = "psci";
22			numa-node-id = <0>;
23		};
24		cpu1@100 {
25			compatible = "arm,neoverse-n1";
26			reg = <0x0 0x100>;
27			device_type = "cpu";
28			enable-method = "psci";
29			numa-node-id = <0>;
30		};
31		cpu2@10000 {
32			compatible = "arm,neoverse-n1";
33			reg = <0x0 0x10000>;
34			device_type = "cpu";
35			enable-method = "psci";
36			numa-node-id = <0>;
37		};
38		cpu3@10100 {
39			compatible = "arm,neoverse-n1";
40			reg = <0x0 0x10100>;
41			device_type = "cpu";
42			enable-method = "psci";
43			numa-node-id = <0>;
44		};
45	};
46
47	pmu {
48		compatible = "arm,armv8-pmuv3";
49		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
50	};
51
52	spe-pmu {
53		compatible = "arm,statistical-profiling-extension-v1";
54		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
55	};
56
57	psci {
58		compatible = "arm,psci-0.2";
59		method = "smc";
60	};
61
62	timer {
63		compatible = "arm,armv8-timer";
64		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
65			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
66			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
67			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
68	};
69
70	soc_refclk100mhz: refclk100mhz {
71		compatible = "fixed-clock";
72		#clock-cells = <0>;
73		clock-frequency = <100000000>;
74		clock-output-names = "apb_pclk";
75	};
76
77	soc_uartclk:  uartclk {
78		compatible = "fixed-clock";
79		#clock-cells = <0>;
80		clock-frequency = <50000000>;
81		clock-output-names = "uartclk";
82	};
83
84	soc {
85		compatible = "arm,neoverse-n1-soc", "simple-bus";
86		#address-cells = <2>;
87		#size-cells = <2>;
88		ranges;
89
90		gic: interrupt-controller@30000000 {
91			compatible = "arm,gic-v3";
92			#address-cells = <2>;
93			#interrupt-cells = <3>;
94			#size-cells = <2>;
95			ranges;
96			interrupt-controller;
97			reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
98				<0x0 0x300c0000 0 0x80000>;	/* GICR */
99
100			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
101
102			its1: its@30040000 {
103				compatible = "arm,gic-v3-its";
104				msi-controller;
105				#msi-cells = <1>;
106				reg = <0x0 0x30040000 0x0 0x20000>;
107			};
108
109			its2: its@30060000 {
110				compatible = "arm,gic-v3-its";
111				msi-controller;
112				#msi-cells = <1>;
113				reg = <0x0 0x30060000 0x0 0x20000>;
114			};
115
116			its_ccix: its@30080000 {
117				compatible = "arm,gic-v3-its";
118				msi-controller;
119				#msi-cells = <1>;
120				reg = <0x0 0x30080000 0x0 0x20000>;
121			};
122
123			its_pcie: its@300a0000 {
124				compatible = "arm,gic-v3-its";
125				msi-controller;
126				#msi-cells = <1>;
127				reg = <0x0 0x300a0000 0x0 0x20000>;
128			};
129		};
130
131		smmu_ccix: iommu@4f000000 {
132			compatible = "arm,smmu-v3";
133			reg = <0 0x4f000000 0 0x40000>;
134			interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
135					<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
136					<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
137			interrupt-names = "eventq", "cmdq-sync", "gerror";
138			msi-parent = <&its1 0>;
139			#iommu-cells = <1>;
140			dma-coherent;
141		};
142
143		smmu_pcie: iommu@4f400000 {
144			compatible = "arm,smmu-v3";
145			reg = <0 0x4f400000 0 0x40000>;
146			interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
147					<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
148					<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>;
149			interrupt-names = "eventq", "cmdq-sync", "gerror";
150			msi-parent = <&its2 0>;
151			#iommu-cells = <1>;
152			dma-coherent;
153		};
154
155		pcie_ctlr: pcie@70000000 {
156			compatible = "arm,n1sdp-pcie";
157			device_type = "pci";
158			reg = <0 0x70000000 0 0x1200000>;
159			bus-range = <0 17>;
160			linux,pci-domain = <0>;
161			#address-cells = <3>;
162			#size-cells = <2>;
163			dma-coherent;
164			ranges = <0x01000000 0x00 0x00000000 0x00 0x75200000 0x00 0x00010000>,
165				 <0x02000000 0x00 0x71200000 0x00 0x71200000 0x00 0x04000000>,
166				 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x20 0x00000000>;
167			#interrupt-cells = <1>;
168			interrupt-map-mask = <0 0 0 7>;
169			interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
170				<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
171				<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
172				<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
173			msi-map = <0 &its_pcie 0 0x10000>;
174			iommu-map = <0 &smmu_pcie 0 0x10000>;
175			status = "disabled";
176		};
177
178		ccix_pcie_ctlr: pcie@68000000 {
179			compatible = "arm,n1sdp-pcie";
180			device_type = "pci";
181			reg = <0 0x68000000 0 0x1200000>;
182			bus-range = <0 17>;
183			linux,pci-domain = <1>;
184			#address-cells = <3>;
185			#size-cells = <2>;
186			dma-coherent;
187			ranges = <0x01000000 0x00 0x00000000 0x00 0x6d200000 0x00 0x00010000>,
188				 <0x02000000 0x00 0x69200000 0x00 0x69200000 0x00 0x04000000>,
189				 <0x42000000 0x29 0x00000000 0x29 0x00000000 0x20 0x00000000>;
190			#interrupt-cells = <1>;
191			interrupt-map-mask = <0 0 0 7>;
192			interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
193				<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
194				<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
195				<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
196			msi-map = <0 &its_ccix 0 0x10000>;
197			iommu-map = <0 &smmu_ccix 0 0x10000>;
198			status = "disabled";
199		};
200
201		soc_uart0: serial@2a400000 {
202			compatible = "arm,pl011", "arm,primecell";
203			reg = <0x0 0x2a400000 0x0 0x1000>;
204			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
205			clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
206			clock-names = "uartclk", "apb_pclk";
207			status = "disabled";
208		};
209	};
210};
211